Analog Devices ADSP-21020 User Manual

EXTERNAL
ADDRESS
BUSES

PROGRAM

SEQUENCER

EXTERNAL
DATA
BUSES

DATA ADDRESS

GENERATORS

DAG 1 DAG 2

PROGRAM MEMORY ADDRESS

PROGRAM MEMORY DATA

DATA MEMORY DATA

DATA MEMORY ADDRESS

INSTRUCTION

CACHE

ARITHMETIC UNITS

SHIFTERMULTIPLIER

ALU

REGISTER FILE

TIMER

JTAG TEST

& EMULATION

32/40-Bit IEEE Floating-Point

a

FEATURES
Superscalar IEEE Floating-Point Processor
Off-Chip Harvard Architecture Maximizes Signal

Processing Performance

30 ns, 33.3 MIPS Instruction Rate, Single-Cycle

Execution
100 MFLOPS Peak, 66 MFLOPS Sustained Performance
1024-Point Complex FFT Benchmark: 0.58 ms
Divide (y/x): 180 ns
Inverse Square Root (1/√
32-Bit Single-Precision and 40-Bit Extended-Precision

IEEE Floating-Point Data Formats
32-Bit Fixed-Point Formats, Integer and Fractional,

with 80-Bit Accumulators
IEEE Exception Handling with Interrupt on Exception
Three Independent Computation Units: Multiplier,

ALU, and Barrel Shifter
Dual Data Address Generators with Indirect, Immedi-

ate, Modulo, and Bit Reverse Addressing Modes
Two Off-Chip Memory Transfers in Parallel with

Instruction Fetch and Single-Cycle Multiply & ALU

Operations
Multiply with Add & Subtract for FFT Butterfly

Computation
Efficient Program Sequencing with Zero-Overhead

Looping: Single-Cycle Loop Setup
Single-Cycle Register File Context Switch
15 (or 25) ns External RAM Access Time for Zero-Wait-

State, 30 (or 40) ns Instruction Execution
IEEE JTAG Standard 1149.1 Test Access Port and

On-Chip Emulation Circuitry
223-Pin PGA Package (Ceramic)

GENERAL DESCRIPTION

The ADSP-21020 is the first member of Analog Devices’ family
of single-chip IEEE floating-point processors optimized for
digital signal processing applications. Its architecture is similar
to that of Analog Devices’ ADSP-2100 family of fixed-point
DSP processors.

Fabricated in a high-speed, low-power CMOS process, the
ADSP-21020 has a 30 ns instruction cycle time. With a high­performance on-chip instruction cache, the ADSP-21020 can
execute every instruction in a single cycle.

The ADSP-21020 features:

•

REV. C

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

Independent Parallel Computation Units

The arithmetic/logic unit (ALU), multiplier and shifter
perform single-cycle instructions. The units are architecturally
arranged in parallel, maximizing computational throughput. A
single multifunction instruction executes parallel ALU and

x): 270 ns

DSP Microprocessor

ADSP-21020

FUNCTIONAL BLOCK DIAGRAM

multiplier operations. These computation units support IEEE
32-bit single-precision floating-point, extended precision
40-bit floating-point, and 32-bit fixed-point data formats.

Data Register File

•

A general-purpose data register file is used for transferring
data between the computation units and the data buses, and
for storing intermediate results. This 10-port (16-register)
register file, combined with the ADSP-21020’s Harvard
architecture, allows unconstrained data flow between
computation units and off-chip memory.

Single-Cycle Fetch of Instruction and Two Operands

•

The ADSP-21020 uses a modified Harvard architecture in
which data memory stores data and program memory stores
both instructions and data. Because of its separate program
and data memory buses and on-chip instruction cache, the
processor can simultaneously fetch an operand from data
memory, an operand from program memory, and an
instruction from the cache, all in a single cycle.

Memory Interface

•

Addressing of external memory devices by the ADSP-21020 is
facilitated by on-chip decoding of high-order address lines to
generate memory bank select signals. Separate control lines
are also generated for simplified addressing of page-mode
DRAM.

The ADSP-21020 provides programmable memory wait
states, and external memory acknowledge controls allow
interfacing to peripheral devices with variable access times.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] Fax: [phone]

ADSP-21020

Instruction Cache

•

The ADSP-21020 includes a high performance instruction
cache that enables three-bus operation for fetching an
instruction and two data values. The cache is selective—only
the instructions whose fetches conflict with program memory
data accesses are cached. This allows full-speed execution
of core, looped operations such as digital filter multiply­accumulates and FFT butterfly processing.

Hardware Circular Buffers

•

The ADSP-21020 provides hardware to implement circular
buffers in memory, which are common in digital filters and
Fourier transform implementations. It handles address
pointer wraparound, reducing overhead (thereby increasing
performance) and simplifying implementation. Circular
buffers can start and end at any location.

Flexible Instruction Set

•

The ADSP-21020’s 48-bit instruction word accommodates a
variety of parallel operations, for concise programming. For
example, the ADSP-21020 can conditionally execute a
multiply, an add, a subtract and a branch in a single
instruction.

DEVELOPMENT SYSTEM

The ADSP-21020 is supported with a complete set of software
and hardware development tools. The ADSP-21000 Family
Development System includes development software, an
evaluation board and an in-circuit emulator.

Assembler

•

Creates relocatable, COFF (Common Object File Format)
object files from ADSP-21xxx assembly source code. It
accepts standard C preprocessor directives for conditional
assembly and macro processing. The algebraic syntax of the
ADSP-21xxx assembly language facilitates coding and
debugging of DSP algorithms.

Linker/Librarian

•

The Linker processes separately assembled object files and
library files to create a single executable program. It assigns
memory locations to code and to data in accordance with a
user-defined architecture file that describes the memory and
I/O configuration of the target system. The Librarian allows
you to group frequently used object files into a single library
file that can be linked with your main program.

Simulator

•

The Simulator performs interactive, instruction-level
simulation of ADSP-21xxx code within the hardware
configuration described by a system architecture file. It flags
illegal operations and supports full symbolic disassembly. It
provides an easy-to-use, window oriented, graphical user
interface that is identical to the one used by the ADSP-21020
EZ-ICE Emulator. Commands are accessed from pull-down
menus with a mouse.

PROM Splitter

•

Formats an executable file into files that can be used with an
industry-standard PROM programmer.

C Compiler and Runtime Library

•

The C Compiler complies with ANSI specifications. It takes
advantage of the ADSP-21020’s high-level language architec­tural features and incorporates optimizing algorithms to speed
up the execution of code. It includes an extensive runtime
library with over 100 standard and DSP-specific functions.

C Source Level Debugger

•

A full-featured C source level debugger that works with the
simulator or EZ-ICE emulator to allow debugging of
assembler source, C source, or mixed assembler and C.

Numerical C Compiler

•

Supports ANSI Standard (X3J11.1) Numerical C as defined
by the Numeric C Extensions Group. The compiler accepts C
source input containing Numerical C extensions for array
selection, vector math operations, complex data types,
circular pointers, and variably dimensioned arrays, and
outputs ADSP-21xxx assembly language source code.

ADSP-21020 EZ-LAB® Evaluation Board

•

The EZ-LAB Evaluation Board is a general-purpose, stand­alone ADSP-21020 system that includes 32K words of
program memory and 32K words of data memory as well as
analog I/O. A PC RS-232 download path enables the user to
download and run programs directly on the EZ-LAB. In
addition, it may be used in conjunction with the EZ-ICE
Emulator to provide a powerful software debug environment.

ADSP-21020 EZ-ICE® Emulator

•

This in-circuit emulator provides the system designer with a
PC-based development environment that allows nonintrusive
access to the ADSP-21020’s internal registers through the
processor’s 5-pin JTAG Test Access Port. This use of on-chip
emulation circuitry enables reliable, full-speed performance in
any target. The emulator uses the same graphical user inter­face as the ADSP-21020 Simulator, allowing an easy tran­sition from software to hardware debug. (See “Target System
Requirements for Use of EZ-ICE Emulator” on page 27.)

ADDITIONAL INFORMATION

This data sheet provides a general overview of ADSP-21020
functionality. For additional information on the architecture and
instruction set of the processor, refer to the ADSP-21020 User’s
Manual. For development system and programming reference
information, refer to the ADSP-21000 Family Development

Software Manuals and the ADSP-21020 Programmer’s Quick
Reference. Applications code listings and benchmarks for key

DSP algorithms are available on the DSP Applications BBS; call
[phone], 8 data bits, no parity, 1 stop bit, 300/1200/
2400/9600 baud.

ARCHITECTURE OVERVIEW

Figure 1 shows a block diagram of the ADSP-21020. The
processor features:

Three Computation Units (ALU, Multiplier, and Shifter)

•

with a Shared Data Register File
Two Data Address Generators (DAG 1, DAG 2)

•

Program Sequencer with Instruction Cache

•

32-Bit Timer

•

Memory Buses and Interface

•

JTAG Test Access Port and On-Chip Emulation Support

•

Computation Units

The ADSP-21020 contains three independent computation
units: an ALU, a multiplier with fixed-point accumulator, and a
shifter. In order to meet a wide variety of processing needs, the
computation units process data in three formats: 32-bit
fixed-point, 32-bit floating-point and 40-bit floating-point. The
floating-point operations are single-precision IEEE-compatible
(IEEE Standard 754/854). The 32-bit floating-point format is

EZ-LAB and EZ-ICE are registered trademarks of Analog Devices, Inc.

–2–

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ADSP-21020

DAG 1

8 x 4 x 32

BUS CONNECT

FLOATING & FIXED-POINT
MULTIPLIER, FIXED-POINT

ACCUMULATOR

DAG 2

8 x 4 x 24

PMD BUS

DMD BUS

48

40

PMA BUS

REGISTER

16 x 40

CACHE

MEMORY

32 x 48

24

32DMA BUS

FILE

PROGRAM

SEQUENCER

32-BIT
BARREL
SHIFTER

JTAG TEST &

EMULATION

FLAGS

TIMER

FLOATING-POINT

& FIXED-POINT

PMA

DMA

PMD

DMD

ALU

Figure 1. ADSP-21020 Block Diagram

the standard IEEE format, whereas the 40-bit IEEE extended­precision format has eight additional LSBs of mantissa for
greater accuracy.

The multiplier performs floating-point and fixed-point
multiplication as well as fixed-point multiply/add and multiply/
subtract operations. Integer products are 64 bits wide, and the
accumulator is 80 bits wide. The ALU performs 45 standard
arithmetic and logic operations, supporting both fixed-point and
floating-point formats. The shifter performs 19 different
operations on 32-bit operands. These operations include logical
and arithmetic shifts, bit manipulation, field deposit, and extract
and derive exponent operations.

The computation units perform single-cycle operations; there is
no computation pipeline. The three units are connected in
parallel rather than serially, via multiple-bus connections with
the 10-port data register file. The output of any computation
unit may be used as the input of any unit on the next cycle. In a
multifunction computation, the ALU and multiplier perform
independent, simultaneous operations.

Data Register File

The ADSP-21020’s general-purpose data register file is used for
transferring data between the computation units and the data
buses, and for storing intermediate results. The register file has
two sets (primary and alternate) of sixteen 40-bit registers each,
for fast context switching.

With a large number of buses connecting the registers to the
computation units, data flow between computation units and
from/to off-chip memory is unconstrained and free from
bottlenecks. The 10-port register file and Harvard architecture

of the ADSP-21020 allow the following nine data transfers to be
performed every cycle:

Off-chip read/write of two operands to or from the register file

•

Two operands supplied to the ALU

•

Two operands supplied to the multiplier

•

Two results received from the ALU and multiplier (three, if

•

the ALU operation is a combined addition/subtraction)

The processor’s 48-bit orthogonal instruction word supports
fully parallel data transfer and arithmetic operations in the same
instruction.

Address Generators and Program Sequencer

Two dedicated address generators and a program sequencer
supply addresses for memory accesses. Because of this, the
computation units need never be used to calculate addresses.
Because of its instruction cache, the ADSP-21020 can
simultaneously fetch an instruction and data values from both
off-chip program memory and off-chip data memory in a single
cycle.

The data address generators (DAGs) provide memory addresses
when external memory data is transferred over the parallel
memory ports to or from internal registers. Dual data address
generators enable the processor to output two simultaneous
addresses for dual operand reads and writes. DAG 1 supplies
32-bit addresses to data memory. DAG 2 supplies 24-bit
addresses to program memory for program memory data
accesses.

Each DAG keeps track of up to eight address pointers, eight
modifiers, eight buffer length values and eight base values. A
pointer used for indirect addressing can be modified by a value

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ADSP-21020

in a specified register, either before (premodify) or after
(postmodify) the access. To implement automatic modulo
addressing for circular buffers, the ADSP-21020 provides buffer
length registers that can be associated with each pointer. Base
values for pointers allow circular buffers to be placed at arbitrary
locations. Each DAG register has an alternate register that can
be activated for fast context switching.

The program sequencer supplies instruction addresses to
program memory. It controls loop iterations and evaluates
conditional instructions. To execute looped code with zero
overhead, the ADSP-21020 maintains an internal loop counter
and loop stack. No explicit jump or decrement instructions are
required to maintain the loop.

The ADSP-21020 derives its high clock rate from pipelined
fetch, decode and execute cycles. Approximately 70% of the
machine cycle is available for memory accesses; consequently,
ADSP-21020 systems can be built using slower and therefore
less expensive memory chips.

Instruction Cache

The program sequencer includes a high performance, selective
instruction cache that enables three-bus operation for fetching
an instruction and two data values. This two-way, set-associative
cache holds 32 instructions. The cache is selective—only the
instructions whose fetches conflict with program memory data
accesses are cached, so the ADSP-21020 can perform a program
memory data access and can execute the corresponding instruction
in the same cycle. The program sequencer fetches the instruction
from the cache instead of from program memory, enabling the
ADSP-21020 to simultaneously access data in both program
memory and data memory.

Context Switching

Many of the ADSP-21020’s registers have alternate register sets
that can be activated during interrupt servicing to facilitate a fast
context switch. The data registers in the register file, DAG
registers and the multiplier result register all have alternate sets.
Registers active at reset are called primary registers; the others
are called alternate registers. Bits in the MODE1 control register
determine which registers are active at any particular time.

The primary/alternate select bits for each half of the register file
(top eight or bottom eight registers) are independent. Likewise,
the top four and bottom four register sets in each DAG have
independent primary/ alternate select bits. This scheme allows
passing of data between contexts.

Interrupts

The ADSP-21020 has four external hardware interrupts, nine
internally generated interrupts, and eight software interrupts.
For the external interrupts and the internal timer interrupt, the
ADSP-21020 automatically stacks the arithmetic status and
mode (MODE1) registers when servicing the interrupt, allowing
five nesting levels of fast service for these interrupts.

An interrupt can occur at any time while the ADSP-21020 is
executing a program. Internal events that generate interrupts
include arithmetic exceptions, which allow for fast trap handling
and recovery.

Timer

The programmable interval timer provides periodic interrupt
generation. When enabled, the timer decrements a 32-bit count
register every cycle. When this count register reaches zero, the
ADSP-21020 generates an interrupt and asserts its TIMEXP

output. The count register is automatically reloaded from a
32-bit period register and the count resumes immediately.

System Interface

Figure 2 shows an ADSP-21020 basic system configuration.
The external memory interface supports memory-mapped

peripherals and slower memory with a user-defined combination
of programmable wait states and hardware acknowledge signals.
Both the program memory and data memory interfaces support
addressing of page-mode DRAMs.

The ADSP-21020’s internal functions are supported by four
internal buses: the program memory address (PMA) and data
memory address (DMA) buses are used for addresses associated
with program and data memory. The program memory data
(PMD) and data memory data (DMD) buses are used for data
associated with the two memory spaces. These buses are
extended off chip. Four data memory select (DMS) signals
select one of four user-configurable banks of data memory.
Similarly, two program memory select (PMS) signals select
between two user-configurable banks of program memory. All
banks are independently programmable for 0-7 wait states.

The PX registers permit passing data between program memory
and data memory spaces. They provide a bridge between the
48-bit PMD bus and the 40-bit DMD bus or between the 40-bit
register file and the PMD bus.

The PMA bus is 24 bits wide allowing direct access of up to
16M words of mixed instruction code and data. The PMD is 48
bits wide to accommodate the 48-bit instruction width. For
access of 40-bit data the lower 8 bits are unused. For access of
32-bit data the lower 16 bits are ignored.

The DMA bus is 32 bits wide allowing direct access of up to 4
Gigawords of data. The DMD bus is 40 bits wide. For 32-bit
data, the lower 8 bits are unused. The DMD bus provides a
path for the contents of any register in the processor to be
transferred to any other register or to any external data memory
location in a single cycle. The data memory address comes from
one of two sources: an absolute value specified in the instruction
code (direct addressing) or the output of a data address
generator (indirect addressing).

External devices can gain control of the processor’s memory
buses from the ADSP-21020 by means of the bus request/grant
signals (
request, the ADSP-21020 halts internal operations and places
its program and data memory interfaces in a high impedance
state. In addition, three-state controls (
allow an external device to place either the program or data
memory interface in a high impedance state without affecting
the other interface and without halting the ADSP-21020 unless
it requires a memory access from the affected interface. The
three-state controls make it easy for an external cache controller
to hold the ADSP-21020 off the bus while it updates an external
cache memory.

JTAG Test and Emulation Support

The ADSP-21020 implements the boundary scan testing
provisions specified by IEEE Standard 1149.1 of the Joint
Testing Action Group (JTAG). The ADSP-21020’s test
access port and on-chip JTAG circuitry is fully compliant with
the IEEE 1149.1 specification. The test access port enables
boundary scan testing of circuitry connected to the
ADSP-21020’s I/O pins.

BR and BG). To grant its buses in response to a bus

DMTS and PMTS)

–4–

REV. C

1×

CLOCK

CLKIN

PROGRAM

MEMORY

SELECTS

WE

ADDR

DATA

2

OE

24
48

PMS1-0
PMRD
PMWR
PMA

PMD

ADSP-21010

PMTS

PMACK

BR

BG

RESET

TIMEXP

RCOMP

4

Figure 2. Basic System Configuration

The ADSP-21020 also implements on-chip emulation through
the JTAG test access port. The processor’s eight sets of break­point range registers enable program execution at full speed
until reaching a desired break-point address range. The
processor can then halt and allow reading/writing of all the
processor’s internal registers and external memories through the
JTAG port.

PIN DESCRIPTIONS

This section describes the pins of the ADSP-21020. When
groups of pins are identified with subscripts, e.g. PMD
highest numbered pin is the MSB (in this case, PMD

, the

47–0

). Inputs

47

identified as synchronous (S) must meet timing requirements
with respect to CLKIN (or with respect to TCK for TMS, TDI,
and

TRST). Those that are asynchronous (A) can be asserted

asynchronously to CLKIN.

O = Output; I = Input; S = Synchronous; A = Asynchronous;
P = Power Supply; G = Ground.

Pin
Name Type Function

PMA

O Program Memory Address. The ADSP-21020

23–0

outputs an address in program memory on
these pins.

PMD

I/O Program Memory Data. The ADSP-21020

47–0

inputs and outputs data and instructions on
these pins. 32-bit fixed-point data and 32-bit
single-precision floating-point data is trans­ferred over bits 47-16 of the PMD bus.

PMS

O Program Memory Select lines. These pins are

1–0

asserted as chip selects for the corresponding
banks of program memory. Memory banks
must be defined in the memory control
registers. These pins are decoded program
memory address lines and provide an early
indication of a possible bus cycle.

PMRD O Program Memory Read strobe. This pin is

asserted when the ADSP-21020 reads from
program memory.

PMWR O Program Memory Write strobe. This pin is

asserted when the ADSP-21020 writes to
program memory.

PMACK I/S Program Memory Acknowledge. An external

device deasserts this input to add wait states
to a memory access.

ADSP-21020

4

IRQ3-0

4

DMS3-0

DMRD

DMWR

DMTS

DMPAGEPMPAGE

DMACK

FLAG3-0

DMA
DMD

JTAG

5

32

32

Pin
Name Type Function

PMPAGE O Program Memory Page Boundary. The

PMTS I/S Program Memory Three-State Control.

DMA

DMD

DMS

O Data Memory Address. The ADSP-21020

31–0

I/O Data Memory Data. The ADSP-21020

39–0

O Data Memory Select lines. These pins are

3–0

DMRD O Data Memory Read strobe. This pin is

DMWR O Data Memory Write strobe. This pin is

DMACK I/S Data Memory Acknowledge. An external

SELECTS
OE
WE
ADDR
DATA

SELECTS
OE
WE
ACK
ADDR
DATA

DATA

MEMORY

PERIPHERALS

ADSP-21020 asserts this pin to signal that a
program memory page boundary has been
crossed. Memory pages must be defined in
the memory control registers.

PMTS places the program memory address,
data, selects, and strobes in a high­impedance state. If

PMTS is asserted while
a PM access is occurring, the processor will
halt and the memory access will not be
completed. PMACK must be asserted for at
least one cycle when

PMTS is deasserted to
allow any pending memory access to com­plete properly.

PMTS should only be
asserted (low) during an active memory
access cycle.

outputs an address in data memory on these
pins.

inputs and outputs data on these pins.
32-bit fixed point data and 32-bit
single-precision floating point data is
transferred over bits 39-8 of the DMD bus.

asserted as chip selects for the correspon­ding banks of data memory. Memory banks
must be defined in the memory control
registers. These pins are decoded data
memory address lines and provide an early
indication of a possible bus cycle.

asserted when the ADSP-21020 reads from
data memory.

asserted when the ADSP-21020 writes to
data memory.

device deasserts this input to add wait states
to a memory access.

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–5–

ADSP-21020

Pin
Name Type Function

DMPAGE O Data Memory Page Boundary. The ADSP-

21020 asserts this pin to signal that a data
memory page boundary has been crossed.
Memory pages must be defined in the
memory control registers.

DMTS I/S Data Memory Three-State Control. DMTS

places the data memory address, data,
selects, and strobes in a high-impedance
state. If
access is occurring, the processor will halt
and the memory access will not be
completed. DMACK must be asserted for
at least one cycle when
deasserted to allow any pending memory
access to complete properly.
only be asserted (low) during an active
memory access cycle.

CLKIIN I External clock input to the ADSP-21020.

The instruction cycle rate is equal to
CLKIN. CLKIN may not be halted,
changed, or operated below the specified
frequency.

RESET I/A Sets the ADSP-21020 to a known state and

begins execution at the program memory
location specified by the hardware reset
vector (address). This input must be
asserted (low) at power-up.

IRQ

3–0

FLAG

BR I/A Bus Request. Used by an external device to

BG O Bus Grant. Acknowledges a bus request

TIMEXP O Timer Expired. Asserted for four cycles

RCOMP Compensation Resistor input. Controls

EVDD P Power supply (for output drivers),

EGND G Power supply return (for output drivers);

I/A Interrupt request lines; may be either edge

triggered or level-sensitive.

I/O/A External Flags. Each is configured via

3–0

control bits as either an input or output. As
an input, it can be tested as a condition. As
an output, it can be used to signal external
peripherals.

request control of the memory interface.
When
execution after completion of the current
cycle, places all memory data, addresses,
selects, and strobes in a high-impedance
state, and asserts
continues normal operation when
released.

(
may take control of the memory interface.
BG is asserted (held low) until BR is
released.

when the value of TCOUNT is
decremented to zero.

compensated output buffers. Connect
RCOMP through a 1.8 kΩ ± 15% resistor
to EVDD. Use of a capacitor (approxi­mately 100 pF), placed in parallel with the

1.8 kΩ resistor is recommended.

nominally +5 V dc (10 pins).

(16 pins).

DMTS is asserted while a DM

DMTS is

DMTS should

BR is asserted, the processor halts

BG. The processor

BR is

BR), indicating that the external device

–6–

Pin
Name Type Function

IVDD P Power supply (for internal circuitry),

nominally +5 V dc (4 pins).

IGND G Power supply return (for internal circuitry); (7

pins).

TCK I Test Clock. Provides an asynchronous clock

for JTAG boundary scan.

TMS I/S Test Mode Select. Used to control the test

state machine. TMS has a 20 kΩ internal
pullup resistor.

TDI VS Test Data Input. Provides serial data for the

boundary scan logic. TDI has a 20 kΩ internal
pullup resistor.

TDO O Test Data Output. Serial scan output of the

boundary scan path.

TRST I/A Test Reset. Resets the test state machine.

TRST must be asserted (pulsed low) after

power-up or held low for proper operation of
the ADSP-21020.
pullup resistor.

NC No Connect. No Connects are reserved pins

that must be left open and unconnected.

INSTRUCTION SET SUMMARY

The ADSP-21020 instruction set provides a wide variety of
programming capabilities. Every instruction assembles into a
single word and can execute in a single processor cycle.
Multifunction instructions enable simultaneous multiplier and
ALU operations, as well as computations executed in parallel
with data transfers. The addressing power of the ADSP-21020
gives you flexibility in moving data both internally and
externally. The ADSP-21020 assembly language uses an
algebraic syntax for ease of coding and readability.

The instruction types are grouped into four categories:

Compute and Move or Modify
Program Flow Control
Immediate Move
Miscellaneous

The instruction types are numbered; there are 22 types. Some
instructions have more than one syntactical form; for example,
Instruction 4 has four distinct forms. The instruction number
itself has no bearing on programming, but corresponds to the
opcode recognized by the ADSP-21020 device.

Because of the width and orthogonality of the instruction word,
there are many possible instructions. For example, the ALU
supports 21 fixed-point operations and 24 floating-point
operations; each of these operations can be the compute portion
of an instruction.

The following pages provide an overview and summary of the
ADSP-21020 instruction set. For complete information, see the
ADSP-21020 User’s Manual. For additional reference informa­tion, see the ADSP-21020 Programmer’s Quick Reference.

This section also contains several reference tables for using the
instruction set.

Table I describes the notation and abbreviations used.

•

Table II lists all condition and termination code mnemonics.

•

Table III lists all register mnemonics.

•

Tables IV through VII list the syntax for all compute

•

(ALU, multiplier, shifter or multifunction) operations.
Table VIII lists interrupts and their vector addresses.

•

TRST has a 20 kΩ internal

REV. C

COMPUTE AND MOVE OR MODIFY INSTRUCTIONS

1. compute,

2. IF condition compute;
3a. IF condition compute,

3b. IF condition compute,

3c. IF condition compute, ureg =|DM(Ia, Mb)|;

3d. IF condition compute, ureg =|DM(Mb, Ia)|;

4a. IF condition compute,

4b. IF condition compute,

4c. IF condition compute, dreg =|DM(Ia, <data6>)|;

4d. IF condition compute, dreg =|DM(<data6>, Ia)|;

5. IF condition compute, ureg1 = ureg2 ;
6a. IF condition shiftimm,

6b. IF condition shiftimm, dreg = |DM(Ia, Mb)|;

7. IF condition compute, MODIFY |(Ia, Mb)|;

7. IF condition compute, MODIFY

DM(Ia, Mb) = dreg1|,

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|

dreg1 = DM(Ia, Mb)

DM(Ia, Mb)|= ureg ;

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PM(Ic, Md)
DM(Mb, Ia)|= ureg ;

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PM(Md, Ic)

DM(Ia, <data6>)|= dreg ;

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PM(Ic, <data6>)
DM(<data6>, Ia)|= dreg ;

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PM(<data6>, Ic)

DM(Ia, Mb)| = dreg ;

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PM(Ic, Md)

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PM(Ic, Md)

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PM(Md, Ic)

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PM(Ic, <data6>)

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PM(<data6>, Ic)

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PM(Ic, Md)

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(Ic, Md)

||

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|

|

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PM(Ic, Md) = dreg2|;

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dreg2 = PM(Ic, Md)

ADSP-21020

|

PROGRAM FLOW CONTROL INSTRUCTIONS

8. IF condition

9. IF condition

11. IF condition

12. LCNTR =

12. LCNTR =

13. LCNTR =

12. LCNTR =

(DB) Delayed branch
(LA) Loop abort (pop loop PC stacks on branch)

REV. C

JUMP

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CALL

|

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|

|

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|

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|

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|

||

CALL

JUMP
CALL

||

CALL

RTS

|

RTI

|

RTI | (

<data16>| ,DO|<addr24>
ureg

<data16>| , DO|<addr24>
ureg

<addr24>

||
||

(PC, <reladdr6>)

(PC, <reladdr6>)

(Md, Ic)

||
||

(PC, <reladdr6>)

(PC, <reladdr6>)

(|DB,
(|LA,

|

DB, LA

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,DO

|

,DO

),compute ;

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|

|

(

<PC, <reladdr24>)

|(|

(PC, <reladdr24>)

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|

|

|
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(|DB

LA

|

(

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DB, LA

(

(|DB

|

LA

(

|

DB, LA

(

|

(|UNTIL LCE ;

|

) ;

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|

,

|

),compute ;

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,

|

UNTIL LCE ;

UNTIL termination ;

|

–7–

ADSP-21020

IMMEDIATE MOVE INSTRUCTIONS

14a. DM(<addr32>) = ureg ;

PM(<addr24>)

14b. ureg = DM(<addr32>) ;

PM(<addr24>)

15a. DM(<data32>, Ia) = ureg;

PM(< data24>, Ic)

15b. ureg = DM(<data32>, Ia) ;

PM(<data24>, Ic)

16. DM(Ia, Mb) = <data32>;
PM(Ic, Md)

17. ureg = <data32>;

MISCELLANEOUS INSTRUCTIONS

18. BIT SET sreg <data32>;

CLR
TGL
TST
XOR

19a. MODIFY (Ia, <data32>)|;

(Ic, <data32>)|

19b. BITREV (Ia, <data32>) ;

20. |PUSH LOOP , PUSH STS ;

|POP POP

21. NOP ;

22. IDLE ;

Table I. Syntax Notation Conventions

Notation Meaning

UPPERCASE Explicit syntax—assembler keyword (nota-

tion only; assembler is not case-sensitive
and lowercase is the preferred programming

convention)
; Instruction terminator
, Separates parallel operations in an

instruction
italics Optional part of instruction
| between lines | List of options (choose one)
<datan> n-bit immediate data value
<addrn> n-bit immediate address value
<reladdrn> n-bit immediate PC-relative address value
compute ALU, multiplier, shifter or multifunction

operation (from Tables IV-VII)
shiftimm Shifter immediate operation

(from Table VI)
condition Status condition (from Table II)
termination Termination condition (from Table II)
ureg Universal register (from Table III)
sreg System register (from Table III)
dreg R15-R0, F15-F0; register file location
Ia I7-I0; DAG1 index register
Mb M7-M0; DAG1 modify register
Ic I15-I8; DAG2 index register
Md M15-M8; DAG2 modify register

Table II. Condition and Termination Codes

Name Description

eq ALU equal to zero
ne ALU not equal to zero
ge ALU greater than or equal to zero
lt ALU less than zero
le ALU less than or equal to zero
gt ALU greater than zero
ac ALU carry
not ac Not ALU carry
av ALU overflow
not av Not ALU overflow
mv Multiplier overflow
not mv Not multiplier overflow
ms Multiplier sign
not ms Not multiplier sign
sv Shifter overflow
not sv Not shifter overflow
sz Shifter zero
not sz Not shifter zero
flag0_in Flag 0
not flag0_in Not Flag 0
flag1_in Flag 1
not flag1_in Not Flag l
flag2_in Flag 2
not flag2_in Not Flag 2
flag3_in Flag 3
not flag3_in Not Flag 3
tf Bit test flag
not tf Not bit test flag
lce Loop counter expired (DO UNTIL)
not lce Loop counter not expired (IF)
forever Always False (DO UNTIL)
true Always True (IF)

In a conditional instruction, the execution of the entire instruction is based on
the specified condition.

–8–

REV. C

ADSP-21020

Table III. Universal Registers

Name Function

Register File

R15–R0 Register file locations

Program Sequencer

PC* Program counter; address of instruction cur-

rently executing
PCSTK Top of PC stack
PCSTKP PC stack pointer
FADDR* Fetch address
DADDR* Decode address
LADDR Loop termination address, code; top of loop

address stack
CURLCNTR Current loop counter; top of loop count stack
LCNTR Loop count for next nested counter-controlled

loop

Data Address Generators

I7–I0 DAG1 index registers
M7–M0 DAG1 modify registers
L7–L0 DAG1 length registers
B7–B0 DAG1 base registers
I15–I8 DAG2 index registers
M15–M8 DAG2 modify registers
L15–L8 DAG2 length registers
B15–B8 DAG2 base registers

Bus Exchange

PX1 PMD-DMD bus exchange 1 (16 bits)
PX2 PMD-DMD bus exchange 2 (32 bits)
PX 48-bit PX1 and PX2 combination

Timer

TPERIOD Timer period
TCOUNT Timer counter

Memory Interface

DMWAIT Wait state and page size control for data

memory
DMBANK1 Data memory bank 1 upper boundary
DMBANK2 Data memory bank 2 upper boundary
DMBANK3 Data memory bank 3 upper boundary
DMADR* Copy of last data memory address
PMWAIT Wait state and page size control for program

memory
PMBANK1 Program memory bank 1 upper boundary
PMADR* Copy of last program memory address

System Registers

MODE1 Mode control bits for bit-reverse, alternate reg-

isters, interrupt nesting and enable, ALU satu-

ration, floating-point rounding mode and

boundary
MODE2 Mode control bits for interrupt sensitivity,

cache disable and freeze, timer enable, and I/O

flag configuration
IRPTL Interrupt latch
IMASK Interrupt mask
IMASKP Interrupt mask pointer (for nesting)
ASTAT Arithmetic status flags, bit test, I/O flag values,

and compare accumulator
STKY Sticky arithmetic status flags, circular buffer

overflow flags, stack status flags (not sticky)
USTAT1 User status register l
USTAT2 User status register 2

*read-only
Refer to User’s Manual for bit-level definitions of each register.

Table IV. ALU Compute Operations

Fixed-Point Floating-Point

Rn = Rx + Ry Fn = Fx + Fy
Rn = Rx – Ry Fn = Fx – Fy
Rn = Rx + Ry, Rm = Rx – Ry Fn = Fx + Fy, Fm = Fx – Fy
Rn = Rx + Ry + CI Fn = ABS (Fx + Fy)
Rn = Rx – Ry + CI – l Fn = ABS (Fx – Fy)
Rn = (Rx + Ry)/2 Fn = (Fx + Fy)/2
COMP(Rx, Ry) COMP(Fx, Fy)
Rn = –Rx Fn = –Fx
Rn = ABS Rx Fn = ABS Fx
Rn = PASS Rx Fn = PASS Fx
Rn = MIN(Rx, Ry) Fn = MIN(Fx, Fy)
Rn = MAX(Rx, Ry) Fn = MAX(Fx, Fy)
Rn = CLIP Rx BY Ry Fn = CLIP Fx BY Fy
Rn = Rx + CI Fn = RND Fx
Rn = Rx + CI – 1 Fn = SCALB Fx BY Ry
Rn = Rx + l Rn = MANT Fx
Rn = Rx – l Rn = LOGB Fx
Rn = Rx AND Ry Rn = FIX Fx BY Ry
Rn = Rx OR Ry Rn = FIX Fx
Rn = Rx XOR Ry Fn = FLOAT Rx BY Ry
Rn = NOT Rx Fn = FLOAT Rx

Fn = RECIPS Fx
Fn = RSQRTS Fx
Fn = Fx COPYSIGN Fy

Rn, Rx, Ry R15–R0; register file location, fixed-point
Fn, Fx, Fy F15–F0; register file location, floating point

REV. C

–9–

ADSP-21020

Table V. Multiplier Compute Operations

Rn = Rx * Ry ( SSF ) Fn = Fx * Fy
MRF = Rx * Ry ( UUI
MRB = Rx * Ry (U U FR

Rn = MRF + Rx * Ry ( SSF ) Rn = MRF – Rx * Ry ( SSF )
Rn = MRB + Rx * Ry ( UUI Rn = MRB= Rx * Ry ( UUI
MRF = MRF + Rx * Ry ( U U FR MRF = MRF= Rx * Ry ( UUI FR
MRB = MRB MRB = MRB

Rn = SAT MRF (SI) Rn = RND MRF (SF)
Rn = SAT MRB (UI) Rn = RND MRB (UF)
MRF = SAT MRF (SF) MRF = RND MRF
MRB = SAT MRB (UF) MRB = RND MRB

MRF = 0
MRB

MRxF = Rn Rn = MRxF
MRxB Rn = MRxB

Rn, Rx, Ry R15–R0; register file location, fixed-point
Fn, Fx, Fy F15–F0; register file location, floating-point
MRxF MR2F, MR1F; MR0F; multiplier result accumulators, foreground
MRxB MR2B, MR1B, MR0B; multiplier result accumulators, background

( x-input y-input data format, )

( x-input y-input rounding

S Signed input
U Unsigned input
I Integer input(s)
F Fractional input(s)
FR Fractional inputs, Rounded output

(SF) Default format for 1-input operations
(SSF) Default format for 2-input operations

Table VI. Shifter and Shifter Immediate Compute Operations

Shifter Shifter Immediate

Rn = LSHIFT Rx BY Ry Rn = LSHIFT Rx BY<data8>
Rn = Rn OR LSHIFT Rx BY Ry Rn = Rn OR LSHIFT Rx BY<data8>
Rn = ASHIFT Rx BY Ry Rn = ASHIFT Rx BY<data8>
Rn = Rn OR ASHIFT Rx BY Ry Rn = Rn OR ASHIFT Rx BY<data8>
Rn = ROT Rx BY RY Rn = ROT Rx BY<data8>
Rn = BCLR Rx BY Ry Rn = BCLR Rx BY<data8>
Rn = BSET Rx BY Ry Rn = BSET Rx BY<data8>
Rn = BTGL Rx BY Ry Rn = BTGL Rx BY<data8>
BTST Rx BY Ry BTST Rx BY<data8>
Rn = FDEP Rx BY Ry Rn = FDEP Rx BY <bit6>: <len6>
Rn = Rn OR FDEP Rx BY Ry Rn = Rn OR FDEP Rx BY <bit6>:<1en6>
Rn = FDEP Rx BY Ry (SE) Rn = FDEP Rx BY <bit6>:<1en6> (SE)
Rn = Rn OR FDEP Rx BY Ry (SE) Rn = Rn OR FDEP Rx BY <bit6>:<1en6> (SE)
Rn = FEXT Rx BY Ry Rn = FEXT Rx BY <bit6>:<1en6>
Rn = FEXT Rx BY Ry (SE) Rn = FEXT Rx BY <bit6>:<1en6> (SE)
Rn = EXP Rx
Rn = EXP Rx (EX)
Rn = LEFTZ Rx
Rn = LEFTO Rx

Rn, Rx, Ry R15-R0; register file location, fixed-point
<bit6>:<len6> 6-bit immediate bit position and length values (for shifter immediate operations)

–10–

REV. C