ANALOG DEVICES ADRF6801 Service Manual

750 MHz to 1150 MHz Quadrature

V

Demodulator with Fractional-N PLL and VCO

FEATURES

IQ demodulator with integrated fractional-N PLL LO frequency range: 750 MHz to 1150 MHz Input P1dB: 12.5 dBm Input IP3: 25 dBm Noise figure (DSB): 14.3 dB Voltage conversion gain: 5.1 dB Quadrature demodulation accuracy

Phase accuracy: 0.3°

Amplitude accuracy: 0.05 dB Baseband demodulation: 275 MHz, 3 dB bandwidth SPI serial interface for PLL programming 40-lead, 6 mm × 6 mm LFCSP

APPLICATIONS

QAM/QPSK RF/IF demodulators Cellular W-CDMA/CDMA/CDMA2000 Microwave point-to-(multi)point radios Broadband wireless and WiMAX

ADRF6801

GENERAL DESCRIPTION

The ADRF6801 is a high dynamic range IQ demodulator with integrated PLL and VCO. The fractional-N PLL/synthesizer generates a frequency in the range of 3.0 GHz to 4.6 GHz. A divide-by-4 quadrature divider divides the output frequency of the VCO down to the required local oscillator (LO) frequency to drive the mixers in quadrature. Additionally, an output buffer can be enabled that generates an f

The PLL reference input is supported from 10 MHz to 160 MHz. The phase detector output controls a charge pump whose output is integrated in an off-chip loop filter. The loop filter output is then applied to an integrated VCO.

The IQ demodulator mixes the differential RF input with the complex LO derived from the quadrature divider. The differential I and Q output paths have excellent quadrature accuracy and can handle baseband signaling or complex IF up to 120 MHz.

The ADRF6801 is fabricated using an advanced silicon-germanium BiCMOS process. It is available in a 40-lead, exposed-paddle, RoHS-compliant, 6 mm × 6 mm LFCSP package. Performance is specified over the −40°C to +85°C temperature range.

/2 signal for external use.

VCO

FUNCTIONAL BLOCK DIAGRAM

LOSEL

CCLO

GND

34

LON

LOP

GND

DATA

CLK

GND

REFIN

GND

MUXOUT

35

37

38

MUX

1

VCC1

FRACTION

REG

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

TEMP

SENSOR

3.3V LDO

2

DECL3

11 12 13 14

LE

15

6

7

8

SPI

INTERFACE

×2

÷2 ÷4

17

10

VCC2

36

MODULUS

– +

FREQUENCY

DETECTOR

16

GND

BUFFER

CTRL

INTEGER

REG

N COUNTER

PHASE

PRESCALER

÷2

CHARGE PUMP 250µA, 500µA (DEFAUL T ), 750µA, 1000µA

4

3

GND

CPOUT

5

RSET

BUFFER

9

DECL2

MUX

DIVIDER

VCO

CORE

39

VTUNE

OR ÷2

÷1

ADRF6801

VCO LDO2.5V LDO

40

DECL1

QUAD

÷2

Figure 1.

18

QBBP

IBBNIBBP

3233

19

QBBN

GND

31

20

GND

30 29 28 27

26

25

24

23

22

21

GND VCCBB GND VCCRF

RFIN

GNDRF GND GND VCCBB GND

09576-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

ADRF6801

REVISION HISTORY

1/11—Revision 0: Initial Version

Rev. 0 | Page 2 of 36

ADRF6801

SPECIFICATIONS

VS = 5 V; ambient temperature (TA) = 25°C; f settings use the recommended values shown in the Register Structure section, unless otherwise noted.

Table 1.

Parameter Test Conditions/Comments Min Typ Max Unit

RF INPUT AT 900 MHz RFIN pins

Internal LO Frequency Range With VCO amplitude = 63 (R6 [DB15 to DB10]) 750 1125 MHz

With VCO amplitude = 24 (R6 [DB15 to DB10]) 750 1150 MHz

Input Return Loss Measured at 900 MHz <−20 dB

Input P1dB 12.5 dBm

Second-Order Input Intercept (IIP2) −5 dBm each tone >65 dBm

Third-Order Input Intercept (IIP3) −5 dBm each tone 25 dBm

Noise Figure Double sideband from RF to either I or Q output 14.3 dB

With a −10 dBm interferer 5 MHz away 18.9 dB

LO-to-RF Leakage At 1×LO frequency, 50 Ω termination at the RF port −75 dBm

I/Q BASEBAND OUTPUTS IBBP, IBBN, QBBP, QBBN pins

Voltage Conversion Gain 450 Ω differential load across IBBP, IBBN (or QBBP, QBBN) 5.1 dB

Demodulation Bandwidth 1 V p-p signal 3 dB bandwidth 275 MHz

Quadrature Phase Error 0.3 Degrees

I/Q Amplitude Imbalance 0.05 dB

Output DC Offset (Differential) ±5 mV

Output Common-Mode Voltage V

Gain Flatness Any 5 MHz (<100 MHz) 0.2 dB p-p

Maximum Output Swing Differential 450 Ω load 4 V p-p

Differential 200 Ω load 2.4 V p-p

Maximum Output Current Each pin 12 mA p-p

LO INPUT/OUTPUT LOP, LON

Output Level

Input Level Externally applied 2×LO, PLL disabled 0 dBm

Input Impedance Externally applied 2×LO, PLL disabled 50 Ω

VCO Operating Frequency With VCO amplitude = 63 (R6 [DB15 to DB10]) 3000 4500 MHz

With VCO amplitude = 24 (R6 [DB15 to DB10]) 3000 4600 MHz

SYNTHESIZER SPECIFICATIONS

Channel Spacing f

PLL Bandwidth

SPURS

Reference Spurs f

f f f

= 26 MHz, fLO = 900 MHz, fBB = 4.5 MHz, R

REF

Into a differential 50 Ω load, LO buffer enabled (LO

= 450  differential, all register and PLL

LOAD

− 2.4 V

POS

−2.5 dBm

frequency = 900 MHz, output frequency = 1800 MHz)

All synthesizer specifications measured with recommended settings provided in Figure 33 through Figure 39

= 26 MHz; modulus = 2047 25 kHz

PFD

Can be adjusted with off-chip loop filter component values and R

= 900 MHz, f

f

LO

at BB outputs with f

= 26 MHz, f

REF

/2 −107.8 dBc

PFD

× 2 −89.1 dBc

PFD

× 3 −94.2 dBc

PFD

SET

= 26 MHz, f

REF

= 50 MHz

BB

= 26 MHz −91.6 dBc

PFD

= 26 MHz, measured

PFD

130 kHz

Rev. 0 | Page 3 of 36

ADRF6801

Parameter Test Conditions/Comments Min Typ Max Unit

PHASE NOISE (USING 130 kHz LOOP FILTER)

= 900 MHz, f

f

LO

= 26 MHz, f

REF

at BB outputs with f

= 50 MHz

BB

= 26 MHz, measured

PFD

1 kHz offset −99.5 dBc/Hz 10 kHz offset −107.8 dBc/Hz 100 kHz offset −106.6 dBc/Hz 500 kHz offset −126.7 dBc/Hz 1 MHz offset −131.7 dBc/Hz 5 MHz offset −143.5 dBc/Hz 10 MHz offset −150.5 dBc/Hz

Integrated Phase Noise 1 kHz to 10 MHz integration bandwidth 0.16 °rms

PHASE NOISE (USING 2.5 kHz LOOP FILTER)

= 900 MHz, f

f

LO

= 26 MHz, f

REF

at BB outputs with f

= 50 MHz

BB

= 26 MHz, measured

PFD

1 kHz offset −71.3 dBc/Hz 10 kHz offset −88.3 dBc/Hz 100 kHz offset −114.1 dBc/Hz 500 kHz offset −129.5 dBc/Hz 1 MHz offset −138.6 dBc/Hz 5 MHz offset −150.2 dBc/Hz 10 MHz offset −150.3 dBc/Hz PLL FIGURE OF MERIT (FOM) Measured with f Measured with f

= 26 MHz, f

REF

= 104 MHz, f

REF

= 26 MHz −215.4 dBc/Hz/Hz

PFD

= 26 MHz −220.9 dBc/Hz/Hz

PFD

Phase Detector Frequency 20 26 40 MHz

REFERENCE CHARACTERISTICS REFIN, MUXOUT pins

REFIN Input Frequency Usable range 10 160 MHz REFIN Input Capacitance 4 pF MUXOUT Output Level VOL (lock detect output selected) 0.25 V V

(lock detect output selected) 2.7 V

OH

REFOUT Duty Cycle 50 %

CHARGE PUMP

Pump Current 500 μA Output Compliance Range 1 2.8 V

LOGIC INPUTS CLK, DATA, LE pins

Input High Voltage, V Input Low Voltage, V Input Current, I

INH/IINL

1.4 3.3 V

INH

0 0.7 V

INL

0.1 μA

Input Capacitance, CIN 5 pF

POWER SUPPLIES VCC1, VCC2, VCCLO, VCCBB, VCCRF pins

Voltage Range (5 V) 4.75 5 5.25 V Supply Current (5 V) Normal Rx mode, internal LO 262 mA Rx mode, internal LO with LO buffer enabled 288 mA

Rx mode, using external LO input (internal VCO, PLL shut down)

Supply Current (5 V) Power-down mode 20 mA

Rev. 0 | Page 4 of 36

157 mA

ADRF6801

C

TIMING CHARACTERISTICS

VS = 5 V, unless otherwise noted.

Table 2.

Parameter Limit at T

t1 20 ns min LE setup time t2 10 ns min DATA to CLK setup time t3 10 ns min DATA to CLK hold time t4 25 ns min CLK high duration t5 25 ns min CLK low duration t6 10 ns min CLK to LE setup time t7 20 ns min LE pulse width

Timing Diagram

LOCK

MIN

to T

(B Version) Unit Test Conditions/Comments

MAX

t

4

t

5

DATA

t

2

DB23 (MSB) DB22 DB2

LE

t

1

LE

t

3

DB1

(CONTROL BIT C2)

DB0 (LSB)

(CONTROL BIT C1)

t

6

t

7

09576-002

Figure 2. Timing Diagram

Rev. 0 | Page 5 of 36

ADRF6801

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

Supply Voltage, VCC1, VCC2, VCCLO,

VCCBB, and VCCRF (V Digital I/O, CLK, DATA, and LE −0.3 V to +3.6 V RFIN 16 dBm θJA (Exposed Paddle Soldered Down) 30°C/W Maximum Junction Temperature 150°C Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C

)

S1

−0.5 V to +5.5 V

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. 0 | Page 6 of 36

ADRF6801

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

ND

31 GND

40 DECL1

39 VTUNE

38 LOP

37 LON

36 LOSEL

35 G

34 VCCLO

32 IBBN

33 IBBP

VCC1 1

DECL3 2

CPOUT 3

GND 4

RSET 5

REFIN 6

GND 7

MUXOUT 8

DECL2 9

VCC2 10

ENABLE

VCO LDO

PHASE DETECTOR

CHARGE PUMP

×

2

÷2

÷4

2.5V LDO

FRACTION

AND

MUX

SCALE

BLEED

VCO

BAND

CURRENT

CAL/SET

PROGRAMABLE

DIVIDER

THIRD-ORDER

MODULUS

6

SDM

BUFFER

CTRL

VCO

3000MHz

TO

4600MHz

MUX

PRESCALER

÷2

INTEGER

DIV

CTRL

DIV

÷1

OR

÷2

QUADRATURE

÷2

30 GND

29 VCCBB

28 GND

27 VCCRF

26 RFIN

25 GNDRF

24 GND

23 GND

22 VCCBB

21 GND

SERIAL PORT

LE 14

GND 11

CLK 13

DATA 12

GND 15

LO 17

GND 16

VCC

N 19

QBBP 18

GND 20

QBB

08817-003

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 VCC1 The 5 V Power Supply Pin for VCO and PLL (VCC1). 2 DECL3 Decoupling Node for the 3.3 V LDO. Connect a 0.1 μF capacitor between this pin and ground. 3 CPOUT Charge Pump Output Pin. Connect this pin to VTUNE through the loop filter. 4, 7, 11, 15, 16, 20, 21,

GND Connect these pins to a low impedance ground plane.

23, 24, 28, 30, 31, 35

Rev. 0 | Page 7 of 36

ADRF6801

Pin No. Mnemonic Description

5 RSET

6 REFIN Reference Input. Nominal input level is 1 V p-p. Input range is 10 MHz to 160 MHz. 8 MUXOUT

9 DECL2 Decoupling Node for 2.5 V LDO. Connect a 0.1 μF capacitor between this pin and ground. 10 VCC2 The 5 V power supply pin for the 2.5 V LDO. 12 DATA Serial Data Input. The serial data is loaded MSB first with the three LSBs being the control bits. 13 CLK

14 LE

17, 34 VCCLO The 5 V Power Supply for the LO Path Blocks. 18, 19 QBBP, QBBN Demodulator Q-Channel Differential Baseband Outputs; Differential Output Impedance of 24 Ω. 22, 29 VCCBB The 5 V Power Supply for the Baseband Output Section of the Demodulator Blocks. 25 GNDRF Ground Return for RF Input Balun. 26 RFIN Single-Ended, Ground Referenced 50 Ω, RF Input. 27 VCCRF The 5 V Power Supply for the RF Input Section of the Demodulator Blocks. 32, 33 IBBN, IBBP Demodulator I-Channel Differential Baseband Outputs; Differential Output Impedance of 24 Ω. 36 LOSEL

37, 38 LON, LOP

39 VTUNE

40 DECL1

EP Exposed Paddle. The exposed paddle should be soldered to a low impedance ground plane.

Charge Pump Current. The nominal charge pump current can be set to 250 μA, 500 μA, 750 μA, or 1 mA using DB10 and DB11 of Register 4 and by setting DB18 to 0 (internal reference current). In this mode, no external R (I

) can be externally tweaked according to the following equation where the resulting value is in

NOMINAL

is required. If DB18 is set to 1, the four nominal charge pump currents

SET

units of ohms.

⎡

=

R

⎢

SET

⎣

I

NOMINAL

⎤

×

I

4.217

CP

⎥

8.37

−

⎦

Multiplexer Output. This output can be programmed to provide the reference output signal or the lock detect signal. The output is selected by programming the appropriate register.

Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 24-bit shift register on the CLK rising edge. Maximum clock frequency is 20 MHz.

Load Enable. When the LE input pin goes high, the data stored in the shift registers is loaded into one of the six registers, the relevant latch being selected by the first three control bits of the 24-bit word.

LO Select. Connect this pin to ground for the simplest operation and to completely control the LO path and input/output direction from the register SPI programming.

For additional control without register reprogramming, this input pin can determine whether the LOP and LON pins operate as inputs or outputs. LOP and LON become inputs if the LOSEL pin is set low, the LDRV bit of Register 5 is set low, and the LXL bit of Register 5 is set high. The externally applied LO drive must be at 2×LO frequency (and the LDIV bit of Register 5 (DB5) set low). LON and LOP become outputs when LOSEL is high or if the LDRV bit of Register 5 (DB3) is set high and the LXL bit of Register 5 (DB4) is set low. The output frequency is 2×LO frequency (and the LDIV bit of Register 5 (DB5) must be set high). This pin should not be left floating.

Local Oscillator Input/Output. When these pins are used as output pins, a differential frequency divided version of the internal VCO is available on these pins. When the internal LO generation is disabled, an external M×LO frequency signal can be applied to these pins (where M corresponds to the LO path divider setting). (Differential Input/Output Impedance of 50 Ω)

VCO Control Voltage Input. This pin is driven by the output of the loop filter. The nominal input voltage range on this pin is 1.0 V to 2.8 V.

Connect a 10 μF capacitor between this pin and ground as close to the device as possible because this pin serves as the VCO supply and loop filter reference.

Rev. 0 | Page 8 of 36

ADRF6801

A

R

A

TYPICAL PERFORMANCE CHARACTERISTICS

VS = 5 V, TA = 25°C, unless otherwise noted. LO = 750 MHz to 1150 MHz.

16

14

IP1dB

12

10

8

GAIN

6

4

2

CONVERSION GAIN (dB) AND I NPUT P1dB (dBm)

0

750 800 850 900 950 1000 1050 1100 1150

TA = +85°C TA = +25°C TA = –40°C

LO FR EQUENCY (MHz)

Figure 4. Conversion Gain and Input P1dB vs. LO Frequency

35

33

TA = +85°C

31

T

= +25°C

A

T

= –40°C

29

27

25

23

INPUT IP3 (dBm)

21

19

17

15

A

750 800 850 900 950 1000 1050 1100 1150

LO FREQUENCY (MHz)

Figure 5. Input IP3 vs. LO Frequency

1.0

0.8

0.6

0.4

0.2

TCH (dB)

0

–0.2

–0.4

IQ GAIN MISM

–0.6

–0.8 –1.0

TA = +85°C T

= +25°C

A

T

= –40°C

A

750 800 850 900 950 1000 1050 1100 1150

LO FREQUENCY (MHz)

Figure 6. IQ Gain Mismatch vs. LO Frequency

09576-004

09576-005

09576-006

80

75

70

65

INPUT IP2 (dBm)

60

55

50

750 800 850 900 950 1000 1050 1100 1150

TA = +85°C TA = +25°C TA = –40°C

I CHANNEL Q CHANNEL

LO FREQ UENCY (MHz )

Figure 7. Input IP2 vs. LO Frequency

20

19

18

TA = +85°C T

17

16

15

14

NOISE FI GURE (dB)

13

12

11

10

750 800 850 900 950 10 00 1050 1 10 0 1150

= +25°C

A

T

= –40°C

A

LO FREQ UENCY (MHz)

Figure 8. Noise Figure vs. LO Frequency

5

4

TA = +85°C T

3

2

1

0

–1

TURE PHASE ERROR (Degrees)

–2

–3

–4

IQ QUAD

–5

750 800 850 900 950 1000 1050 1100 1150

= +25°C

A

T

= –40°C

A

LO FREQUENCY (MHz)

Figure 9. IQ Quadrature Phase Error vs. LO Frequency

09576-007

09576-008

09576-009

Rev. 0 | Page 9 of 36

ADRF6801

–

50

–55

–60

–65

–70

–75

–80

LO-TO-RF F E E DTHROUGH (dBm)

–85

–90

750 800 850 900 950 1000 1050 1100 1150

LO FREQUENCY (MHz)

Figure 10. LO-to-RF Feedthrough vs. LO Frequency, LO Output Turned Off

35

–40

–45

–50

–55

–60

–65

LO-TO-BB FEE DTHROUGH (dBV rms)

–70

1

0

–1

–2

–3

–4

NORMALIZE D BASE BAND

–5

FREQUENCY RES PONSE (dB)

–6

–7

1 10 100

09576-010

BASEBAND FREQUENCY (MHz)

09576-013

Figure 13. Normalized Baseband Frequency Response vs. Baseband

Frequency

80

70

60

TA = +85°C

= +25°C

T

50

40

30

AND INPUT IP3 ( dBm)

20

INPUT P1dB (dBm), INPUT IP2 (d Bm),

10

A

= –40°C

T

A

I CHANNEL Q CHANNEL

IIP2

IIP3

IP1dB

–75

750 800 850 900 950 1000 1050 1100 1150

LO FREQ UENCY (MHz )

09576-011

Figure 11. LO-to-BB Feedthrough vs. LO Frequency, LO Output Turned Off

30

–35

–40

–45

–50

–55

–60

RF-TO-BB FEEDTHROUGH (dBc)

–65

–70

750 800 850 900 950 1000 1050 1100 1150

RF FREQUENC Y (MHz)

09576-012

Figure 12. RF-to-BB Feedthrough vs. RF Frequency

0

5 101520253035404550

BASEBAND FREQUENCY (MHz)

09576-014

Figure 14. Input P1dB, Input IP2, and Input IP3 vs. Baseband Frequency

34 32 30 28 26 24 22 20 18

NOISE FI GURE (dB)

16 14 12 10

–35 –30 –25 –20 –15 –10 –5 0 5

INPUT BLOCKE R P OWER (dBm)

09576-015

Figure 15. Noise Figure vs. Input Blocker Level,

= 900 MHz (RF Blocker 5 MHz Offset)

f

LO

Rev. 0 | Page 10 of 36

ADRF6801

A

T

0

2.0

–5

–10

–15

–20

–25

–30

RF INPUT RET URN L OSS (dB)

–35

–40

750 800 850 900 950 1000 1050 1100 1150

RF FREQUENC Y ( MHz )

Figure 16. RF Input Return Loss vs. RF Frequency

0

–2

–4

L

–6

–8

–10

LOP, LON DIFFERENTI

12

OUTPUT RET URN LOSS (dB)

–14

1.9

1.8

1.7

1.6

1.5

VPTAT VOLTAGE (V )

1.4

1.3

1.2 –40 –15 10 35 60 85

09576-016

TEMPERATURE (°C)

09576-019

Figure 19. VPTAT vs. Temperature

3.5

3.0

2.5

AGE (V)

2.0

1.5

VTUNE VOL

1.0

TA = +85°C TA = +25°C TA = –40°C

–16

1500 1600 1700 1800 1900 2000 2100 2200 2300

LOP, LON OUTPUT FREQUENCY (MHz)

Figure 17. LO Output Return Loss vs. LO Output Frequency, LO Output

Enabled (1500 MHz to 2300 MHz), Measured through TC1-1-13 Balun

400

380

360

340

320

300

280

CURRENT (mA)

260

240

220

200

750 800 850 900 950 1000 1050 1100 1150

LO FREQ UENCY (MHz )

TA = +85°C T

= +25°C

A

T

= –40°C

A

Figure 18. 5 V Supply Currents vs. LO Frequency,

LO Output Enabled

0.5

09576-017

750 800 850 900 950 1000 1050 1 100 1150

LO FREQUENCY (MHz)

09576-020

Figure 20. VTUNE vs. LO Frequency

09576-018

Rev. 0 | Page 11 of 36

ANALOG DEVICES ADRF6801 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

TIMING CHARACTERISTICS

Timing Diagram

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS