Datasheet ADRF6604 Datasheet (ANALOG DEVICES)

2500 MHz to 2900 MHz Rx Mixer with

V

Integrated Fractional-N PLL and VCO

FEATURES

Rx mixer with integrated fractional-N PLL RF input frequency range: 1200 MHz to 3600 MHz Internal LO frequency range: 2500 MHz to 2900 MHz Input P1dB: 14.5 dBm Input IP3: 27.5 dBm IIP3 optimization via external pin SSB noise figure

IP3SET pin open: 14.3 dB

IP3SET pin at 3.3 V: 15.5 dB Voltage conversion gain: 6.8 dB Matched 200 Ω IF output impedance IF 3 dB bandwidth: 500 MHz Programmable via 3-wire SPI interface 40-lead, 6 mm × 6 mm LFCSP

APPLICATIONS

Cellular base stations

GENERAL DESCRIPTION

The ADRF6604 is a high dynamic range active mixer with integrated phase-locked loop (PLL) and voltage controlled oscillator (VCO). The PLL/synthesizer uses a fractional-N PLL to generate a f can be divided or multiplied and then applied to the PLL phase frequency detector (PFD).

LODRV_EN

MUXOUT

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

input to the mixer. The reference input

LO

CC1

CC2VCC_LOVCC_MIXVCC_V2IVCC_LO

36

LON

37

38

LOP

16

PLL_EN

DATA

CLK

REF_IN

12

13

14

LE

6

8

SPI

INTERFACE

×2

MUX

÷2

÷4

FRACTION

TEMP

SENSOR

7 11 15 20 21 23 24 25 28 30 31 35

FUNCTIONAL BLOCK DIAGRAM

PHASE

INTEGER

N COUNTER

21 TO 123

MODULUS

REG

THIRD-ORDER

FRACTIONAL

INTERP OLAT OR

– +

FREQUENCY

DETECTOR

GND

REG

Figure 1.

ADRF6604

The PLL can support input reference frequencies from 12 MHz to 160 MHz. The PFD output controls a charge pump whose output drives an off-chip loop filter.

The loop filter output is then applied to an integrated VCO. The VCO output at 2 × f programmable PLL divider. The programmable PLL divider is controlled by a sigma-delta (Σ-) modulator (SDM). The modulus of the SDM can be programmed from 1 to 2047.

The active mixer converts the single-ended, 50  RF input to a differential, 200 Ω IF output. The IF output can operate up to 500 MHz.

The ADRF6604 is fabricated using an advanced silicon-germanium BiCMOS process. It is available in a 40-lead, RoHS-compliant, 6 mm × 6 mm LFCSP with an exposed paddle. Performance is specified over the −40°C to +85°C temperature range.

Table 1.

Internal LO

Part No.

Range

ADRF6601 750 MHz 300 MHz 450 MHz

1160 MHz 2500 MHz 1600 MHz

ADRF6602 1550 MHz 1000 MHz 1350 MHz

2150 MHz 3100 MHz 2750 MHz

ADRF6603 2100 MHz 1100 MHz 1450 MHz

2600 MHz 3200 MHz 2850 MHz

ADRF6604 2500 MHz 1200 MHz 1600 MHz

2900 MHz 3600 MHz 3200 MHz

2717101 22

34

BUFFER

PRESCALER

÷2

CHARGE PUMP 250µA, 500µA (DEFAULT), 750µA, 1000µA

54

R

SET

is applied to an LO divider, as well as to a

LO

±3 dB RF Balun Range

ADRF6604

INTERNAL LO RANGE 2500MHz TO 2900MHz

DIV

2:1

BY

MUX

2, 1

VCO

CORE

3

CP VTUNE

IFP

191839

IFN

NC

32 33

NC

3.3V LDO

2.5V LDO

VCO LDO

IN

40

26

29

2

DECL3P3

9

DECL2P5

DECLVCO

RF

IP3SET

±1 dB RFIN Balun Range

IN

8553-001

ADRF6604

REVISION HISTORY

5/11—Rev. 0 to Rev. A

Changes to Features and General Description Sections.............. 1

Changes to Table 2............................................................................ 3

Changes to Synthesizer Specifications Parameter and to Phase

Noise Parameter, Table 3 ............................................................. 4

Changes to Power Supplies Parameter, Table 4 ............................ 4

Replaced Typical Performance Characteristics Section;

Renumbered Sequentially ........................................................... 9

Added Spurious Performance Section......................................... 15

Change to Figure 41 ....................................................................... 17

Changes to Figure 42...................................................................... 18

Changes to Theory of Operation Section.................................... 20

Changes to Figure 46...................................................................... 22

Added AC Test Fixture Section and Figure 47 ........................... 23

Changes to Evaluation Board Control Software Section and

Figure 48 ...................................................................................... 24

Changes to Figure 49...................................................................... 25

6/10—Revision 0: Initial Version

Rev. A | Page 2 of 32

ADRF6604

SPECIFICATIONS

RF SPECIFICATIONS

VS = 5 V, ambient temperature (TA) = 25°C, f

= 153.6 MHz, f

REF

using CDAC = 0xC and IP3SET = 3.3 V, unless otherwise noted.

Table 2.

Parameter Test Conditions/Commen Min Typ Max Unit

INTERNAL LO FREQUENCY RANGE 2500 2900 MHz RF INPUT FREQUENCY RANGE ±3 dB RF input range 1200 3600 MHz RF INPUT AT 2360 MHz

Input Return Loss Relative to 50 Ω (can be improved with external match) −16.2 dB Input P1dB 14.6 dBm Second-Order Intercept (IIP2) −5 dBm each tone (10 MHz spacing between tones) 54.5 dBm Third-Order Intercept (IIP3) −5 dBm each tone (10 MHz spacing between tones) 28 dBm Single-Sideband Noise Figure IP3SET = 3.3 V 14.8 dB

IP3SET = open 13.9 dB

LO-to-IF Leakage At 1× LO frequency, 50 Ω termination at the RF port −43 dBm

RF INPUT AT 2560 MHz

Input Return Loss Relative to 50 Ω (can be improved with external match) −21 dB Input P1dB 14.5 dBm Second-Order Intercept (IIP2) −5 dBm each tone (10 MHz spacing between tones) 58.2 dBm Third-Order Intercept (IIP3) −5 dBm each tone (10 MHz spacing between tones) 27.6 dBm Single-Sideband Noise Figure IP3SET = 3.3 V 14.9 dB

IP3SET = open 14.2 dB

LO-to-IF Leakage At 1× LO frequency, 50 Ω termination at the RF port −42 dBm

RF INPUT AT 2760 MHz

Input Return Loss Relative to 50 Ω (can be improved with external match) −20 dB Input P1dB 14.4 dBm Second-Order Intercept (IIP2) −5 dBm each tone (10 MHz spacing between tones) 64.4 dBm Third-Order Intercept (IIP3) −5 dBm each tone (10 MHz spacing between tones) 27 dBm Single-Sideband Noise Figure IP3SET = 3.3 V 15.5 dB

IP3SET = open 14.6 dB

LO-to-IF Leakage At 1× LO frequency, 50 Ω termination at the RF port −44 dBm

IF OUTPUT

Voltage Conversion Gain Differential 200 Ω load 6.8 dB IF Bandwidth Small signal 3 dB bandwidth 500 MHz Output Common-Mode Voltage External pull-up balun or inductors required 5 V Gain Flatness Over frequency range, any 5 MHz/50 MHz 0.2/0.5 dB Gain Variation Over full temperature range 1.3 dB Output Swing Differential 200 Ω load 2 V p-p Output Return Loss Relative to 200 Ω −15 dB

LO INPUT/OUTPUT (LOP, LON) Externally applied 1× LO input, inte al PLL disabled rn

Frequency Range 250 6000 MHz Output Level (LO as Output) 1× LO into a 50 Ω load, LO output buffer enabled −9 dBm Input Level (LO as Input) −6 0 +6 dBm Input Impedance 50 Ω

= 38.4 MH

PFD

ts

z, high-side LO injection, f = 140 MHz, IIP3 optimized

IF

Rev. A | Page 3 of 32

ADRF6604

SYNTHESIZER/PLL SPE

= 140 MHz, IIP3 optimi

f

IF

Table 3.

Parameter Test Conditions/Comments Min Typ Max Unit

SYNTHESIZER SPECIFICATIONS Synthesizer specifications referenced to 1× LO

Frequency Range 2500 2900 MHInternally generated LO z

Figure of Merit1 P

Reference Spurs f f

−82 dBc f >f PH ASE NOISE fLO = 2500 MHz to 2900 MHz, f

1 kHz to 10 kHz offset −87.7 dBc/Hz

100 kHz offset −96 dBc/Hz

−117 dBc500 kHz offset /Hz

1 MHz offset −126 dBc/Hz

5 MHz offset −142 dBc/Hz

10 MHz offset −148 dBc/Hz

20 MHz offset −150 dBc/Hz

Integrated Phase Noise 1 kHz to 40 MHz integration bandwidth 0.69

PFD Frequency 20 40 MHz RE T pins FERENCE CHARACTERISTICS REF_IN, MUXOU

REF_IN Input Frequency 12 160 MH z

REF_IN Input Capacitance 4 pF

MUXOUT Output Level

V

MUXOUT Duty Cycle 50 % CH ARGE PUMP

Pump Current Programmable to 250 μA, 500 μA, 750 μA, 1 mA 500 μA

Output Compliance Range 1 2.8 V

1

T ) is computed as pha as m sured across LO ran with f

he figure of merit (FOM

a

nd f power = 10 dBm

REF

CIFICATIONS

e (TA) = 25°C, f

turVS = 5 V, ambient tempera

zed using CDAC = 0xC and IP3SET = 3.3 V, unless otherwise noted.

(500 V/μs slew rate) w

se noise (dBc/Hz) – 10 log 10(f

= 153.6 MHz, f

REF

= 0 dBm −221.4 dBc/Hz/Hz

REF_IN

= 38.4 MHz

PFD

/4 −107 dBc

PFD

−80 dBc

PFD

(lock detect output selected) 0.25 V V

OL

(lock detect output selected) 2.7 V

OH

ith a 40 MHz f

. The FOM was computed at 50 kHz offset.

PFD

power = 4 dBm, f

REF

= 38.4 MHz

PFD

) – 20 log 10(fLO/f

PFD

). The FOM w

PFD

= 38.4 MHz, high-side LO injection,

PFD

ea the full ge, 0 MHz,

°rms

= 8

REF

LOGIC INPU ER SPECIFIC

V = 2 -side LO injection, fIF = 140 MHz, IIP3 optimize

= 5 V, ambient temperature (TA) 5°C, f

S

us xC and IP3SET = 3.3

ing CDAC = 0 V, unless otherwise noted.

T

able 4.

Pa Test Cond T p Max Unit

rameter itions/Comments Min y

T AND POW ATIONS

= 153.6 MHz, f

REF

= 38.4 MHz, high d

PFD

LOGIC INPUTS CLK, DATA , LE

Input High Voltage, V

Input Low Voltage, V

Input Current, I

Input Capacitance, C

1.4 3.3 V

INH

0 0.7 V

INL

0.1 μA

INH/IINL

IN

5 pF

POWER SUPPLIES VCC1, VCC2, VCC_LO, VCC_MIX, and VCC_V2I pins

Voltage Range 4.75 5 5.25 V

Supply Current PLL only 96 mA External LO mode (internal PLL disabled, IP3SET pin = 3.3 V, LO output buffer off) 164 mA Internal LO mode (internal PLL enabled, IP3SET pin = 3.3 V, LO output buffer on) 274 mA Internal LO mode (internal PLL enabled, IP3SET pin = 3.3 V, LO output buffer off) 260 mA Power-down mode 30 mA

Rev. A | Page 4 of 32

ADRF6604

TIMING CHARACTERISTICS

VCC2 = 5 V ± 5%.

Table 5.

Paramete

t1 20 e ns min LE setup tim t2 10 ns min DATA-to-CLK setup time t3 -CLK hold time 10 ns min DATA-to t4 25 CLK high duration ns min t5 CLK low duration 25 ns min t6 10 CLK-to-LE setup time ns min t7 20 in LE pulse width ns m

Timing Diagram

r Limit Unit Description

CLK

t

4

t

5

DATA

t

2

DB23 (MSB)

t

1

LE

DB22

t

3

DB2 DB1

(CONTROL BIT C(CONTROL BIT C3)

2)

(CO BIT C1)

DB0 (L

NTROL

SB)

t

7

6

08553-002

Figure 2. Timing Diagram

Rev. A | Page 5 of 32

ADRF6604

ABSOLUTE MAXIMUM R

Table 6.

Paramete

Supply Voltage, VC 2, VCC_LO,

Digital I/O, CLK, DA E, LODRV_EN,

VTUNE 3.3 V 0 V to IFP, IFN to VCC_V2I −0.3 V + 0.3 V RFIN 16 dBm LOP, LON, REF_IN 13 dBm θJA (Exposed Paddle Soldered Down) 35°C/W Maximum Junction Temperature 150°C Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C

r Rating

C1, VCC

VCC_MIX, VCC_V

PLL_EN

2I

TA, L

ATINGS

V to +5.5 V

−0.5

to +3.6 V

−0.3 V

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section o maximu de

f this specification is not implied. Exposure to absolute

m rating conditions for extended periods may affect

vice reliability.

ESD CAUTION

Rev. A | Page 6 of 32

ADRF6604

TION DESCRIPTIONS PIN CONFIGURATION AND FUNC

NC

VCC_LO

GND

LODRV_EN

LON

LOP

VTUNE

DECLVCO

38

39

40

PIN 1

11

VCC

GND

R

SET

RE

F_IN GND

XOUT

MU

2P5

DECL

VCC2

NOTES

1. NC = NO CONNECT . DO NOT CONNECT TO T HIS PIN.

2. THE EXPOSED PADDLE SHOULD BE SOLDERED TO A LOW IMPEDANCE GROUND PL AN

INDICATO R

2DECL3P3 3CP 4

ADRF6604

5 6 7 8 9

10

TOP VIEW

(Not to Scale)

11

12

13

ND

CLK

G

DATA

Figure 3. Pin Configuration

NC

GND

32

31

33

34

35

36

37

30 GND 29 IP3SET 28 GND 27 VCC_V2I

RF

26

IN

25

GND 24 GND 23 GND 22 VCC_MIX 21

GND

15

17

16

18

19

14

LE

20

O

IFP

IFN

GND

PLL_EN

VCC_L

E.

8553-003

Table 7. Pin Function Descriptions

Pin No. Mnemonic Description

1 VCC1

Power Supply for the 3.3 V LDO. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin

should be decoupled with a 100 pF capacitor and a 0.1 μF capacitor located close to the pin. 2 DECL3P3 Decoupling Node for 3.3 V LDO. Connect a 0.1 μF capacitor between this pin and ground. 3 CP Charge Pump Output Pin. Connect to VTUNE through the loop filter. 4, 7, 11, 15, 20,

GND Ground. Connect these pins to a low impedance ground plane. 21, 23, 24, 25, 28, 30, 31, 35

5 R

SET

Charge Pump Current. The nominal charge pump current can be set to 250 μA, 500 μA, 750 μA, or 1 mA using Bit DB11 and Bit DB10 in Register 4 and by setting Bit DB18 in Register 4 to 0 (internal reference current). In this mode, no external R

is required. If Bit DB18 is set to 1, the four nominal charge pump currents (I

SET

can be externally adjusted according to the following equation:

4.217

I

×

R

=

SET

6 REF_IN

Reference Input. Nominal input level is 1 V p-p. Input range is 12 MHz to 160 MHz. This pin is internally dc-

⎛ ⎜ ⎜ ⎝

I

NOMINAL

⎞

CP

⎟ ⎟ ⎠

37.8

−

biased and should be ac-coupled.

8 MUXOUT

Multiplexer Output. This output can be programmed to provide the reference output signal or the lock detect

signal. The output is selected by programming the appropriate register. 9 DECL2P5 Decoupling Node for 2.5 V LDO. Connect a 0.1 μF capacitor between this pin and ground. 10 VCC2

Power Supply for the 2.5 V LDO. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin

should be decoupled with a 100 pF capacitor and a 0.1 μF capacitor located close to the pin. 12 DATA Serial Data Input. The serial data input is loaded MSB first; the three LSBs are the control bits. 13 CLK

Serial Clock Input. The serial clock input is used to clock in the serial data to the registers. The data is latched

into the 24-bit shift register on the CLK rising edge. The maximum clock frequency is 20 MHz. 14 LE

Load Enable. When the LE input pin goes high, the data stored in the shift register is loaded into one of the

eight registers. The relevant latch is selected by the three control bits of the 24-bit word. 16 PLL_EN

PLL Enable. Switch between internal PLL and external LO input. When this pin is logic high, the mixer LO is

automatically switched to the internal PLL and the internal PLL is powered up. When this pin is logic low, the

internal PLL is powered down and the external LO input is routed to the mixer LO inputs. The SPI can also be

used to switch modes. 17, 34 VCC_LO

Power Supply. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin should be decoupled

with a 100 pF capacitor and a 0.1 μF capacitor located close to the pin. 18, 19 IFP, IFN Mixer IF Outputs. These outputs should be pulled to VCC_MIX with RF chokes.

NOMINAL

)

Rev. A | Page 7 of 32

ADRF6604

Pin No. Mnemonic Description

22 VCC_MIX

26 RFIN RF Input. Single-ended, 50 Ω. 27 VCC_V2I

29 IP3SET Connect a resistor from this pin to a 5 V supply to adjust IIP3. Normally leave open. 32, 33 NC NC = No Connect. Do not connect to this pin. 36 LODRV_EN

37, 38 LON, LOP

39 VTUNE

40 DECLVCO Decoupling Node for VCO LDO. Connect a 100 pF capacitor and a 10 μF capacitor between this pin and ground. EPAD Exposed Paddle. The exposed paddle should be soldered to a low impedance ground plane.

Power Supply. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin should be decoupled with a 100 pF capacitor and a 0.1 μF capacitor located close to the pin.

LO Driver Enable. Together with Pin 16 (PLL_EN), this digital input pin determines whether the LOP and LON pins operate as inputs or outputs. LOP and LON become inputs if the PLL_EN pin is low or if the PLL_EN pin is set high with the PLEN bit (DB6 in Register 5) set to 0. LOP and LON become outputs if either the LODRV_EN pin or the LDRV bit (DB3 in Register 5) is set to 1 while the PLL_EN pin is set high. The external LO drive frequency must be 1× LO. This pin has an internal 100 kΩ pull-down resistor.

Local Oscillator Input/Output. The internally generated 1× LO is available on these pins. When internal LO generation is disabled, an external 1× LO can be applied to these pins.

VCO Control Voltage Input. This pin is driven by the output of the loop filter. The nominal input voltage range on this pin is 1.5 V to 2.5 V.

Rev. A | Page 8 of 32

ADRF6604

TYPIC ERFORM

RF FREQUE

CDA terna ted high-side LO, RFIN = −5 d

AL P ANCE CHARACTERISTICS

NCY SWEEP

C = 0xC, in lly genera Bm, fIF = 140 MHz, unless otherwise noted.

5

IP3SET = OPEN

4

IP3SET = 3.3V

3

2

1

0

GAIN (dB)

–1

–2

–3

–4

–5

2360 2410 2510

2460 2560 2610 2660 2710 2760

RF FREQUENCY ( MHz)

TA = +85°C T

= +25°C

A

T

= –40°C

A

Figure 4. Gain vs. RF Frequency

90

IP3SET = OPEN IP3SET = 3.3V

80

70

60

INPUT IP2 (dBm)

50

40

30

2360 2410 2460 2510 2560 2610 2660 2710 2760

RF FREQUENCY (M Hz)

TA = +85°C T

= +25°C

A

T

= –40°C

A

Figure 5. Input IP2 vs. RF Frequency

553-104 08

08553-105

35

IP3SET = OPEN

34

IP3SET = 3.3V

33

32

31

30

29

28

27

UT IP3 (dBm)

26

INP

25

24

23

22

21 20

2360 2410 2460 2510 2560 2610 2660

Figure 7. Input IP3 vs. RF Frequency

18

IP3SET = OPEN

17

IP3SET = 3.3V

16

15

14

13

12

INPUT P1dB (dBm)

11

10

9

8

2360 2410 2460 2510 2560 2610 2660 2710 2760

Figure 8. Input P1dB vs. RF Frequency

RF FREQUENCY ( MHz)

TA = +85°C T

= +25°C

A

T

= –40°C

A

2710 2760

TA = +85°C T

= +25°C

A

T

= –40°C

A

7

08553-10

08553-108

20

18

16

14

12

10

8

NOISE FI GURE (dB)

6

4

IP3SET = OPEN

2

IP3SET = 3.3V

0

2360 2410 2460 2510 2560 2610 2660 2710 2760

RF FREQUENCY ( MHz)

Figure 6. Noise Figure vs. RF Frequency

TA = +85°C T

= +25°C

A

T

= –40°C

A

08553-106

Rev. A | Page 9 of 32

ADRF6604

IF FREQUENCY SWEEP

ted swept low-side LO, f = 2490 MHz, CDAC = 0xC, internally genera

5

IP3SET = OPEN

4

IP3SET = 3.3V

3

2

1

0

GAIN (dB)

–1

–2

–3

–4

–5

25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400

IF FREQUENCY (MHz)

Figure 9. Gain vs. IF Frequency

TA = +85°C T

= +25°C

A

T

= –40°C

A

RF

08553-109

RFIN = −5 dBm, unless otherwise noted.

45

IP3SET = OPEN

40

IP3SET = 3.3V

35

30

25

20

INPUT IP3 (dBm)

15

10

5

25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400

Figure 12. Input IP3 vs. IF Frequency, RF

IF FREQUENCY (MHz)

TA = +85°C T

= +25°C

A

T

= –40°C

A

= −5 dBm

IN

08553-112

90

IP3SET = OPEN IP3SET = 3.3V

80

70

60

INPUT IP2 (dBm)

50

40

30

25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400

IF FREQUENCY (MHz)

Figure 10. Input IP2 vs. IF Frequency, RF

20

18

16

14

12

10

8

NOISE FI GURE (dB)

6

4

IP3SET = OPEN

2

IP3SET = 3.3V

0

25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400

IF FREQUENCY (MHz)

TA = +85°C T

= +25°C

A

T

= –40°C

A

= −5 dBm

IN

TA = +85°C T

= +25°C

A

T

= –40°C

A

Figure 11. Noise Figure vs. IF Frequency

20

18

16

14

12

10

8

INPUT P1dB (dBm)

6

4

IP3SET = OPEN

2

IP3SET = 3.3V

0

25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400

08553-110

IF FREQUENCY (MHz)

TA = +85°C T

= +25°C

A

T

= –40°C

A

08553-113

Figure 13. Input P1dB vs. IF Frequency

08553-111

Rev. A | Page 10 of 32

ADRF6604

–

0

IP3SET = OPEN

–5

IP3SET = 3.3V

–10

–15

–20

–25

–30

–35

–40

–45

LO-TO -IF FEE DTHROUGH (dBm)

–50

–55

–60

2500 2550 2600 2650 2700 2750 2800 2850 2900

LO FREQUENCY (MHz)

T = +85° C

A

= +25°C

T

A

T

= –40°C

A

Figure 14. LO-to-IF Feedthrough vs. LO Frequency,

LO Output Turned Off, CDAC = 0xC

20

IP3SET = OPEN IP3SET = 3.3V

2500 2550 2600 2650 2700 2750 2800 2850 2900

LO FREQUENCY (MHz)

LO-TO- RF LEAKAGE (dBm)

–25

–30

–35

–40

–45

–50

–55

–60

–65

–70

–75

–80

–85

–90

TA = +85°C T

= +25°C

A

T

= –40°C

A

Figure 15. LO-to-RF Leakage vs. LO Frequency, LO Output Turned Off

0

–1

–2

–3

–4

–5

–6

–7

–8

–9

–10

RETURN LOSS (d B)

–11

–12

–13

–14

–15

2300 2400 2500 2600 2700 2800 2900 3000 3100

08553-114

LO FREQUENCY (MHz)

08553-117

Figure 17. LO Input Return Loss vs. LO Frequency (Including TC1-1-13 Balun)

350

300

250

200

150

RESISTANCE (Ω)

100

50

0

50 100 150 200 250 300 350 400 450 500

08553-115

RESISTANCE

CAPACITANCE

IF FREQUENCY (MHz)

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

CAPACITANCE (pF )

08553-118

Figure 18. IF Differential Output Impedance (R Parallel, C Equivalent)

0

–5

–10

–15

–20

–25

–30

RETURN LOSS (d B)

–35

–40

–45

–50

2300 2400 2500 2600 2700 2800 2900 3000 3100

RF FREQUENCY ( MHz)

Figu cy re 16. RF Input Return Loss vs. RF Frequen

08553-116

35

IP3SET = OPEN IP3SET = 3.3V

30

25

20

NOISE FI GURE (dB)

15

10

–60 –50 –40 –30 –20 –10 0

Figure 19. SSB Noise Figure vs. z Offset CW Blocker Level,

CW BLOCKER LEVEL (dBm)

5 MH

08553-119

LO Frequency = 2500 MHz, RF Frequency = 2358 MHz

Rev. A | Page 11 of 32

ADRF6604

0

–5

–10

–15

–20

–25

–30

–35

–40

–45

RF-TO-IF ISOLATION (dBc)

IP3SET = OPEN

–50

IP3SET = 3.3V

–55

–60

2160 2260 2360 2460 2560 2660 2760 2860 2960

RF FREQUENCY ( MHz)

TA = +85°C T

= +25°C

A

T

= –40°C

A

Figure 20. R 140 MHz, F-to-IF Isolation vs. RF Frequency, High-Side LO, IF =

LO Output Turned Off

0

IP3SET = OPEN

–1

IP3SET = 3.3V

–2

–3

–4

–5

–6

–7

–8

–9

–10

–11

–12

LO OUTPUT AMPLITUDE (dBm)

–13

–14

–15

2500 2550 2600 2650 2700 2750 2800 2850 2900

LO FREQUENCY (MHz)

TA = +85°C T

= +25°C

A

T

= –40°C

A

Figure 21. LO Output Amplitude vs. LO Frequency

5.0

4.5

4.0

3.5

3.0

2.5

VOLTAGE (V)

2.0

TUNE

V

1.5

1.0

0.5

0

2500 2550 2600 2650 2700 2750 2800 2850 2900

08553-120

LO FREQUENCY (MHz)

TA = +85°C T

= +25°C

A

T

= –40°C

A

08553-123

Figure 23. VTUNE vs. LO Frequency

350

IP3SET = OPEN IP3SET = 3.3V

300

250

200

SUPPLY CURRENT (mA)

150

100

2500 2550 2600 2650 2700 2750 2800 2850 2900

08553-121

LO FREQUENCY (MHz)

TA = +85°C T

= +25°C

A

T

= –40°C

A

08553-124

Figure 24. Supply Current vs. LO Frequency

25

20

15

10

5

0

–5

–10

–15

–20

FREQUENCY DEVI ATION F ROM 2500MHz (M Hz)

–25

0 50 100 150 200 250

TIME (µs)

Figure 22. Frequency Deviation from 2500 MHz vs. Time

(Demonstrat 2500 MHz) es LO Frequency Settling Time from 2490 MHz to

08553-122

Rev. A | Page 12 of 32

2.5

2.4

2.3

2.2

2.1

2.0

1.9

1.8

1.7

1.6

1.5

VPTAT VOLTAGE (V)

1.4

1.3

1.2

1.1

1.0

IP3SET = OPEN IP3SET = 3.3V

–55 –35 –15 5 25 45 65 85 105

TEMPERATURE (°C)

Figure 25. VPTAT Voltage vs. Temperature (IP3SET = Optimized, Ope )

08553-125

n

ADRF6604

Complementary cumulative distribution function (CCDF), fRF = 2360 MHz, fIF = 140 MHz.

100

DISTRIBUTI ON PERCENTAG E (%)

IP3SET = OPEN

90

IP3SET =

3.3V

80

TA = +85°C

70

T

= +25°C

A

T

= –40°C

60

50

40

30

20

10

A

0 –0.5 0 0.5 1.0 1.5 2.0

GAIN (dB)

Figure 26. Gain

26

08553-1

100

DISTRIBUTI ON PERCENTAG E (%)

90

80

70

60

50

40

30

20

10

0

22 23

IP3SET = OPEN IP3SET =

3.3V

TA = +85°C T

= +25°C

A

T

= –40°C

A

24 25 26 27 28

INPUT IP3 (dBm)

Figure 29. Input IP3

29 30

08553-129

100

DISTRIBUTI ON PERCENTAG E (%)

IP3SET = OPEN

90

IP3SET =

3.3V

80

70

60

50

40

30

20

10

0

45 50 55 60 65 70

INPUT IP2 (dBm)

TA = +85°C T

A

T

A

Figure 27. Input IP2

100

IP3SET = OPEN

90

80

70

60

50

40

30

20

DISTRIBUTI ON PERCENTAG E (%)

10

0

10 11 12 13 14 15 16 17 18 19 20

NOISE FI GURE (dB)

TA = +85°C T

A

T

A

Figure 28. Noise Figure

= +25°C = –40°C

100

DISTRIBUTION PERCENTAGE (%)

75

08553-127

IP3SET =

90

OPEN IP3SET =

3.3V

80

70

60

50

40

30

20

10

0

10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.5 14.0 14.5 15.0

TA = +85°C T

= +25°C

A

T

= –40°C

A

INPUT P1dB (dBm)

15.5 16.0

08553-130

Figure 30. Input P1dB

100

DISTRIBUTI ON PERCENTAG E (%)

128

08553-

IP3SET = OPEN IP3SET = 3.3V

90

80

TA = +85°C T

= +25°C

70

60

50

40

30

20

10

A

T

= –40°C

A

0

–50 –48 –46 –44 –42 –40 –38 –36

LO FEEDT HROUGH TO I F (dBm)

3-131 0855

Figure 31. LO Feedthrough to IF, LO Output Turned Off

Rev. A | Page 13 of 32

ADRF6604

–

Measured at IF output, CDAC = 0xC, IP3SET = open, internally generated high-side LO, f RF

= −5 dBm, fIF = 140 MHz, unless otherwise noted. Phase noise measurements made at LO output, unless otherwise noted.

IN

70

LO FREQ UENCY = 2883.2MHz

–80

–90

–100

–110

LO FREQ UENCY = 2537.6MHz

–120

–130

PHASE NOISE (dBc/Hz)

–140

–150

–160

1k 1M 10M 100M 1G

FFSET FREQUENC

O Y (Hz)

Figure 32. Phase Noise vs. Offset Frequency

TA = +85°C T

= +25°C

A

T

= –40°C

A

08553-132

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

INTEGRATED PHASE NOISE (° rms)

0.1

0 2500 2550 2600 2650 2700 2750 2800 2850 2900

= 153.6 MHz, f

REF

TA = +85°C T

= +25°C

A

T

= –40°C

A

LO FREQUENCY (MHz)

Figure 35. Integrated Phase Noise vs. LO Frequency

= 38.4 MHz,

PFD

08553-135

70

–75

–80

–85

–90

–95

SPURS LEVEL (dBc)

–100

–105

–110

TA = +85°C T

= +25°C

A

T

= –40°C

A

2500 2550 2600 2650 2700 2750 2800 2850 2900

LO FREQUENCY (MHz

OFFSET AT 2× PFD OFFSET AT 4× PFD

)

08553-133

Figure 33. PLL Reference Spurs vs. LO Frequency (2× PFD and 4× PFD)

70

OFFSET AT 3× PFD OFFSET AT 1× PFD

–75

–80

–85

–90

–95

SPURS LEVEL (dBc)

–100

–105

–110

2500 2550 2600 2650 2700 2750 2800 2850 2900

OFFSE T AT 0.25× PFD

LO FREQUENCY (MHz)

TA = +85°C T

= +25°C

A

T

= –40°C

A

08 34553-1

Figure 34. PLL Reference Spurs vs. LO Frequency (0.25× PFD, 1× PFD, and 3× PFD)

80

–90

–100

–110

–120

–130

PHASE NOISE (d Bc/Hz)

–140

–150

2500 2550 2600 2650 2700 2750 2800 2850 2900

OFFSET = 1kHz

OFFSET = 100kHz

OFFSET = 5MHz

LO FREQUENCY (MHz)

TA = +85°C T

= +25°C

A

T

= –40°C

A

08553-136

Figure 36. Phase Noise vs. LO Frequency (1 kHz, 100 kHz, and 5 MHz Steps)

80

–85

–90

–95

–100

–105

–110

–115

PHASE NOISE (d Bc/Hz)

–120

–125

–130

2500 2550 2600 2650 2700 2750 2800 2850 2900

OFFSE T = 10kHz

OFFSET = 1MHz

LO FREQUENCY (MHz)

TA = +85°C T

= +25°C

A

T

= –40°C

A

08553-137

Figure 37. Phase Noise vs. LO Frequency (10 kHz, 1 MHz Steps)

Rev. A | Page 14 of 32

ADRF6604

SPURIOUS PERFORMANCE

(N × fRF) − (M × fLO) spur measurements were made using the standard evaluation board (see the Evaluation Board section). Mixer spu products were measured in decibels relative to the carrier (dBc) from the IF output power level. All spurious components greater than

−125 dBc are shown.

LO = 2500 MHz, RF = 2360 MHz (horizontal axis is M, vertical axis is N), and RF

0 1 2

N

3 4 5 6 7

0 1 2 3 4

-115.19 −43.0184 −33.3455

−23.6708 0.0 −67.1671 −47.1921

−63.4281 −65.1191 −61.1065 −79.8957 −80.0324

−83.6746 −86.8944 −58.5001 −105.514

−108.708 −104.041 −108.518

−110.825 −113.19

−108.548

M

power = 0 dBm.

IN

LO = 2700 MHz, RF = 2560 MHz (horizontal axis is M, vertical axis is N), and RF

0 −114.804 −42.7987 −31.9174 1 −22.6289 0.0 −65.0063 −48.5279 2 −61.2522 −66.5602 −57.5224 −77.0905 −76.8305

N

3 −84.4436 −82.5056 −56.9437 −98.8811 4 5 6 7

0 1 2 3 4

−108.087 −98.5103 −99.2295

M

−110.572 −113.601

power = 0 dBm.

IN

−109.829

LO al axis is N),

= 2900 MHz, RF = 2760 MHz (horizontal axis is M, vertic and RF

0 −114.956 −44.0336 −31.2423 1 −22.092 0.0 −62.6978 −48.9358 2 −60.2824 −69.8043 −56.7826 −73.218

N

3 −85.957 −80.7407 −56.7503 −105.061 4 5 6 7

0 1 2 3 4

−108.949 −100.938 −100.159

−110.193 −111.146

M

power = 0 dBm.

IN

−111.428

rious

Rev. A | Page 15 of 32

ADRF6604

REGISTER STRUCTURE

This section provides the register maps for the ADRF6604. The three LSBs determine the register that is programmed.

REGISTER 0—INT

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0000 0 4 C3(

EGER DIVIDE CONTROL (DEFAULT: 0x0001C0)

RESERVED

00000000 DMID6ID5IDID3ID2ID1ID0 0)C2(0)C1(0)

DM

0

1

ID6 ID5 ID4 ID3 ID2 ID1 ID0

0010101

0010110

0010111

0011000

... ... ... ... ... ... ...

... . ... ... ... ... ...

01110 0

... ... ... .. ...

... ... ...

11 01

11 10

1 10

11110

igure 38. Register 0—Integ r Divide Control Register Ma

F e p

DIVIDE MODE

FRACTIONAL

INTEGER

..

... ... .

... ... ... ...

11

11 10

(DEFAULT)

1 11

1

INTEGER DI VIDE

0

00

01

11

RATIO CO NTROL BIT S

INTEGER DIVI

21 (INTEG ER M DE ONLY)

22 (INTEG ER M DE ONLY)

23 (INTEG ER MODE ONL Y)

24

...

56 (DEFAULT)

...

119

120 (INTEGE R M

121 (INTEGE R

122 (INTEGE R

123 (INTEGE R

DE RATIO

O

ODE ONLY)

MODE ONLY)

08553-004

REGISTER 1—MODULUS DIVIDE CONTROL (DEFAULT: 0x003001)

DB23 DB22 DB21 DB20 DB19 DB18 DB17 6 DB15 DB14 DB13 DB1 DB10 DB9 DB8 D DB6 DB5 DB4 DB3 2 DB1 DB0

0 0 0 0 0 MD10 MD MD6 MD5 M 4 MD3 MD2 MD1 MD0 3(0) C2(0) C1(1)

0 0 0 0 0 9 MD8 MD7 D C

RESERVED

DB1 2 DB11 B7 DB

MD10MD9M D6MD5MD4 2MD1MD0

0 0000000001

0 0000000010

... ... ... . .. ... ... ...

... ... ... ... ... ... ... ... ...

1 1000000000

... ... ... ... ... ... ... ... ... ... ...

1 1111111111

D8MD7M MD3MD

... ... ... ...

Figure 39. Register 1—Modulus Divide Control Register Map

Rev. A | Page 16 of 32

MODULUS VALUE

... ...

CONTROL BI TS

ODULUS VALUE

M

1

2

...

1536 (DEFAUL

.....

.

2047

T)

08553-005

ADRF6604

IVIDE CONTROL (DEFAULT: 0x001802) REGISTER 2—FRACTIONAL D

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

FRACTIONAL VALUERESERVED

FD5FD4FD3FD2FD1FD0C3(0)C2(1)C1(0)0000000000FD10FD9FD8FD7FD6

CONTROL BI TS

FD10FD9FD8FD7FD6FD5FD4FD3FD2FD1FD0

0 0000000000

0 0000000001

... ... ... ... ... ... ... ... ... ... ...

0 1100000000

... ... ... ... ... ... ... ... ... ... ...

FRACTIONAL VALUE MUST BE LESS THAN MO DULUS

Figure 40. Register 2—Fractional Divide Control Register Map

REGISTER 3—Σ-Δ MODULATOR DITHER CONTROL (DEFAULT: 0x10000B)

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 DITH1 DIT H0 DE N DV16 DV15 DV14 DV13 DV12 DV11 DV10 DV9 DV8 DV7 DV6 DV5 DV4 DV3 DV2 DV1 DV0 C3(0) C2(1) C1(1)

DITH1 DI TH0 00 01

10

11

DITHER

MAGNITUDE

DITHER MAGNITUDE 15 (DEFAULT ) 7

3

1 (RECOMMENDED)

DITHER

ENABLE

DEN 0 1

DITHER RESTART VALUE CONTROL BI TS

DITHER ENABLE DISABLE ENABLE (DEFAULT, RECOMME NDED)

FRACTIONAL VALUE

0

1

...

768 (DEFAULT )

...

<MDR

08553-006

DV16 DV15 DV14 DV13 DV12 DV11 DV10 DV9 DV8 DV7 DV6 DV5 DV4 DV3 DV2 DV1 DV0

00000000000000001

... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...

11111111111111111

Figure 41. Register 3—Σ-Δ Modulator Dither Contro

l Register Map

DITHER RESTART VALUE

0x00001 (DEFAULT )

... ... 0x1FFFF

8553-007

Rev. A | Page 17 of 32

ADRF6604

ROL (DEFAULT: 0x0AA7E4) REGISTER 4—PLL CHARGE PUMP, PFD, AND REFERENCE PATH CONT

REF OUTPUT MUX SELECT

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

RMS2 RMS1 RMS0 RS1 RS0 CPM CPBD CPB4 CPB3 CPB2 CPB1 CPB0 CPP1 CPP0 CPS CPC1 CPC0 PE1 PE0 PAB1 PAB0 C3(1) C2(0) C1(0)

INPUT REF

PATH

CP

CURRENT

REF

SOURCE

PFD POL

PFD PHASE OFFSET

MULTIPLIER

CP

CURRENT

CP

SRC

CP

CONTROL

PFD EDG E CONT ROL BITS

PFD ANTI-

BACKLASH

DELAY

CPB4 CPB3 CPB2 CPB1 CPB0

0000 0 0000 1 0011 0 0101 0 1000 0 1111 1

CPC1 CP C0

00 01 10 11

CHARGE PUMP CONTROL SOURCE

CPS

CONTROL BASE D ON STATE OF DB7 AND DB8 (CP CONT ROL)

0

CONTROL FRO M PFD (DEFAUL T)

1

CPP1 CPP0

00 01 10 11

PFD PHASE OFFSET MULTIPLIER

0 × 22.5°/I 1 × 22.5°/I 6 × 22.5°/I 10 × 22.5°/I 16 × 22.5°/I 31 × 22.5°/I

CHARGE PUMP CURRENT

250µA 500µA (DEFAUL T) 750µA 1000µA

CPMULT CPMULT

(RECOMMENDED)

CPMULT

(DEFAULT)

CPMULT CPMULT CPMULT

PAB1 PAB0

00 01 10 11

REFERENCE PATH EDGE

PE0

SENSITIVITY

0

FALLING EDGE RISING EDGE (DEFAULT)

1

DIVIDER PATH EDG E

PE1

SENSITIVITY

0

FALLING EDGE RISING EDG E (DEFAULT )

1

CHARGE PUMP CONTROL

BOTH ON PUMP DOWN PUMP UP TRISTATE (DEFAULT)

PFD ANTIBACKLASH DELAY

0ns (DEFAULT )

0.5ns

0.75ns

0.9ns

RMS2 RMS1 RMS0

000 001 010 011 100 101 110 111

CP

0 1

CHARGE PUMP CURRENT

CPM

REFERENCE SOURCE INTERNAL (DEF AULT)

0

EXTERNAL

1

RS1 RS0

00 01 10 11

REF OUTPUT MUX SELECT

LOCK DETECT (DEFAULT) VPTAT REF_IN (BUFFERED)

0.5 × REFIN ( BUFFERED) 2 × REFIN (BUFFERED) TRISTATE RESERVED RESERVED

INPUT REFERENCE PATH SOURCE

2 × REFIN REFIN ( DEFAUL T)

0.5 × REFI N

0.25 × REFIN

Figure 42. Register 4—PLL Charge Pump, PFD, and Reference Path Control Register Map

BD

PFD PHASE OFFSET POLARITY

NEGATIVE POSITIVE (DEFAULT)

Rev. A | Page 18 of 32

08553-008

ADRF6604

REGISTER 5—PLL ENABLE AND LO PATH CONTROL (DEFAULT: 0x0000E5)

LO

RESERVED

DB23 DB22 DB21 DB20 DB 19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB 11 DB10 DB9 DB8 DB7

000 0 0000000 0

CAP DAC CONTRO L BITS

CD3 CD2 CD1 CD0 PLEN L DV1 LXL LDRV C3(1) C2(0) C1(1)

PLLENLO

DIV1

LDV2

DIV1LOEXTLODRV

DB6 DB5 DB4 DB3 DB2 DB1 DB0

CAPACITOR DAC

CD3 CD2 CD1 CD0

0000

... ... ... ...

1111

CONTROL F OR IIP3 OPTIMIZATION

MIN ... MAX

LDV2

DIVIDE-BY- 2 OR 1

DIVIDE BY 1

0

DIVIDE BY 2 (DE FAULT)

1

Figure 43. Register 5—PLL Enable and LO Path Control Register Map

REGISTER 6—VCO CONTROL AND VCO ENABLE (DEFAULT: 0x1E2106)

DB23

000

CPEN

0 1

CHARGE

PUMP

DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

CHARGE PUMP ENABLE

DISABLE ENABLE (DEFAULT)

ENABLE

L3EN 3.3V LDO ENABLE

DISABLE

0

ENABLE (DEFAULT)

1

LVEN VCO LDO ENABLE

0 1

3.3V VCO LDO

LDO

ENABLE

CPEN L3EN VCO EN VCO SW VC5

DISABLE ENABLE (DEFAULT)

LVEN

VCO

ENABLE

VCO EN

0 1

VCO

SWITCH

VCO SW

0 1

VCO SWIT CH CONTROL FROM SPI

REGULAR (DEFAUL T) BAND CAL

VCO ENABLE

DISABLE ENABLE (DEFAULT)

Figure 44. Register 6—VCO Control and VCO Enable Register Map

VCO

VCO AMPLITUDERESERVED

VC4 VC3 VC2 VC1 VC0 VBSRC VBS5 VBS4 VBS3 VBS2 VBS1 VBS0 C3(1) C2(1) C1(0)

VC[5:0] VCO AMPLITUDE

0x00 0 …. ….

0x18 24 (DEFAULT) …. ….

0x2B 43 …. ….

0x3F 63 ( RECOMMENDED)

BW SW

CTRL

VBSRC

0 1

LO OUTPUT DRIVER

LDRV

ENABLE

DRIVER OFF (DEFAULT)

0

DRIVER ON

1

EXTERNAL LO DRIVE

LXL

ENABLE (PIN 37, PIN 38)

INTERNAL LO OUTPUT (DEFAULT)

0

EXTERNAL LO INPUT

1

DIVIDE-BY-2 I N LO CHAIN E NABLE

LDV1

DIVIDE BY 1

0

DIVIDE BY 2 (DEFAULT)

1

PLEN

PLL ENABLE

DISABLE

0

ENABLE (DEFAULT)

1

VCO BAND SELECT FROM SPI

VBS[5:0] VCO BAND SELECT FROM SPI

0x00 0x01

…. 0x20

…. 0x3F

VCO BW CAL AND SW SOURCE CONTRO L

BAND CAL (DEFAULT ) SPI

DEFAULT

CONTROL BI TS

08553-009

08553-010

REGISTER 7—MIXER BIAS ENABLE AND EXTERNAL VCO ENABLE (DEFAULT: 0x000007)

MIXER

XVCORES

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0XVCO

B_EN

MBE0 0 0000000000000000C3(1)C2(1)C1(1)

MIXER BIAS ENABL E

MBE

ENABLE (DEFAULT)

0

DISABLE

1

EXTERNAL VCO

XVCO

INTERNAL VCO (DEFAULT)

0 1

EXTERNAL V

CO

Figure 45. Register 7—Mixer Bias Enable and External VCO Enable Register Map

RESERVED CONTROL BITS

Rev. A | Page 19 of 32

8553-011

ADRF6604

THEORY OF OPERATION

The ADRF6604 integrates a high performance downconverting mixer with a state-of-the-art fractional-N PLL. The PLL also integrates a low noise VCO. The SPI port allows the user to control the fractional-N PLL functions and the mixer optimization functions, as well as allowing for an externally applied LO or VCO.

The mixer core within the ADRF6604 is the next generation of an industry-leading family of mixers from Analog Devices, Inc. The RF input is converted to a current and then mixed down to IF using high performance NPN transistors. The mixer output currents are transformed to a differential output. The high performance active mixer core results in an exceptional IIP3 and IP1dB with a very low output noise floor for excellent dynamic range. Over the specified frequency range, the ADRF6604 typically provides IF input P1dB of 14.5 dBm and IIP3 of 27.5 dBm.

Improved performance at specific frequencies can be achieved with the use of the internal capacitor DAC (CDAC), which is programmable via the SPI port, and by us supply from the IP3SET pin (Pin 29). Adju

AC allows increments in phase shift at internal nodes in the

D ADRF6604, thus allowing cancellation of third-order distortion with no change in supply current. Connecting a resistor to a 5 V supply from the IP3SET pin increases the internal mixer core current, thereby improving overall IIP2 and IIP3, as well as IP1dB. Using the IP3SET pin for this purpose increases the overall supply current.

The fractional divide function of the PLL allows the frequency multiplication value from REF_IN to LO output to be a fractional value rather than to be restricted to an integer value as in traditional PLLs. In operation, this multiplication value is

INT + (FRAC/MOD)

where:

INT is the integer value. FRAC is the fractional value. MOD is the modulus value.

The INT, FRAC, and MOD values are all programmable via the SPI port. In other fractional-N PLL designs, fractional multiplication is achieved by periodically changin

a deterministic way. The disadvantage of this approach is that

in there are often spurious components close to the fundamental signal. In the ADRF6604, a Σ- modulator is used to distribute the fractional value randomly, thus significantly reducing the spurious content due to the fractional function.

ing a resistor to a 5 V stment of the capacitor

g the fractional value

PROGRAMMING THE ADRF6604

The ADRF6604 is programmed via a 3-pin SPI port. The timing requirements for the SPI port are shown in Figure 2. Eight programmable registers, each with 24 bits, control the operation of the device. The register functions are listed in Tabl e 8 .

Table 8. ADRF6604 Register Functions

Register Function

Register 0 Integer divide control for the PLL Register 1 Modulus divide control for the PLL Register 2 Fractional divide control for the PLL Register 3 Σ-Δ modulator dither control Register 4 PLL charge pump, PFD, reference path control Register 5 PLL enable and LO path control Register 6 VCO control and VCO enable Register 7 Mixer bias enable and external VCO enable

Note that internal calibration for the PLL must be run when the ADRF6604 is initialized at a given frequency. This calibration is run automatically whenever Register 0, Register 1, or Register 2 is programmed. Because the other registers affect PLL performance, Register 0, Register 1, and Register 2 should always be programmed last and in the following order: Register 0, Register 1, Register 2.

To program the frequenc programs only Register 0, Register 1, and Register 2. However, if registers other t should be insert ensures that the VCO band calibration has sufficient time to complete before the final band calibration for Register 0 is initiated.

Software is available on the ADRF6604 product page under the Evaluation Boards & Kits section that allows easy programming from a PC running Windows® XP or Vista.

ed before programming Register 0. This delay

y of the ADRF6604, the user typically

han these are programmed first, a short delay

INITIALIZATION SEQUENCE

To ensure proper power-up of the ADRF6604, it is important to reset the PLL circuitry after the VCC supply rail settles to 5 V ±

0.25 V. Resetting the PLL ensures that the internal bias cells are properly configured, even under poor supply start-up conditions.

To ensure that the PLL is reset after power-up, use the following procedure:

1. Disable the PLL by setting the PLEN bit to 0 (Register 5,

Bit DB6).

2. After a delay of >10

Bit DB6).

After this procedure is completed, the o be programmed in the following order: Register 7, Register 6, Register 4, Register 3, Register 2, Register 1. Then, after a delay of >100 ms, Register 0 should be programmed.

0 ms, set the PLEN bit to 1 (Register 5,

ther registers should

Rev. A | Page 20 of 32

ADRF6604

LO SELECTION LOGIC

The downconverting mixer in the ADRF6604 can be used without the internal PLL by applying an external differential LO to Pin 37 (LON) and Pin 38 (LOP). In addition, when using an LO generated by the internal PLL, the LO signal can be acc directly at these pins. This function can be used for debugging purposes, or the internally generated LO can be used as the LO for a separate mixer.

Table 9. LO Selection Logic

Pins1 Reg

Pin 16 (PLL_EN) Pin 36 (LODRV_EN) Bit DB6 (PLEN) Bit DB3 (LDRV) Output Buffer LO

0 X 0 X Disabled External 0 X 1 X Disabled External 1 X 0 X Disabled External 1 0 1 0 Disabled Internal 1 X 1 1 Enabled Internal 1 1 1 X Enabled Internal

1

X = don’t care.

essed

ister 5 B

The operation of the LO generation and whether LOP and LON are inputs or outputs are determined by the logic levels applied at Pin 16 (PLL_EN) and Pin 36 (LODRV_EN (LDRV) a DB6 (PLEN externally a d logic and internal bits required f LO functio given in Tab l e 9 .

nd Bit ) in Register 5. The combination of

pplie or particular

ns is

), as well as Bit DB3

its1 Outputs

Rev. A | Page 21 of 32

ADRF6604

O

APPLICATIONS INF

ORMATION

BASIC CONNECTIONS FOR OPERATION

Figure 46 shows the basic connections for the ADRF6604 evaluation board. The six power supply pins should be individually decoupled using 100 pF and 0.1 µF capacitors located as close as possible to the device. In addition, the internal decoupling nodes (DECL3P3, DECL2P5, and DECLVCO) should be decoupled

th the capacitor valwi

The RF input is internally acbias. The IF outputs are open required from thes ts to VCC.

A peak-to-peak d tial swing on RF of V (0.353 V rms fo su w

r a sine wave input) re lts in an IF output po er of 4.7 dBm.

Th y fo fro

e reference frequenc r the PLL should be m 12 MHz to

16 ap in,

0 MHz and should be plied to the REF_IN p which should

VCC1

RED

R55 OPEN (0402)

S1

PEN

R56

0Ω

(0402)

LO IN/OUT

TC1-1-13+

REF_IN

49.9Ω (0402)

REFOUT

ues shown in Figure 46.

e outpu

ifferen

4

3

51

T8

C31 1nF

(0402)

R70

R16

0Ω

(0402)

LODRV_EN

C5 1nF

(0402)

C6 1nF

(0402)

MUXOUT

LON

LOP

REF_IN

36

37

38

6

8

coupled and needs no external

collector, and a bias inductor is

1

IN

VCC RED

+5V

C7

C25

C23

0.1µF

(0402)

R6

R26

0Ω (0402)

C8 100pF (0402)

27

34 22 17 10 1

ADRF6604

×2

MUX

÷2

÷4

R25

0Ω

(0402)

(0402) C24 100pF (0402)

VCC_MIXVCC_V2IVCC_LO

FRACTION

TEMP

SENSOR

1174 2015 2321 2524 3028 3531

VCC_LO VCC2 VCC1

MODULUS

REG

THIRD-O RDER

FRACTIO NAL

INTERPO LATOR

(ORANG E)

Figure 46. Basic Connections for Operation of the ADRF6604

0.1µF (0402)

C22 100pF (0402)

N COUNTER

–

PHASE

+

FREQUENCY

DETECTOR

CP

TEST

POINT

C20

0.1µF (0402)

R24 0Ω (0402)

C21 100pF (0402)

INTEGER

REG

21 TO 123

R38 0Ω

(0402)

C14

22pF

(0603)

C43

10µF

(0603)

S2

C19

0.1µF (0402)

R17 0Ω (0402)

C18 100pF (0402)

PRESCALER

CHARGE PUMP 250µA, 500µA (DEFAULT), 750µA, 1000µA

R

SET

R2

OPEN

R37

(0402)

0Ω

(0402)

R9 10kΩ

(0402)

R10 3kΩ (0603)

C15

2.7nF (1206)

R11 OPEN (0402)

C2

OPEN

(0402)

be ac-coupled and terminated with a 50 Ω resistor as shown in Figure 46. The reference signal, or a divided-down version of the reference signal, can be brought back off chip at the multiplexer output pin (MUXOUT). A lock detect signal and a voltage

ortional to the ambient tempprop

o

n the multiplexer output pin.

erature can also be selected

The loop filter is connected between the CP and VTUNE pins. When connected in this way, the internal VCO is operational. For information about the loop filter components, see the Eval ons section

uation Board Configuration Opti .

Operation wit xternal VCO is a ssible the loop filter comp ld be referr nd. The output of the loop f ected to the i age pin of the external VCO. T of the VCO i ack into the device on the LO N pins, using f necessary.

h an e lso po . In this case,

onents shou ed to grou

ilter is conn nput volt

he output s brought b

P and LO a balun i

P1

89

R57 0Ω (0402)

CLK

DATA

13 12

SPI

INTERFACE

1840393

VCC

+5V

9-PIN DSUB

R36 0Ω (0402)

C34

R52

OPEN

(0402)

C33

R51

OPEN

(0402)

C32

R50

OPEN

(0402)

LE

14

DECL2P5

9

C16 100pF (0402)

DECL3P3

2

C12 100pF (0402)

RF

IN

26

R28

0Ω

(0402)

IP3SET

29

195

IFNIFP

R59

0Ω

(0402)

C29

0.1µF (0402)

R27

0Ω

(0402)

14

2

5

3

R18

0Ω

(0402)

R8 0Ω

(0402)

R43

0Ω

(0402)

RFIN

C27

0.1µF (0402)

C17

0.1µF (0402)

C11

0.1µF (0402)

RFOUT

VCC

÷2

(0402)

R54 10kΩ (0402)

R7 0Ω (0402)

BUFFER

R65 10kΩ

(0402)

C13

6.8pF (0603)

R1

0Ω

C1 100pF (0402)

R53

10kΩ

(0402)

C9

0.1µF (0402)

C10 100pF (0402)

BUFFER

R20

0Ω

(0402)

C40 22pF (0603)

R12 0Ω (0402)

2 4 61357

R19

0Ω

(0402)

DIVIDER

÷2

DIV

2:1

BY

MUX

2, 1

VCO

CORE

VTUNE

CP

R62 0Ω (0402)

R35 0Ω (0402)

DECLVCO

R63 OPEN (0402)

R30 0Ω (0402)

PLL_EN

16

VTUNE

C42 10µF (0603)

C41 OPEN (0603)

8553-024

Rev. A | Page 22 of 32

ADRF6604

A

AC TEST FIXTURE

Characterization data for the ADRF6604 was taken u

nder very strict test conditions. All possible techniques were used to achieve optimum accuracy and to remove degrading effects of

RF1 AGILENT N5181A

HP 11636A

POWER DIVI DER

RF2 AGILENT N5181A

REF_IN AGILENT N5181A

REF_IN

IF_OUT

DRF6604 CH LL INSTRUM

A

OMPUTER V AISY

C

AINED TO

CH EACH INDIVIDUAL INSTRUMENT.

the signal generation and measurement equipment. Figure 47 shows the typical AC test setup used in the characterization of the ADRF6604.

ARACTERIZATION RACK DIAGRAM. ENTS ARE CONTROLLED BY A LAB

IA A USB TO GPIB CONTROLLER, D

RF

IN

ADRF6604

EVALUATION BOARD

ROHDE & SCHWARZ

FSEA30

10-PIN DC HEADER

AGILENT 34401A SET TO IDC

(SET FOR SUPPLY CURRENT)

5V dc VIA

10-PIN DC HEADER

AGILENT 34980A WITH THREE 34921 MODUL ES

AND ONE 34950 MODULE

5V dc MEASURED FOR SUPPLY CURRENT

9-PIN CONTRO LLER D-SUB AND

GND VIA 10-PIN DC HEADER

3.3V dc VI A 10-PIN DC HEADER

AGILENT E3631A 25V SET TO

3.3V, 6V SET TO 5V. RETURNS ARE

JUMPERED TOGETHER

08553-027

Figure 47. ADRF6604 AC Test Setup

Rev. A | Page 23 of 32

ADRF6604

EVALUATION BOAR

Figure 50 shows the schematic of the RoHS-compliant evaluation board for the ADRF6604. This board has four layers and w designed using Rogers 4350 hybrid material to minimize high

equency losses. FR4 material is also adequate if the design can

accept the slightly higher trace loss of this material.

The evaluation board is designed to operate using the internal VCO of the device (the default configuration) or using an external VCO. To use an external VCO, R62 and R12 should be removed. Place 0 Ω resistors in R63 and R11. The input of the external VCO should be connected to the VTUNE SMA connector, and the external VCO output should be connected to the LO IN/OUT SMA connector. In addition to these hardware changes, internal register settings must be changed to enable operation with an external VCO (see the Register 6—VCO Control and VCO Enable (Default: 0x1E2106) section).

Additional configuration options for the evaluation board are described in Ta bl e 10 .

D

as

EVALUATION BOARD CONTROL SOFTWARE

Software to program the ADRF6604 is available for download from the ADRF6604 product page under the Evaluation Boards & Kits section. To install the software

1. Download and extract the zip file:

ADRF6x0x_customer_6p0p0_install.zip file.

2. Follow the instructions in the read me file.

The evaluation board can be connected to the PC using a PC parallel port or a USB port. These options are selectable from the opening menu of the software interface (see Figure 48). The evaluation board is shipped with a 25-pin parallel port cable for connection to the PC parallel port.

To connect the evaluation board to a USB port, a USB adapter board (frEVAL-ADF4XXXZ-USB) must be purchased from Analog Devices This board conne a USB mini-connector at one end. An additional 25-pin male to 9-pin female adapter is required to mate the EVAL-ADF4XXXZUSB board to the 9-pin D-Sub connector on the ADRF6604 evaluation board.

Figure 49 shows the main window of the control software with the default settings displayed.

cts to the PC using a standard USB cable with

Figure 48. Control Software Opening Menu

.

08553-028

Rev. A | Page 24 of 32

ADRF6604

08553-029

Figure 49. Main Window of the ADRF6604 Evaluation Board Software

Rev. A | Page 25 of 32

ADRF6604

C

SCHEMATIC AND ARTWORK

V

T7

GND2

GND1

GND

VCC

1

VCC_BB

VCC_LO

VCC_RF

11A22A3

P1-T7

AGND

9J1

1

10J1

5J1

6J1

7J1

8J1

1

AGND

VCO_LDO

2P5V_LDO

3P3V_LDO

VCC_SENSE

LO_EXTERN

1J1

2J1

3J1

4J1

AGND

OUT

VCC

AGND

0

R43

461

T3

TC4-1W

3

2

VCC_SENSE

0

SNS1

SNS

C28

AGND

0

R32

0

R31

0

R29

AGNDAGND

6A

10UF

LO

AGND

VCC_LO

0

R69

AGND

P4-T7

44A55A6

T8

3A

1

C7

VCC_LO

P1-T7

4

2

NC

0

R6

C8

153

P3-T7

P1-T7

LO_EXTERN

P3-T7

P4-T7

R66

0

R67

R68

0DNI

IP3SET

OUTPUT_EN

0.1UF

AGND AGND

100PF

VCC_BB

C27

0.1UF

TBD

R27

R60

TBD

1

IP3SET

AGND

0

R33

1NF

C6 C5

1NF

R56

AGND

10K

2

VCC

1

VCC1

3

10K

R55

AGND

1

S1

VCC_RF

1

VCC_RF

C25

0.1UF

0

R26

C24

100PF

AGND AGND

27

282930

GND

IP3SET

GND

31323334353637383940

NC

VCC_V2I

NC

VCC_LO

GND

LODRV_EN

LON

LOP

VTUNE

DECLVCO

P1-6

0

R63

R72

100K

AGND

VTUNE

0

R62

22PF

C40

10K

R65R9

C13

6.8PF

10K

3K

C15

2.7NF

R10

C14

22PF

0

R37

0

R38

1

CP

0

R12

VCO_LDO

DNI

AGND

R11

100PF

C10

0

R7

0.1UF

C9

1

VCC4

VCC

0PF

C1

10

0

R1

C2

0.1UF

1

R49

VCO_LDO

R8

AGND AGND

1

3P3V1

VCC1

123456789

AGND

10UF

C43

AGND

DNI

C12

100PF

AGND

0

AGND

C11

0.1UF

OSC_3P3V

C41

10UF

AGND

DECL3P3CPGND

0

R15

1

C4

OSC_3P3V

R59

0

VCC

R44

AGND

C29

0.1UF

AGND

RFIN

0

R28

AGND

VCC_BB

1

C23

VCC_BB1

0.1UF

0

R25

AGND AGND

C22

100PF

DNI

IFP

AGND

R47

C35

DNI

L1

TBD

VCC

IFN

AGND

0

R48

C36

DNI

L2

TBD

VCC

DNI

R58

VCC_LO

26

IN

GND

RF

21

PAD

GND

E-PAD

VCC_MIX

GND

AGND

IFN

AGND

222324

25

IFP

VCC_LO

PLL_EN

Z1

SET

R

REF_IN

GND

MUXOUT

R2

DNI

AGND

GND

LE

CLK

DATA

GND

DECL2P5

VCC2

10

AGND

P1-1

TBD

0

13 14 17 19

R35

11 12 15 16 18 20

R19

C32

100PFDNI

AGND

P1-1

1

R50

1K DNI

P1

123456789

CLK

C16

100PF

0

R18

C17

0.1UF

1

2P5V

10UF

C42

R71

0

R16

2P5V_LDO

AGND

REFOUT

DNI

R14

Y1

10PF

22000PF

C3

C31

1000PF

AGND

R70

49.9

AGND

REFIN

1

VCC_LO1

0

R34

0

R20

1

DATA

0

R57

R30

P1-6

AGNDAGND

C20

0.1UF

0

R24

C21

100PF

OUTPUT_EN

R54

3

1

2

S2

AGND

100PFDNI

C33

1

0

R51

DIG_GND

R36

1K DNI

VCC

AGND

R53

10K 10K

C34

100PFDNI

AGND

R52

1K DNI

AMP745781-4

AGND

100PF

C18

AGND

0

R17

0.1UF

C19

1

VCC2

AGND

VCC

08553-023

1

VCC5

1

LE

AGND

3P3V_LDO

Figure 50. Evaluation Board Schematic

Rev. A | Page 26 of 32

ADRF6604

08553-013

Figure 51. Evaluation Board Layout (Bottom)

Figure 52. Evaluation Board Layout (Top)

08553-012

Rev. A | Page 27 of 32

ADRF6604

EVALUATION BOARD CONFIGURATION OPTIONS

Table 10.

Default Condition/

Component Description

S1, R55, R56, R33

LO IN/OUT SMA Connector

REFIN SMA Connector

REFOUT SMA Connector

CP Test Point

R37, C14, R9, R10, C15, C13, R65, C40

R11, R12

RS62, R63, VTUNE

MA Connector

R2 R RFIN SMA Connector

T3

LO select. Switch and resistors to ground the LODRV_EN pin. The LODRV_EN pin setting, in combination with internal register settings, determines whether the LOP and LON pins function as inputs or outputs (see the LO Selection Logic section for more information).

LO input/output. An external 1× LO or 2× LO can be applied to this single-ended input connector.

Reference input. The input reference frequency for the PLL is applied to this connector. Input impedance is 50 Ω.

Multiplexer output. The REFOUT connector connects directly to the MUXOUT pin. The on-board multiplexer can be programmed to bring out the following signals: REFIN, 2× REFIN, REFIN/2, and REFIN/4; temperature sensor output voltage; and lock detect indicator.

Charge pump test point. The unfiltered charge pump signal can be probed at this test point. Note that the CP pin should not be probed during critical measurements, such as phase noise.

Loop filter. Loop filter components.

Loop filter return. When the internal VCO is used, the loop filter components should be

VCO is used, the loop filter com resistor in R11.

Internal vs. external VCO. When the internal VCO is enabled, the loop filter components are connected directly to the VTUNE pin (Pin 39) by installing a 0 Ω resistor in R62. To use an external VCO, R62 should be left open. A 0 Ω resistor should be installed in R63, and the voltage input of the VCO should be connected to the VTUNE SMA connector. The output of the VCO is brought back into the PLL via the LO IN/OUT SMA connector.

pin. This pin is unused and should be left open. R2 = open (0402)

SET

RF input. The RF input signal should be applied to the RFIN SMA connector. The RF input of the ADRF6604 is ac-coupled; therefore, no bias is necessary.

IF output. The differential IF output signals from the ADRF6604 (IFP and IFN) are converted to a single-ended signal by T3.

(Pin 40) by installing a 0 Ω resistor in

ponents can be returned to ground b

R12. When an external

y installing a 0 Ω

Option Settings

S1 = R55 = open (not installed), R56 = R33 = 0 Ω, LODRV_EN = 0 V

LO input

Lock detect

R12 = 0 Ω (0402),

R11 = op

R62 = 0 Ω (0402), R63 = open (0402)

R3 = R23 = open (0402)

en (0402) returned to the DECLVCO pin

Rev. A | Page 28 of 32

ADRF6604

OUTLINE DIMENSIONS

PIN 1

INDICATOR

1.00

0.85

0.80

12° MAX

SEATING PLANE

6.00

BSC SQ

TOP

VIEW

5.75

BSC SQ

0.80 MAX

0.65 TYP

0.30

0.23

0.18

COMPLIANT TO

0.20 REF

0.60 MAX

0.50

BSC

0.50

0.40

0.30

0.05 MAX

0.02 NOM

COPLANARITY

0.08

JEDEC STANDARDS MO-220-VJJD-2

0.60 MAX

4031

30

EXPOSED

(BOTTOM VIEW)

21

20

1

PAD

10

11

4.50 REF

FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONF IGURATIO N AND FUNCTION DES CRIPTIONS SECTION O F THIS DAT A SHEET.

PIN 1 INDICATOR

4.25

4.10 SQ

3.95

0.25 MIN

Figure 53. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

6 mm × 6 mm Body, Very Thin Quad

(CP-40-1)

Dimensions shown in millimeters

ORDERING GU

Model1

IDE

Temperature Range Package Description Package Option

ADRF6604ACPZ-R7 CP-40-1 −40°C to +85°C 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] ADRF6604-EVALZ Evaluation Board

1

Z = RoHS Compliant Part .

072108-A

Rev. A | Page 29 of 32

ADRF6604

NOTES

Rev. A | Page 30 of 32

ADRF6604

NOTES

Rev. A | Page 31 of 32

ADRF6604

NOTES

Rev. A | Page 32 of 32

Datasheet ADRF6604 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

RF SPECIFICATIONS

TIMING CHARACTERISTICS

Timing Diagram

ESD CAUTION

IF FREQUENCY SWEEP

SPURIOUS PERFORMANCE

REGISTER STRUCTURE

REGISTER 1—MODULUS DIVIDE CONTROL (DEFAULT: 0x003001)

REGISTER 3—Σ-Δ MODULATOR DITHER CONTROL (DEFAULT: 0x10000B)

REGISTER 5—PLL ENABLE AND LO PATH CONTROL (DEFAULT: 0x0000E5)

REGISTER 6—VCO CONTROL AND VCO ENABLE (DEFAULT: 0x1E2106)

REGISTER 7—MIXER BIAS ENABLE AND EXTERNAL VCO ENABLE (DEFAULT: 0x000007)

THEORY OF OPERATION

PROGRAMMING THE ADRF6604

INITIALIZATION SEQUENCE

LO SELECTION LOGIC

BASIC CONNECTIONS FOR OPERATION

AC TEST FIXTURE

EVALUATION BOARD CONTROL SOFTWARE

SCHEMATIC AND ARTWORK

EVALUATION BOARD CONFIGURATION OPTIONS

OUTLINE DIMENSIONS