ANALOG DEVICES ADRF6604 Service Manual

2500 MHz to 2900 MHz Rx Mixer with

V

Integrated Fractional-N PLL and VCO

FEATURES

Rx mixer with integrated fractional-N PLL RF input frequency range: 1200 MHz to 3600 MHz Internal LO frequency range: 2500 MHz to 2900 MHz Input P1dB: 14.5 dBm Input IP3: 27.5 dBm IIP3 optimization via external pin SSB noise figure

IP3SET pin open: 14.3 dB

IP3SET pin at 3.3 V: 15.5 dB Voltage conversion gain: 6.8 dB Matched 200 Ω IF output impedance IF 3 dB bandwidth: 500 MHz Programmable via 3-wire SPI interface 40-lead, 6 mm × 6 mm LFCSP

APPLICATIONS

Cellular base stations

GENERAL DESCRIPTION

The ADRF6604 is a high dynamic range active mixer with integrated phase-locked loop (PLL) and voltage controlled oscillator (VCO). The PLL/synthesizer uses a fractional-N PLL to generate a f can be divided or multiplied and then applied to the PLL phase frequency detector (PFD).

LODRV_EN

MUXOUT

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

input to the mixer. The reference input

LO

CC1

CC2VCC_LOVCC_MIXVCC_V2IVCC_LO

36

LON

37

38

LOP

16

PLL_EN

DATA

CLK

REF_IN

12

13

14

LE

6

8

SPI

INTERFACE

×2

MUX

÷2

÷4

FRACTION

TEMP

SENSOR

7 11 15 20 21 23 24 25 28 30 31 35

FUNCTIONAL BLOCK DIAGRAM

PHASE

INTEGER

N COUNTER

21 TO 123

MODULUS

REG

THIRD-ORDER

FRACTIONAL

INTERP OLAT OR

– +

FREQUENCY

DETECTOR

GND

REG

Figure 1.

ADRF6604

The PLL can support input reference frequencies from 12 MHz to 160 MHz. The PFD output controls a charge pump whose output drives an off-chip loop filter.

The loop filter output is then applied to an integrated VCO. The VCO output at 2 × f programmable PLL divider. The programmable PLL divider is controlled by a sigma-delta (Σ-) modulator (SDM). The modulus of the SDM can be programmed from 1 to 2047.

The active mixer converts the single-ended, 50  RF input to a differential, 200 Ω IF output. The IF output can operate up to 500 MHz.

The ADRF6604 is fabricated using an advanced silicon-germanium BiCMOS process. It is available in a 40-lead, RoHS-compliant, 6 mm × 6 mm LFCSP with an exposed paddle. Performance is specified over the −40°C to +85°C temperature range.

Table 1.

Internal LO

Part No.

Range

ADRF6601 750 MHz 300 MHz 450 MHz

1160 MHz 2500 MHz 1600 MHz

ADRF6602 1550 MHz 1000 MHz 1350 MHz

2150 MHz 3100 MHz 2750 MHz

ADRF6603 2100 MHz 1100 MHz 1450 MHz

2600 MHz 3200 MHz 2850 MHz

ADRF6604 2500 MHz 1200 MHz 1600 MHz

2900 MHz 3600 MHz 3200 MHz

2717101 22

34

BUFFER

PRESCALER

÷2

CHARGE PUMP 250µA, 500µA (DEFAULT), 750µA, 1000µA

54

R

SET

is applied to an LO divider, as well as to a

LO

±3 dB RF Balun Range

ADRF6604

INTERNAL LO RANGE 2500MHz TO 2900MHz

DIV

2:1

BY

MUX

2, 1

VCO

CORE

3

CP VTUNE

IFP

191839

IFN

NC

32 33

NC

3.3V LDO

2.5V LDO

VCO LDO

IN

40

26

29

2

DECL3P3

9

DECL2P5

DECLVCO

RF

IP3SET

±1 dB RFIN Balun Range

IN

8553-001

ADRF6604

REVISION HISTORY

5/11—Rev. 0 to Rev. A

Changes to Features and General Description Sections.............. 1

Changes to Table 2............................................................................ 3

Changes to Synthesizer Specifications Parameter and to Phase

Noise Parameter, Table 3 ............................................................. 4

Changes to Power Supplies Parameter, Table 4 ............................ 4

Replaced Typical Performance Characteristics Section;

Renumbered Sequentially ........................................................... 9

Added Spurious Performance Section......................................... 15

Change to Figure 41 ....................................................................... 17

Changes to Figure 42...................................................................... 18

Changes to Theory of Operation Section.................................... 20

Changes to Figure 46...................................................................... 22

Added AC Test Fixture Section and Figure 47 ........................... 23

Changes to Evaluation Board Control Software Section and

Figure 48 ...................................................................................... 24

Changes to Figure 49...................................................................... 25

6/10—Revision 0: Initial Version

Rev. A | Page 2 of 32

ADRF6604

SPECIFICATIONS

RF SPECIFICATIONS

VS = 5 V, ambient temperature (TA) = 25°C, f

= 153.6 MHz, f

REF

using CDAC = 0xC and IP3SET = 3.3 V, unless otherwise noted.

Table 2.

Parameter Test Conditions/Commen Min Typ Max Unit

INTERNAL LO FREQUENCY RANGE 2500 2900 MHz RF INPUT FREQUENCY RANGE ±3 dB RF input range 1200 3600 MHz RF INPUT AT 2360 MHz

Input Return Loss Relative to 50 Ω (can be improved with external match) −16.2 dB Input P1dB 14.6 dBm Second-Order Intercept (IIP2) −5 dBm each tone (10 MHz spacing between tones) 54.5 dBm Third-Order Intercept (IIP3) −5 dBm each tone (10 MHz spacing between tones) 28 dBm Single-Sideband Noise Figure IP3SET = 3.3 V 14.8 dB

IP3SET = open 13.9 dB

LO-to-IF Leakage At 1× LO frequency, 50 Ω termination at the RF port −43 dBm

RF INPUT AT 2560 MHz

Input Return Loss Relative to 50 Ω (can be improved with external match) −21 dB Input P1dB 14.5 dBm Second-Order Intercept (IIP2) −5 dBm each tone (10 MHz spacing between tones) 58.2 dBm Third-Order Intercept (IIP3) −5 dBm each tone (10 MHz spacing between tones) 27.6 dBm Single-Sideband Noise Figure IP3SET = 3.3 V 14.9 dB

IP3SET = open 14.2 dB

LO-to-IF Leakage At 1× LO frequency, 50 Ω termination at the RF port −42 dBm

RF INPUT AT 2760 MHz

Input Return Loss Relative to 50 Ω (can be improved with external match) −20 dB Input P1dB 14.4 dBm Second-Order Intercept (IIP2) −5 dBm each tone (10 MHz spacing between tones) 64.4 dBm Third-Order Intercept (IIP3) −5 dBm each tone (10 MHz spacing between tones) 27 dBm Single-Sideband Noise Figure IP3SET = 3.3 V 15.5 dB

IP3SET = open 14.6 dB

LO-to-IF Leakage At 1× LO frequency, 50 Ω termination at the RF port −44 dBm

IF OUTPUT

Voltage Conversion Gain Differential 200 Ω load 6.8 dB IF Bandwidth Small signal 3 dB bandwidth 500 MHz Output Common-Mode Voltage External pull-up balun or inductors required 5 V Gain Flatness Over frequency range, any 5 MHz/50 MHz 0.2/0.5 dB Gain Variation Over full temperature range 1.3 dB Output Swing Differential 200 Ω load 2 V p-p Output Return Loss Relative to 200 Ω −15 dB

LO INPUT/OUTPUT (LOP, LON) Externally applied 1× LO input, inte al PLL disabled rn

Frequency Range 250 6000 MHz Output Level (LO as Output) 1× LO into a 50 Ω load, LO output buffer enabled −9 dBm Input Level (LO as Input) −6 0 +6 dBm Input Impedance 50 Ω

= 38.4 MH

PFD

ts

z, high-side LO injection, f = 140 MHz, IIP3 optimized

IF

Rev. A | Page 3 of 32

ADRF6604

SYNTHESIZER/PLL SPE

= 140 MHz, IIP3 optimi

f

IF

Table 3.

Parameter Test Conditions/Comments Min Typ Max Unit

SYNTHESIZER SPECIFICATIONS Synthesizer specifications referenced to 1× LO

Frequency Range 2500 2900 MHInternally generated LO z

Figure of Merit1 P

Reference Spurs f f

−82 dBc f >f PH ASE NOISE fLO = 2500 MHz to 2900 MHz, f

1 kHz to 10 kHz offset −87.7 dBc/Hz

100 kHz offset −96 dBc/Hz

−117 dBc500 kHz offset /Hz

1 MHz offset −126 dBc/Hz

5 MHz offset −142 dBc/Hz

10 MHz offset −148 dBc/Hz

20 MHz offset −150 dBc/Hz

Integrated Phase Noise 1 kHz to 40 MHz integration bandwidth 0.69

PFD Frequency 20 40 MHz RE T pins FERENCE CHARACTERISTICS REF_IN, MUXOU

REF_IN Input Frequency 12 160 MH z

REF_IN Input Capacitance 4 pF

MUXOUT Output Level

V

MUXOUT Duty Cycle 50 % CH ARGE PUMP

Pump Current Programmable to 250 μA, 500 μA, 750 μA, 1 mA 500 μA

Output Compliance Range 1 2.8 V

1

T ) is computed as pha as m sured across LO ran with f

he figure of merit (FOM

a

nd f power = 10 dBm

REF

CIFICATIONS

e (TA) = 25°C, f

turVS = 5 V, ambient tempera

zed using CDAC = 0xC and IP3SET = 3.3 V, unless otherwise noted.

(500 V/μs slew rate) w

se noise (dBc/Hz) – 10 log 10(f

= 153.6 MHz, f

REF

= 0 dBm −221.4 dBc/Hz/Hz

REF_IN

= 38.4 MHz

PFD

/4 −107 dBc

PFD

−80 dBc

PFD

(lock detect output selected) 0.25 V V

OL

(lock detect output selected) 2.7 V

OH

ith a 40 MHz f

. The FOM was computed at 50 kHz offset.

PFD

power = 4 dBm, f

REF

= 38.4 MHz

PFD

) – 20 log 10(fLO/f

PFD

). The FOM w

PFD

= 38.4 MHz, high-side LO injection,

PFD

ea the full ge, 0 MHz,

°rms

= 8

REF

LOGIC INPU ER SPECIFIC

V = 2 -side LO injection, fIF = 140 MHz, IIP3 optimize

= 5 V, ambient temperature (TA) 5°C, f

S

us xC and IP3SET = 3.3

ing CDAC = 0 V, unless otherwise noted.

T

able 4.

Pa Test Cond T p Max Unit

rameter itions/Comments Min y

T AND POW ATIONS

= 153.6 MHz, f

REF

= 38.4 MHz, high d

PFD

LOGIC INPUTS CLK, DATA , LE

Input High Voltage, V

Input Low Voltage, V

Input Current, I

Input Capacitance, C

1.4 3.3 V

INH

0 0.7 V

INL

0.1 μA

INH/IINL

IN

5 pF

POWER SUPPLIES VCC1, VCC2, VCC_LO, VCC_MIX, and VCC_V2I pins

Voltage Range 4.75 5 5.25 V

Supply Current PLL only 96 mA External LO mode (internal PLL disabled, IP3SET pin = 3.3 V, LO output buffer off) 164 mA Internal LO mode (internal PLL enabled, IP3SET pin = 3.3 V, LO output buffer on) 274 mA Internal LO mode (internal PLL enabled, IP3SET pin = 3.3 V, LO output buffer off) 260 mA Power-down mode 30 mA

Rev. A | Page 4 of 32

ADRF6604

TIMING CHARACTERISTICS

VCC2 = 5 V ± 5%.

Table 5.

Paramete

t1 20 e ns min LE setup tim t2 10 ns min DATA-to-CLK setup time t3 -CLK hold time 10 ns min DATA-to t4 25 CLK high duration ns min t5 CLK low duration 25 ns min t6 10 CLK-to-LE setup time ns min t7 20 in LE pulse width ns m

Timing Diagram

r Limit Unit Description

CLK

t

4

t

5

DATA

t

2

DB23 (MSB)

t

1

LE

DB22

t

3

DB2 DB1

(CONTROL BIT C(CONTROL BIT C3)

2)

(CO BIT C1)

DB0 (L

NTROL

SB)

t

7

6

08553-002

Figure 2. Timing Diagram

Rev. A | Page 5 of 32

ADRF6604

ABSOLUTE MAXIMUM R

Table 6.

Paramete

Supply Voltage, VC 2, VCC_LO,

Digital I/O, CLK, DA E, LODRV_EN,

VTUNE 3.3 V 0 V to IFP, IFN to VCC_V2I −0.3 V + 0.3 V RFIN 16 dBm LOP, LON, REF_IN 13 dBm θJA (Exposed Paddle Soldered Down) 35°C/W Maximum Junction Temperature 150°C Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C

r Rating

C1, VCC

VCC_MIX, VCC_V

PLL_EN

2I

TA, L

ATINGS

V to +5.5 V

−0.5

to +3.6 V

−0.3 V

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section o maximu de

f this specification is not implied. Exposure to absolute

m rating conditions for extended periods may affect

vice reliability.

ESD CAUTION

Rev. A | Page 6 of 32

ADRF6604

TION DESCRIPTIONS PIN CONFIGURATION AND FUNC

NC

VCC_LO

GND

LODRV_EN

LON

LOP

VTUNE

DECLVCO

38

39

40

PIN 1

11

VCC

GND

R

SET

RE

F_IN GND

XOUT

MU

2P5

DECL

VCC2

NOTES

1. NC = NO CONNECT . DO NOT CONNECT TO T HIS PIN.

2. THE EXPOSED PADDLE SHOULD BE SOLDERED TO A LOW IMPEDANCE GROUND PL AN

INDICATO R

2DECL3P3 3CP 4

ADRF6604

5 6 7 8 9

10

TOP VIEW

(Not to Scale)

11

12

13

ND

CLK

G

DATA

Figure 3. Pin Configuration

NC

GND

32

31

33

34

35

36

37

30 GND 29 IP3SET 28 GND 27 VCC_V2I

RF

26

IN

25

GND 24 GND 23 GND 22 VCC_MIX 21

GND

15

17

16

18

19

14

LE

20

O

IFP

IFN

GND

PLL_EN

VCC_L

E.

8553-003

Table 7. Pin Function Descriptions

Pin No. Mnemonic Description

1 VCC1

Power Supply for the 3.3 V LDO. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin

should be decoupled with a 100 pF capacitor and a 0.1 μF capacitor located close to the pin. 2 DECL3P3 Decoupling Node for 3.3 V LDO. Connect a 0.1 μF capacitor between this pin and ground. 3 CP Charge Pump Output Pin. Connect to VTUNE through the loop filter. 4, 7, 11, 15, 20,

GND Ground. Connect these pins to a low impedance ground plane. 21, 23, 24, 25, 28, 30, 31, 35

5 R

SET

Charge Pump Current. The nominal charge pump current can be set to 250 μA, 500 μA, 750 μA, or 1 mA using Bit DB11 and Bit DB10 in Register 4 and by setting Bit DB18 in Register 4 to 0 (internal reference current). In this mode, no external R

is required. If Bit DB18 is set to 1, the four nominal charge pump currents (I

SET

can be externally adjusted according to the following equation:

4.217

I

×

R

=

SET

6 REF_IN

Reference Input. Nominal input level is 1 V p-p. Input range is 12 MHz to 160 MHz. This pin is internally dc-

⎛ ⎜ ⎜ ⎝

I

NOMINAL

⎞

CP

⎟ ⎟ ⎠

37.8

−

biased and should be ac-coupled.

8 MUXOUT

Multiplexer Output. This output can be programmed to provide the reference output signal or the lock detect

signal. The output is selected by programming the appropriate register. 9 DECL2P5 Decoupling Node for 2.5 V LDO. Connect a 0.1 μF capacitor between this pin and ground. 10 VCC2

Power Supply for the 2.5 V LDO. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin

should be decoupled with a 100 pF capacitor and a 0.1 μF capacitor located close to the pin. 12 DATA Serial Data Input. The serial data input is loaded MSB first; the three LSBs are the control bits. 13 CLK

Serial Clock Input. The serial clock input is used to clock in the serial data to the registers. The data is latched

into the 24-bit shift register on the CLK rising edge. The maximum clock frequency is 20 MHz. 14 LE

Load Enable. When the LE input pin goes high, the data stored in the shift register is loaded into one of the

eight registers. The relevant latch is selected by the three control bits of the 24-bit word. 16 PLL_EN

PLL Enable. Switch between internal PLL and external LO input. When this pin is logic high, the mixer LO is

automatically switched to the internal PLL and the internal PLL is powered up. When this pin is logic low, the

internal PLL is powered down and the external LO input is routed to the mixer LO inputs. The SPI can also be

used to switch modes. 17, 34 VCC_LO

Power Supply. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin should be decoupled

with a 100 pF capacitor and a 0.1 μF capacitor located close to the pin. 18, 19 IFP, IFN Mixer IF Outputs. These outputs should be pulled to VCC_MIX with RF chokes.

NOMINAL

)

Rev. A | Page 7 of 32

ADRF6604

Pin No. Mnemonic Description

22 VCC_MIX

26 RFIN RF Input. Single-ended, 50 Ω. 27 VCC_V2I

29 IP3SET Connect a resistor from this pin to a 5 V supply to adjust IIP3. Normally leave open. 32, 33 NC NC = No Connect. Do not connect to this pin. 36 LODRV_EN

37, 38 LON, LOP

39 VTUNE

40 DECLVCO Decoupling Node for VCO LDO. Connect a 100 pF capacitor and a 10 μF capacitor between this pin and ground. EPAD Exposed Paddle. The exposed paddle should be soldered to a low impedance ground plane.

Power Supply. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin should be decoupled with a 100 pF capacitor and a 0.1 μF capacitor located close to the pin.

LO Driver Enable. Together with Pin 16 (PLL_EN), this digital input pin determines whether the LOP and LON pins operate as inputs or outputs. LOP and LON become inputs if the PLL_EN pin is low or if the PLL_EN pin is set high with the PLEN bit (DB6 in Register 5) set to 0. LOP and LON become outputs if either the LODRV_EN pin or the LDRV bit (DB3 in Register 5) is set to 1 while the PLL_EN pin is set high. The external LO drive frequency must be 1× LO. This pin has an internal 100 kΩ pull-down resistor.

Local Oscillator Input/Output. The internally generated 1× LO is available on these pins. When internal LO generation is disabled, an external 1× LO can be applied to these pins.

VCO Control Voltage Input. This pin is driven by the output of the loop filter. The nominal input voltage range on this pin is 1.5 V to 2.5 V.

Rev. A | Page 8 of 32

ADRF6604

TYPIC ERFORM

RF FREQUE

CDA terna ted high-side LO, RFIN = −5 d

AL P ANCE CHARACTERISTICS

NCY SWEEP

C = 0xC, in lly genera Bm, fIF = 140 MHz, unless otherwise noted.

5

IP3SET = OPEN

4

IP3SET = 3.3V

3

2

1

0

GAIN (dB)

–1

–2

–3

–4

–5

2360 2410 2510

2460 2560 2610 2660 2710 2760

RF FREQUENCY ( MHz)

TA = +85°C T

= +25°C

A

T

= –40°C

A

Figure 4. Gain vs. RF Frequency

90

IP3SET = OPEN IP3SET = 3.3V

80

70

60

INPUT IP2 (dBm)

50

40

30

2360 2410 2460 2510 2560 2610 2660 2710 2760

RF FREQUENCY (M Hz)

TA = +85°C T

= +25°C

A

T

= –40°C

A

Figure 5. Input IP2 vs. RF Frequency

553-104 08

08553-105

35

IP3SET = OPEN

34

IP3SET = 3.3V

33

32

31

30

29

28

27

UT IP3 (dBm)

26

INP

25

24

23

22

21 20

2360 2410 2460 2510 2560 2610 2660

Figure 7. Input IP3 vs. RF Frequency

18

IP3SET = OPEN

17

IP3SET = 3.3V

16

15

14

13

12

INPUT P1dB (dBm)

11

10

9

8

2360 2410 2460 2510 2560 2610 2660 2710 2760

Figure 8. Input P1dB vs. RF Frequency

RF FREQUENCY ( MHz)

TA = +85°C T

= +25°C

A

T

= –40°C

A

2710 2760

TA = +85°C T

= +25°C

A

T

= –40°C

A

7

08553-10

08553-108

20

18

16

14

12

10

8

NOISE FI GURE (dB)

6

4

IP3SET = OPEN

2

IP3SET = 3.3V

0

2360 2410 2460 2510 2560 2610 2660 2710 2760

RF FREQUENCY ( MHz)

Figure 6. Noise Figure vs. RF Frequency

TA = +85°C T

= +25°C

A

T

= –40°C

A

08553-106

Rev. A | Page 9 of 32

ADRF6604

IF FREQUENCY SWEEP

ted swept low-side LO, f = 2490 MHz, CDAC = 0xC, internally genera

5

IP3SET = OPEN

4

IP3SET = 3.3V

3

2

1

0

GAIN (dB)

–1

–2

–3

–4

–5

25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400

IF FREQUENCY (MHz)

Figure 9. Gain vs. IF Frequency

TA = +85°C T

= +25°C

A

T

= –40°C

A

RF

08553-109

RFIN = −5 dBm, unless otherwise noted.

45

IP3SET = OPEN

40

IP3SET = 3.3V

35

30

25

20

INPUT IP3 (dBm)

15

10

5

25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400

Figure 12. Input IP3 vs. IF Frequency, RF

IF FREQUENCY (MHz)

TA = +85°C T

= +25°C

A

T

= –40°C

A

= −5 dBm

IN

08553-112

90

IP3SET = OPEN IP3SET = 3.3V

80

70

60

INPUT IP2 (dBm)

50

40

30

25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400

IF FREQUENCY (MHz)

Figure 10. Input IP2 vs. IF Frequency, RF

20

18

16

14

12

10

8

NOISE FI GURE (dB)

6

4

IP3SET = OPEN

2

IP3SET = 3.3V

0

25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400

IF FREQUENCY (MHz)

TA = +85°C T

= +25°C

A

T

= –40°C

A

= −5 dBm

IN

TA = +85°C T

= +25°C

A

T

= –40°C

A

Figure 11. Noise Figure vs. IF Frequency

20

18

16

14

12

10

8

INPUT P1dB (dBm)

6

4

IP3SET = OPEN

2

IP3SET = 3.3V

0

25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400

08553-110

IF FREQUENCY (MHz)

TA = +85°C T

= +25°C

A

T

= –40°C

A

08553-113

Figure 13. Input P1dB vs. IF Frequency

08553-111

Rev. A | Page 10 of 32

ANALOG DEVICES ADRF6604 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

RF SPECIFICATIONS

TIMING CHARACTERISTICS

Timing Diagram

ESD CAUTION

IF FREQUENCY SWEEP