ANALOG DEVICES ADRF6516 Service Manual

31 MHz, Dual Programmable Filters

V

Data Sheet

FEATURES

Matched pair of programmable filters and VGAs Continuous gain control range: 50 dB Digital gain control: 15 dB 6-pole Butterworth filter: 1 MHz to 31 MHz

in 1 MHz steps, 1 dB corner frequency Preamplifier and postamplifier gain steps IMD3: >65 dBc for 1.5 V p-p composite output HD2, HD3: >65 dBc for 1.5 V p-p output Differential input and output Flexible output and input common-mode ranges Optional dc offset compensation loop SPI programmable filter corners and gain steps Power-down feature Single 3.3 V supply operation

APPLICATIONS

Baseband IQ receivers Diversity receivers ADC drivers Point-to-point and point-to-multipoint radio Instrumentation Medical

and Variable Gain Amplifiers

ADRF6516

FUNCTIONAL BLOCK DIAGRAM

INP1 INM1

ENBL

VPSD

COMD

LE

CLK

DATA

SDO

COM

VPS

SPI

COM INP2 INM2 VPS COM OFDS OFS2 V PS

PS

COMVICM OFS1VPS

ADRF6516

Figure 1.

OPP1

OPM1

COM

GAIN

VOCM

COM

OPM2

OPP2

09422-001

GENERAL DESCRIPTION

The ADRF6516 is a matched pair of fully differential, low noise and low distortion programmable filters and variable gain amplifiers (VGAs). Each channel is capable of rejecting large out-of-band interferers while reliably boosting the desired signal, thus reducing the bandwidth and resolution requirements on the analog-to-digital converters (ADCs). The excellent matching between channels and their high spurious-free dynamic range over all gain and bandwidth settings make the ADRF6516 ideal for quadrature-based (IQ) communication systems with dense constellations, multiple carriers, and nearby interferers.

The filters provide a six-pole Butterworth response with 1 dB corner frequencies programmable through the SPI port from 1 MHz to 31 MHz in 1 MHz steps. The preamplifier that precedes the filters offers a SPI-programmable option of either 3 dB or 6 dB of gain. The preamplifier sets a differential input impedance of 1600  and has a common-mode voltage that defaults to VPS/2 but can be driven from 1.1 V to 1.8 V.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

The variable gain amplifiers that follow the filters provide 50 dB of continuous gain control with a slope of 15.5 mV/dB. Their maximum gains can be programmed to various values through the SPI. The output buffers provide a differential output impedance of 30 Ω and are capable of driving 2 V p-p into 1 kΩ loads. The output common-mode voltage defaults to VPS/2, but it can be adjusted down to 700 mV by driving the high impedance VOCM pin. Independent, built-in dc offset compensation loops can be disabled if fully dc-coupled operation is desired. The high-pass corner frequency is defined by external capacitors on the OFS1 and OFS2 pins and the VGA gain.

The ADRF6516 operates from a 3.15 V to 3.45 V supply and consumes a maximum supply current of 360 mA when programmed to the highest bandwidth setting. When disabled, it consumes <9 mA. The ADRF6516 is fabricated in an advanced silicon-germanium BiCMOS process and is available in a 32-lead, exposed paddle LFCSP. Performance is specified over the −40°C to +85°C temperature range.

ADRF6516 Data Sheet

REVISION HISTORY

9/11—Revision A: Initial Version

Maximizing the Dynamic Range.............................................. 19

Key Parameters for Quadrature-Based Receivers .................. 20

Applications Information .............................................................. 21

Basic Connections ...................................................................... 21

Supply Decoupling ..................................................................... 21

Input Signal Path ........................................................................ 21

Output Signal Path ..................................................................... 21

DC Offset Compensation Loop Enabled ................................ 21

Common-Mode Bypassing ....................................................... 21

Serial Port Connections ............................................................. 22

Enable/Disable Function ........................................................... 22

Error Vector Magnitude (EVM) Performance ........................... 22

EVM Test Setup .......................................................................... 22

Effect of Filter Bandwidth on EVM ......................................... 22

Effect of Output Voltage Levels on EVM ................................ 23

Effect of C

Evaluation Board ............................................................................ 24

Evaluation Board Control Software ......................................... 24

Schematics and Artwork ........................................................... 25

Outline Dimensions ....................................................................... 27

Ordering Guide .......................................................................... 27

Value on EVM ..................................................... 23

OFS

Rev. A | Page 2 of 28

Data Sheet ADRF6516

SPECIFICATIONS

VPS = 3.3 V, TA = 25°C, Z

Table 1.

Parameter Test Conditions/Comments Min Typ Max Unit

FREQUENCY RESPONSE

Low-Pass Corner Frequency, fC 6-pole Butterworth filter, 0.5 dB bandwidth 1 31 MHz Step Size 1 MHz Corner Frequency Absolute

Accuracy

Corner Frequency Matching

Pass-Band Ripple 0.5 dB p-p Gain Matching

Group Delay Variation From midband to peak

Corner Frequency = 1 MHz 135 ns Corner Frequency = 31 MHz 11 ns

Group Delay Matching Channel A and Channel B at same gain

Corner Frequency = 1 MHz 5 ns Corner Frequency = 31 MHz 0.2 ns

Stop-Band Rejection

Relative to Pass Band 2 × fC 30 dB 5 × fC 75 dB

INPUT STAGE INP1, INM1, INP2, INM2, VICM pins

Maximum Input Swing At minimum gain, V Differential Input Impedance 1600 Ω Input Common-Mode Range 0.4 V p-p input voltage, HD3 > 65 dBc 1.1 1.65 1.8 V

Input pins left floating VPS/2 V

VICM Output Impedance 7 kΩ

GAIN CONTROL GAIN pin

Voltage Gain Range V Gain Slope 15.5 mV/dB Gain Error V

OUTPUT STAGE OPP1, OPM1, OPP2, OPM2, VOCM pins

Maximum Output Swing At maximum gain, R HD2 > 65 dBc, HD3 > 65 dBc 1.5 V p-p Differential Output Impedance 30 Ω Output DC Offset Inputs shorted, offset loop disabled 35 mV Output Common-Mode Range 0.7 1.65 2.8 V

VOCM pin left floating VPS/2 V

VOCM Input Impedance 23 kΩ

NOISE/DISTORTION

Corner Frequency = 1 MHz

Output Noise Density Gain = 0 dB at fC/2 −141 dBV/√Hz Gain = 20 dB at fC/2 −131 dBV/√Hz Gain = 40 dB at fC/2 −112 dBV/√Hz Second Harmonic, HD2 250 kHz fundamental, 1.5 V p-p output voltage Gain = 5 dB 82 dBc Gain = 40 dB 68 dBc Third Harmonic, HD3 250 kHz fundamental, 1.5 V p-p output voltage Gain = 5 dB 71 dBc Gain = 40 dB 56 dBc

= 1 kΩ, digital gain code = 111, unless otherwise noted.

LOAD

Over operating temperature range ±15 % f

Channel A and Channel B at same gain and bandwidth settings

= 0 V 1 V p-p

GAIN

from 0 V to 1 V −5 +45 dB

GAIN

from 300 mV to 800 mV 0.2 dB

GAIN

= 1 kΩ 2 V p-p

LOAD

C

±0.5 % f

C

±0.1 dB

Rev. A | Page 3 of 28

ADRF6516 Data Sheet

Parameter Test Conditions/Comments Min Typ Max Unit

IMD3

f1 = 500 kHz, f2 = 550 kHz, 1.5 V p-p composite

output voltage Gain = 5 dB 61 dBc Gain = 35 dB 42.5 dBc IMD3 with Input CW Blocker

f1 = 500 kHz, f2 = 550 kHz, 1.5 V p-p composite

output, gain = 5 dB; blocker at 5 MHz, 10 dBc

relative to two-tone composite output voltage

Corner Frequency = 31 MHz

Output Noise Density Midband, gain = 0 dB −143.5 dBV/√Hz Midband, gain = 20 dB −139 dBV/√Hz Midband, gain = 40 dB −125 dBV/√Hz Second Harmonic, HD2 8 MHz fundamental, 1.5 V p-p output voltage Gain = 5 dB 68 dBc Gain = 40 dB 70 dBc Third Harmonic, HD3 8 MHz fundamental, 1.5 V p-p output voltage Gain = 5 dB 55 dBc Gain = 40 dB 75 dBc IMD3

f1 = 14 MHz, f2 = 15 MHz, 1.5 V p-p composite

output voltage Gain = 5 dB 55 dBc Gain = 35 dB 77.5 dBc IMD3 with Input CW Blocker

f1 = 14 MHz, f2 = 15 MHz, 1.5 V p-p composite

output, gain = 5 dB; blocker at 150 MHz, 10 dBc

relative to two-tone composite output voltage

DIGITAL LOGIC LE, CLK, DATA, SDO, OFDS pins

Input High Voltage, V Input Low Voltage, V Input Current, I

INH/IINL

>2 V

INH

<0.8 V

INL

<1 μA

Input Capacitance, CIN 2 pF

SPI TIMING LE, CLK, DATA, SDO pins (see Figure 2 and Figure 3)

f

1/t

SCLK

20 MHz

SCLK

tDH DATA hold time 5 ns tDS DATA setup time 5 ns tLH LE hold time 5 ns tLS LE setup time 5 ns tPW CLK high pulse width 5 ns tD CLK to SDO delay 5 ns

POWER AND ENABLE VPS, VPSD, COM, COMD, ENBL pins

Supply Voltage Range 3.15 3.3 3.45 V Total Supply Current ENBL = 3.3 V Corner frequency = 31 MHz 360 mA Corner frequency = 1 MHz 330 mA Disable Current ENBL = 0 V 9 mA Disable Threshold 1.6 V Enable Response Time Delay following ENBL low-to-high transition 20 μs Disable Response Time Delay following ENBL high-to-low transition 300 ns

40 dBc

55 dBc

Rev. A | Page 4 of 28

Data Sheet ADRF6516

A

TIMING DIAGRAMS

t

CLK

LE

DAT

NOTES

1. THE FI RST DATA BIT DETERMINES WHETHER THE PART IS W RITING T O OR READING FROM THE INTERNAL 8- BIT REGI STER. F OR A WRITE OPERATIO N, THE FI RST BIT SHOULD BE A LO GIC 1. T HE 8-BIT WO RD IS THEN W RITTEN T O THE DATA P IN ON CONSECUT IVE RISI NG EDGES OF THE CLOCK.

t

LS

tDSt

WRITE BIT

DH

B2LSB

t

CLK

DON’T CAREDON’T CAREREAD BIT DON’T CARE DO N’T CARE DON’T CARE DON’T CARE DON'T CARE

CLK

DATA

t

D

t

LS

LE

t

DStDH

t

PW

B3

B4 B5 B6

Figure 2. Write Mode Timing Diagram

t

PW

B7 MSB

MSB - 2

DON’T CAREDON’T CARE

t

LH

9422-003

t

LH

SDO

NOTES

1. THE FI RST DATA BIT DETERMINES W HETHER THE PART IS WRITING TO OR READING F ROM THE I NTERNAL 8-BIT REGIST ER. FOR A READ OPERATION, THE F IRST BIT SHOULD BE A LOGIC 0. T HE 8-BIT W ORD IS THE N REGISTERED AT THE SDO PIN ON CONSECUTIVE FALLING E DGES OF THE CL OCK.

B2LSB

B3

B4 B5

B6

B7 MSB

Figure 3. Read Mode Timing Diagram

09422-004

Rev. A | Page 5 of 28

ADRF6516 Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Supply Voltages, VPS, VPSD 3.45 V ENBL, OFDS, LE, CLK, DATA, SDO VPSD + 0.5 V INP1, INM1, INP2, INM2 VPS + 0.5 V OPP1, OPM1, OPP2, OPM2 VPS + 0.5 V OFS1, OFS2 VPS + 0.5 V GAIN VPS + 0.5 V Internal Power Dissipation 1.25 W θJA (Exposed Pad Soldered to Board) 37.4°C/W Maximum Junction Temperature 150°C Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering 60 sec) 300°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. A | Page 6 of 28

Data Sheet ADRF6516

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

L

M1

COM

ENB

32

VICM

IN

VPS

OFS1

INP1

31

30

VPS

29

28

27

26

25

1VPSD

PIN 1

2COMD

INDICATOR

3LE 4CLK

ADRF6516

5DATA

TOP VIEW

6SDO

(Not to Scal e)

7COM 8VPS

1

9

1

13

10

12

VPS

INP2

COM

INM2

NOTES

1. CONNECT THE EXPOSED PADDLE TO A LOW IMPEDANCE GROUND PAD.

24 OPP1 23 OPM1 22 COM 21 GAIN 20 VOCM 19 COM 18 OPM2 17 OPP2

14

15

16

VPS

OFS2

OFDS

09422-002

Figure 4. Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

1 VPSD Digital Positive Supply Voltage: 3.15 V to 3.45 V. 2 COMD Digital Common. Connect to external circuit common using the lowest possible impedance. 3 LE Latch Enable. SPI programming pin. TTL levels: V 4 CLK SPI Port Clock. TTL levels: V 5 DATA SPI Data Input. TTL levels: V 6 SDO SPI Data Output. TTL levels: V

< 0.8 V, V

LOW

< 0.8 V, V

LOW

HIGH

< 0.8 V, V

HIGH

> 2 V.

HIGH

LOW

> 2 V.

< 0.8 V, V

HIGH

> 2 V.

7, 9, 13, 19, 22, 28 COM Analog Common. Connect to external circuit common using the lowest possible impedance. 8, 12, 16, 25, 29 VPS Analog Positive Supply Voltage: 3.15 V to 3.45 V. 10, 11, 30, 31

INP2, INM2,

Differential Inputs. 1600 Ω input impedance.

INM1, INP1 14 OFDS Offset Compensation Loop Disable. Pull high to disable the offset compensation loop. 15, 26 OFS2, OFS1 Offset Compensation Loop Capacitors. Connect capacitors to circuit common. 17, 18, 23, 24

OPP2, OPM2,

Differential Outputs. 30 Ω output impedance. Common-mode range is 0.7 V to 2.8 V; default is VPS/2.

OPM1, OPP1 20 VOCM Output Common-Mode Setpoint. Defaults to VPS/2 if left floating. 21 GAIN Analog Gain Control. 0 V to 1 V, 15.5 mV/dB gain scaling. 27 VICM

Input Common-Mode Voltage. VPS/2 V reference. Use to reference the optimal common-mode drive

to the differential inputs. 32 ENBL Chip Enable. Pull high to enable. EP Exposed Paddle. Connect the exposed paddle to a low impedance ground pad.

Rev. A | Page 7 of 28

ADRF6516 Data Sheet

A

–

TYPICAL PERFORMANCE CHARACTERISTICS

VPS = 3.3 V, TA = 25°C, Z

50

BANDWIDTH = 31MHz

45

40

35

30

25

VPS = 3.15V, 3.3V, 3.45V

20

15

GAIN (dB)

10

5

0

–5

–10

0 100 200 300 400

Figure 5. In-Band Gain vs. V

VPS = 3.15V, 3.3V, 3.45V

(Bandwidth Setting = 31 MHz)

= 1 kΩ, digital gain code = 111, unless otherwise noted.

LOAD

+25°C

–40°C

+85°C

VPS = 3.15V, 3.3V, 3.45V

500 600

V

(mV)

GAIN

over Supply and Temperature

GAIN

700 800 900

1000

09422-005

5.0 BANDWIDTH = 31MHz

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0 –0.5 –1.0 –1.5

GAIN ERROR (dB)

–2.0 –2.5 –3.0 –3.5 –4.0 –4.5 –5.0

+25°C VPS = 3.15V, 3.3V, 3.45V

0 100 200 300 400 500 600 700 800 900 1000

Figure 8. Gain Conformance vs. V

+85°C VPS = 3.15V, 3.3V, 3.45V

–40°C VPS = 3.15V, 3.3V, 3.45V

V

(mV)

GAIN

over Supply and Temperature

GAIN

(Bandwidth Setting = 31 MHz)

09422-008

50 45 40 35 30 25 20 15 10

5 0

–5

GAIN (dB)

–10 –15 –20 –25 –30 –35 –40 –45 –50

110

FREQUENCY (MHz)

Figure 6. Gain vs. Frequency over V

0.25

0.20

0.15

0.10

0.05

TCH (dB)

0

–0.05

–0.10

GAIN MISM

–0.15

–0.20

–0.25

0 100 200 300 400 500 600 700 800 900 1000

Figure 7. Gain Matching vs. V

V

GAIN

BANDWIDTH = 31MHz

(Bandwidth Setting = 31 MHz)

GAIN

BANDWIDTH = 31MHz

(mV)

(Bandwidth Setting = 31 MHz)

–10

–11

AMPLI TUDE (d B)

–12

–13

–14

100

09422-006

09422-007

–15

–5

–10

–15

AMPLITUDE ( dB)

–20

–25

–30

5

BANDWIDTH = 31MHz

–6

–7

DIGITAL GAIN = 111

–8

–9

DIGITAL GAIN = 011

0 5 10 15 20 25 30 35

FREQUENCY ( MHz)

Figure 9. Gain Step and Gain Error vs. Frequency

(Bandwidth Setting = 31 MHz, V

0

BANDWIDTH = 31MHz

DIGITAL GAIN = 011

DIGITAL GAIN = 000

0 5 10 15 20 25 30 35

FREQUENCY ( MHz)

GAIN

= 0 V)

Figure 10. Gain Step and Gain Error vs. Frequency

(Bandwidth Setting = 31 MHz, V

GAIN

= 0 V)

8

7

6

5

4

3

2

GAIN STEP (dB)

1

0

–1

–2

09422-009

14

13

12

11

GAIN STEP (dB)

10

9

8

09422-010

Rev. A | Page 8 of 28

Data Sheet ADRF6516

A

L

A

20

BANDWIDTH = 31MHz

15

10

DIGITAL GAIN = 111

DIGITAL GAIN = 000

0 5 10 15 20 25 30 35 40

GAIN (dB)

OP1dB (dBV )

5

0

–5

–10

–15

–20

Figure 11. Output P1dB vs. Gain at 15 MHz (Bandwidth Setting = 31 MHz)

40

35

30

25

20

15

GAIN (dB)

10

5

0

–5

–10

110

FREQUENCY ( MHz)

100

Figure 12. Frequency Response vs. Bandwidth Setting (Gain = 30 dB),

Log Scale

40

BANDWIDTH = 31MHz

38

36

34

32

30

GAIN (dB)

28

+25°C, VPS = 3.15V, 3.3V, 3.45V

26

24

22

20

09422-011

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40

–40°C, VPS = 3.15V, 3.3V, 3.45V

+85°C,

VPS = 3.15V, 3.3V, 3.45V

V

(mV)

GAIN

09422-014

Figure 14. Frequency Response over Supply and Temperature

(Bandwidth Setting = 31 MHz, Gain = 30 dB)

1000

GAIN = 20dB

900

800

700

600

Y (ns)

500

400

GROUP DEL

300

200

100

0

0.3 3 30

09422-012

BW = 1MHz

BW = 5MHz

BW = 10MHz

FREQUENCY ( MHz)

BW = 31MHz

BW = 20MHz

50

09422-015

Figure 15. Group Delay vs. Frequency (Gain = 20 dB)

40

35

30

25

20

15

GAIN (dB)

10

5

0

–5

–10

0 102030405060708090100

FREQUENCY ( MHz)

Figure 13. Frequency Response vs. Bandwidth Setting (Gain = 30 dB),

Linear Scale

09422-013

2.0 BANDWIDTH = 31MHz

1.5

1.0

TCH (ns)

0.5

0

Y MISM

–0.5

–1.0

GROUP DE

–1.5

–2.0

0.3 3 30

GAIN = 20dB

GAIN = 40dB

FREQUENCY ( MHz)

Figure 16. Group Delay Matching vs. Frequency

(Bandwidth Setting = 31 MHz)

09422-016

Rev. A | Page 9 of 28

ANALOG DEVICES ADRF6516 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

TIMING DIAGRAMS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS