Input voltage range: 3.3 V to 20 V
Maximum output current: 300 mA
Low noise: 15 µV rms for fixed output versions
PSRR performance of 60 dB at 10 kHz, V
Reverse current protection
Low dropout voltage: 200 mV at 300 mA load
Initial accuracy: ±0.8%
Accuracy over line, load, and temperature: −2%, +1%
Low quiescent current (V
= 5 V), I
IN
GND
load
Low shutdown current: 40 µA at V
IN
Stable with small 1 µF ceramic output capacitor
7 fixed output voltage options: 1.5 V, 1.8 V, 2.5 V, 3 V, 3.3 V,
5 V, and 9 V
Adjustable output from 1.22 V to V
Foldback current limit and thermal overload protection
User programmable precision UVLO/enable
Power good indicator
8-lead LFCSP and 8-lead SOIC packages
= 3.3 V
OUT
= 750 μA with 300 mA
= 12 V
– VDO
IN
TYPICAL APPLICATION CIRCUITS
Figure 1. ADP7102 with Fixed Output Voltage, 5 V
Figure 2. ADP7102 with Adjustable Output Voltage, 5 V
APPLICATIONS
Regulation to noise sensitive applications: ADC, DAC
circuits, precision amplifiers, high frequency oscillators,
clocks, and PLLs
Communications and infrastructure
Medical and healthcare
Industrial and instrumentation
GENERAL DESCRIPTION
The ADP7102 is a CMOS, low dropout linear regulator that
operates from 3.3 V to 20 V and provides up to 300 mA of
output current. This high input voltage LDO is ideal for
regulation of high performance analog and mixed signal
circuits operating from 19 V to 1.22 V rails. Using an
advanced proprietary architecture, it provides high power
supply rejection, low noise, and achieves excellent line and
load transient response with just a small 1 µF ceramic
output capacitor.
The ADP7102 is available in 7 fixed output voltage options and
an adjustable version, which allows output voltages that range
from 1.22 V to V
− VDO via an external feedback divider.
IN
The ADP7102 output noise voltage is 15 μV rms and is independent of the output voltage. A digital power good output
allows power system monitors to check the health of the output
voltage. A user programmable precision undervoltage lockout
function facilitates sequencing of multiple power supplies.
The ADP7102 is available in 8-lead, 3 mm × 3 mm LFCSP
and 8-lead SOIC packages. The LFCSP offers a very compact
solution and also provides excellent thermal performance for
applications requiring up to 300 mA of output current in a
small, low-profile footprint.
Information furnishe d by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
ADP7102 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
UVLO Hysteresis Current UVLO
Enable Pulldown Current I
INPUT VOLTAGE
Shutdown Threshold V
Hysteresis 250 mV
OUTPUT NOISE OUT
10 Hz to 100 kHz, VIN = 6.3 V, V
10 Hz to 100 kHz, VIN = 8 V, V
10 Hz to 100 kHz, VIN = 12 V, V
10 Hz to 100 kHz, VIN = 5.5 V, V
10 Hz to 100 kHz, VIN = 12 V, V
10 Hz to 100 kHz, VIN = 18 V, V
POWER SUPPLY REJECTION RATIO PSRR 100 kHz, VIN = 4.3 V, V
100 kHz, VIN = 6 V, V
10 kHz, VIN = 4.3 V, V
10 kHz, VIN = 6 V, V
100 kHz, VIN = 3.3 V, V
100 kHz, VIN = 6 V, V
100 kHz, VIN = 16 V, V
10 kHz, VIN = 3.3 V, V
10 kHz, VIN = 6 V, V
10 kHz, VIN = 16 V, V
1
Based on an end-point calculation using 1 mA and 300 mA loads. See Figure 6 for typical load re gulation performance for loads less than 1 mA.
2
Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output
voltages above 3.0 V.
3
Start-up time is defined as the time between the rising edge of EN to VOUT being at 90% of its nominal value.
4
Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 5.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 5.0 V, or 4.5 V.
3.3 V ≤ VIN ≤ 20 V, TJ = −40°C to +125°C 1.18 1.23 1.28 V
RISE
3.3 V ≤ VIN ≤ 20 V, TJ = −40°C to +125°C, 10 kΩ
FAL L
1.13 V
in series with enable pin
VEN > 1.25 V, TJ = −40°C to +125°C 7.5 9.8 12 µA
HYS
EN = VIN 500 nA
EN-IN
STA RT
TJ = −40°C to +125°C 2.45 V
SHUTDOWN
10 Hz to 100 kHz, VIN = 5.5 V, V
NOISE
= 1.8 V 15 µV rms
OUT
= 3.3 V 15 µV rms
OUT
= 5 V 15 µV rms
OUT
= 9 V 15 µV rms
OUT
= 1.5 V,
OUT
18 µV rms
adjustable mode
OUT
= 5 V,
30 µV rms
adjustable mode
= 15 V,
OUT
65 µV rms
adjustable mode
= 3.3 V 50 dB
OUT
= 5 V 50 dB
OUT
= 3.3 V 60 dB
OUT
= 5 V 60 dB
OUT
= 1.8 V, adjustable mode 50 dB
OUT
= 5 V, adjustable mode 60 dB
OUT
= 15 V, adjustable mode 60 dB
OUT
= 1.8 V, adjustable mode 60 dB
OUT
= 5 V, adjustable mode 80 dB
OUT
= 15 V, adjustable mode 80 dB
OUT
INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS
Table 2.
Parameter Symbol Conditions Min Typ Max Unit
Minimum Input and Output Capacitance1 C
Capacitor ESR R
1
The minimum input and output capacitance should be greater than 0.7 μF over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended;
Y5V and Z5U capacitors are not recommended for use with any LDO.
TA = −40°C to +125°C 0.7 µF
MIN
TA = −40°C to +125°C 0.001 0.2 Ω
ESR
Rev. A | Page 4 of 28
Data Sheet ADP7102
Operating Ambient Temperature Range
–40°C to +85°C
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
VIN to GND –0.3 V to +22 V
VOUT to GND –0.3 V to +20 V
EN/UVLO to GND –0.3 V to VIN
PG to GND –0.3 V to VIN
SENSE/ADJ to GND –0.3 V to VOUT
Storage Temperature Range –65°C to +150°C
Operating Junction Temperature Range –40°C to +125°C
Soldering Conditions JEDEC J-STD-020
Stresses above those listed under absolute maximum ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination. The ADP7102 can be damaged when the junction
temperature limit is exceeded. Monitoring ambient temperature
does not guarantee that T
limits. In applications with high power dissipation and poor
thermal resistance, the maximum ambient temperature may
have to be derated.
In applications with moderate power dissipation and low PCB
thermal resistance, the maximum ambient temperature can
exceed the maximum limit as long as the junction temperature
is within specification limits. The junction temperature (T
the device is dependent on the ambient temperature (T
power dissipation of the device (P
ambient thermal resistance of the package (θ
Maximum junction temperature (T
ambient temperature (T
formula
T
= TA + (PD × θJA)
J
Junction-to-ambient thermal resistance (θ
based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent on
the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
is within the specified temperature
J
) of
J
), the
A
), and the junction-to-
D
).
JA
) is calculated from the
J
) and power dissipation (PD) using the
A
) of the package is
JA
board design is required. The value of θ
on PCB material, layout, and environmental conditions. The
specified values of θ
are based on a 4-laye r, 4 in. × 3 in. circuit
JA
board. See JESD51-7 and JESD51-9 for detailed information on
the board construction. For additional information, see the
AN-617 Application Note, MicroCSP™ Wafer Level Chip Scale
Package, available at www.analog.com.
Ψ
is the junction-to-board thermal characterization parameter
JB
with units of °C/W. The package’s Ψ
calculation using a 4-layer board. The JESD51-12, Guidelines
for Reporting and Using Electronic Package Thermal
Information, states that thermal characterization parameters are
not the same as thermal resistances. Ψ
component power flowing through multiple thermal paths
rather than a single path as in thermal resistance, θ
Ψ
thermal paths include convection from the top of the
JB
package as well as radiation from the package, factors that make
Ψ
more useful in real-world applications. Maximum junction
JB
temperature (T
and power dissipation (P
T
= TB + (PD × ΨJB)
J
) is calculated from the board temperature (TB)
J
) using the formula
D
See JESD51-8 and JESD51-12 for more detailed information
about Ψ
.
JB
Thermal Resistance
θJA and ΨJB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
θ
is a parameter for surface-mount packages with top
2. IT IS HI GHLY RECOM M E NDE D THAT THE
EXPOSED PAD ON THE BOTTOM OF THE
PACKAGE BE CONNE CTED TO THE GROUND
PLANE ON T HE BOARD.
3GND
4NC
1VOUT
2SENSE/ADJ
6 GND
5 EN/UVLO
8 VIN
7 PG
ADP7102
TOP VIEW
(Not to S cale)
09506-003
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO
THIS PIN.
2. IT IS HI GHLY RECOM M E NDE D THAT THE
EXPOSED PAD ON THE BOTTOM OF THE
PACKAGE BE CONNE CTED TO THE GROUND
PLANE ON T HE BOARD.
VOUT
1
SENSE/ADJ
2
GND
3
NC
4
VIN
8
PG
7
GND
6
EN/UVLO
5
ADP7102
TOP VIEW
(Not to S cale)
09506-104
Sense (SENSE). Measures the actual output voltage at the load and feeds it to the error amplifier.
performance and is electrically connected to GND inside the package. It is highly recommended
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 3. LFCSP Package
Figure 4. Narrow Body SOIC Package
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 VOUT Regulated Output Voltage. Bypass VOUT to GND with a 1 µF or greater capacitor.
2 SENSE/ADJ
Connect SENSE as close as possible to the load to minimize the effect of IR drop between the
regulator output and the load. This function applies to fixed voltages only.
Adjust Input (ADJ). An external resistor divider sets the output voltage. This function applies to
adjustable voltages only.
3 GND Ground.
4 NC Do Not Connect to this Pin.
5 EN/UVLO Enable Input (EN). Drive EN high to turn on the regulator; drive EN low to turn off the regulator.
For automatic startup, connect EN to VIN.
Programmable Undervoltage Lockout (UVLO). When the programmable UVLO function is used,
the upper and lower thresholds are determined by the programming resistors.
6 GND Ground.
7 PG Power Good. This open-drain output requires an external pull-up resistor to VIN or VOUT. If the
part is in shutdown, current limit, thermal shutdown, or falls below 90% of the nominal output
voltage, PG immediately transitions low. If the power good function is not used, the pin may be
left open or connected to ground.
8 VIN Regulator Input Supply. Bypass VIN to GND with a 1 µF or greater capacitor.
EPAD Exposed Pad. Exposed paddle on the bottom of the package. The EPAD enhances thermal
that the EPAD be connected to the ground plane on the board.