ANALOG DEVICES ADP5589 Service Manual

Keypad Decoder and I/O Expansion

FEATURES

16-element FIFO for event recording 19 configurable I/Os allowing functions such as

Keypad decoding for matrix up to 11 × 8 Key press/release interrupts Key pad lock/unlock GPIO functions GPI with selectable interrupt level 100 kΩ or 300 kΩ pull-up resistors 300 kΩ pull-down resistors GPO with push-pull or open drain Dual programmable logic blocks PWM generator

Internal PWM generation

External PWM with internal PWM AND function Clock divider Reset generators

C interface with fast-mode plus (Fm+) support up to 1 MHz Open-drain interrupt output 24-lead LFCSP 3.5 mm × 3.5 mm 25-ball WLCSP 1.99 mm × 1.99 mm

APPLICATIONS

Devices requiring keypad entry and I/O expansion

capabilities

GENERAL DESCRIPTION

The ADP5589 is a 19 I/O port expander with built-in keypad matrix decoder, programmable logic, reset generator, and PWM generator. I/O expander ICs are used in portable devices (phones, remote controls, and cameras) and nonportable applications (healthcare, industrial, and instrumentation). I/O expanders can be used to increase the number of I/Os available to a processor or to reduce the number of I/Os required through interface connectors for front panel designs.

The ADP5589, which handles all key scanning and decoding, can flag the main processor via an interrupt line when new key events have occurred. In addition, GPI changes and logic changes can be tracked as events via the FIFO, eliminating the

ADP5589

FUNCTIONAL BLOCK DIAGRAM

ADP5589

RST

SCL

C10

UVLO

POR

I2C INTERFACE

I/O

CONFIG

KEY SCAN

AND

DECODE

GPI SCAN

AND

DECODE

LOGIC 1

LOGIC 2

CLK DIV

PWM

RESET 1

GEN

RESET 2

GEN

OSCILLAT OR

Figure 1.

need to monitor different registers for event changes. The

ADP5589 is equipped with a FIFO to store up to 16 events.

Events can be read back by the processor via an I interface.

The ADP5589 frees up the main processor from having to monitor the keypad, thereby reducing power consumption and/or increasing processor bandwidth for performing other functions.

The programmable logic functions allow common logic requirements to be integrated as part of the GPIO expander, saving board area and cost.

GND

REGISTERS

C compatible

INT

09714-001

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

ADP5589

Features.............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 5

Thermal Resistance ...................................................................... 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Quick Device Overview................................................................... 7

Device Enable................................................................................ 8

Device Overview .......................................................................... 8

Detailed Description ........................................................................9

Event FIFO.....................................................................................9

Key Scan Control...........................................................................9

GPO Output................................................................................ 15

Logic Blocks ................................................................................ 16

PWM Block................................................................................. 17

Clock Divider Block................................................................... 17

Reset Blocks ................................................................................ 17

Interrupts..................................................................................... 18

Detailed Register Descriptions................................................. 23

Application Diagram...................................................................... 47

Outline Dimensions....................................................................... 48

Ordering Guide .......................................................................... 48

REVISION HISTORY

8/11—Revision A: Initial Version

Rev. A | Page 2 of 48

ADP5589

SPECIFICATIONS

VDD = 1.8 V to 3.3 V, TA = −40°C to +85C, unless otherwise noted.1

Table 1.

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

SUPPLY VOLTAGE

VDD Input Voltage Range VDD 1.65 3.6 V Undervoltage Lockout Threshold UVLO

SUPPLY CURRENT

Standby Current I VDD = 3.3 V 1 10 µA Operating Current (One Key Press) I

PULL-UP, PULL-DOWN RESISTANCE

Pull-Up Option 1 50 100 150 kΩ Pull-Up Option 2 150 300 450 kΩ Pull-Down 150 300 450 kΩ

INPUT LOGIC LEVEL (

R5, R6, R7, C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10)

RST

, SCL, SDA, R0, R1, R2, R3, R4,

Logic Low Input Voltage VIL 0.3 × VDD V Logic High Input Voltage VIH 0.7 × VDD V Input Leakage Current (Per Pin) V

PUSH-PULL OUTPUT LOGIC LEVEL (R0, R1, R2, R3, R4,

R5, R6, R7, C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10) Logic Low Output Voltage2 V Logic Low Output Voltage3 V Logic High Output Voltage VOH Source current = 5 mA 0.7 × VDD V Logic High Leakage Current (Per Pin) V

INT

, SDA)

)

OPEN-DRAIN OUTPUT LOGIC LEVEL (

Logic Low Output Voltage ( Logic Low Output Voltage (SDA) VOL I Logic High Leakage Current (Per Pin) V Logic Propagation Delay 125 300 ns FF1 Hold Time4 0 ns FF1 Setup Time4 175 ns FF2 Hold Time

FF2 Setup Time4 175 ns GPIO Debounce4 70 µs Internal Oscillator Frequency5 OSC

I2C TIMING SPECIFICATIONS

Delay from UVLO/Reset Inactive to I2C Access 60 µs SCL Clock Frequency f SCL High Time t SCL Low Time t Data Setup Time t Data Hold Time t Setup Time for Repeated Start t

UVLO active, VDD falling 1.2 1.3 V

VDD

UVLO inactive, VDD rising 1.4 1.6 V

VDD = 1.65 V 1 4 A

STNBY

CORE_FREQ = 50 kHz, scan active,

SCAN = 10 ms

30 40 µA

300 kΩ pull-up, VDD = 1.65 V

CORE_FREQ = 50 kHz, scan active,

SCAN = 10 ms

35 45 µA

100 kΩ pull-up, VDD = 1.65 V

CORE_FREQ = 50 kHz, scan active,

SCAN = 10 ms

75 85 A

300 kΩ pull-up, VDD = 3.3 V

CORE_FREQ = 50 kHz, scan active,

SCAN = 10 ms

80 90 A

100 kΩ pull-up, VDD = 3.3 V

0.1 1 µA

I-Leak

Sink current = 10 mA 0.4 V

Sink current = 10 mA 0.5 V

0.1 1 µA

OH-Leak

0.1 1 µA

OH-Leak

= 10 mA 0.4 V

SINK

= 20 mA 0.4 V

SINK

0 ns

900 1000 1100 kHz

FREQ

0 1000 kHz

SCL

0.26 µs

HIGH

0.5 µs

LOW

50 ns

SU; DAT

HD; DAT

0.26 µs

SU; STA

µs

Rev. A | Page 3 of 48

ADP5589

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

Hold Time for Start/Repeated Start t Bus Free Time for Stop and Start Condition t Setup Time for Stop Condition t Data Valid Time t Data Valid Acknowledge t Rise Time for SCL and SDA tR 120 ns Fall Time for SCL and SDA tF 120 ns Pulse Width of Suppressed Spike tSP 0 50 ns Capacitive Load for Each Bus Line C

All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). Typical values are at TA = 25°C, VDD = 1.8 V.

Maximum of five GPIOs active simultaneously.

All GPIOs active simultaneously.

Guaranteed by design.

All timers are referenced from the base oscillator and have the same ±10% accuracy.

CB is the total capacitance of one bus line in picofarads.

SDA

SCL

SDA

70%

30%

HD; DAT

70%

30%

HD; STA

SCL

FIRST CL OCK CYCLE

70% 30%

70%

30%

0.26 µs

HD; STA

0.5 µs

BUF

0.26 µs

SU; STO

0.45 µs

VD; DAT

0.45 µs

VD; ACK

SU; DAT

550 pF

70%

30%

VD; DAT

NINTH CLOCK

BUF

70%

30%

LOW

HIGH

SCL

VIL = 0.3VDD

= 0.7VDD

SU; STA

HD; STA

Sr PS

Figure 2. I

C Interface Timing Diagram

70%

30%

VD; ACK

SU; STO

NINTH CLOCK

09714-002

Rev. A | Page 4 of 48

ADP5589

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

VDD to Ground –0.3 V to 4 V SCL, SDA, RST, INT, R0, R1, R2,

–0.3 V to (VDD + 0.3 V)

R3, R4, R5, R6, R7, C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10 to Ground

Operating Ambient

−40°C to +85°C

Temperature Range

Operating Junction

−40°C to +125°C

Temperature Range Storage Temperature Range −65°C to +150°C Soldering Conditions JEDEC J-STD-020

In applications where high power dissipation and poor thermal resistance

are present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (T operating junction temperature (T dissipation of the device (P resistance of the part/package in the application (θ equation: T

A(MAX)

= T

J(MAXOP)

D(MAX)

− (θJA × P

) is dependent on the maximum

A(MAX)

= 125°C), the maximum power

J(MAXOP)

), and the junction-to-ambient thermal

D(MAX)

), using the following

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified, all other voltages are referenced to ground.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.

Table 3.

Thermal Resistance θJA Unit

24-Lead LFCSP 43.83 C/W Maximum Power Dissipation 120 mW 25-Ball WLCSP 43 C/W Maximum Power Dissipation 120 mW

ESD CAUTION

Rev. A | Page 5 of 48

ADP5589

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

INT

SCL

C10

NOTES

1. THE EXPOSED

ADP5589

TOP VIEW

(Not to Scale)

PAD MUST BE CONN

Figure 3. LFCSP Pin Configuration

Table 4. Pin Function Descriptions

Pin No. (LFCSP)

Pin No. (WLCSP) Mnemonic Description

1 E3 R7 2 E2 R6 3 E1 R5 4 D1 R4 5 D2 R3 6 C1 R2 7 C2 R1 8 B1 R0 9 B4 C0 10 C3 C1 11 C4 C2 12 D3 C3 13 D4 C4 14 E4 C5 15 E5 C6 16 D5 C7 17 B3

RST 18 A1 VDD 19 C5 C8 20 B5 C9

21 A5 C10 22 A2 SDA 23 A3 SCL 24 B2

INT EP (pad) A4 GND

VDD

ECTED

09714-003

TO GROUND.

GPIO 8. This pin functions as Row 7 if used as keypad.

GPIO 7. This pin functions as Row 6 if used as keypad.

GPIO 6. This pin functions as Row 5 if used as keypad.

GPIO 5 (GPIO alternate function: RESET1). This pin functions as Row 4 if used as keypad.

GPIO 4 (GPIO alternate function: LC1, PWM_OUT, or CLK_OUT. This pin functions as Row 3 if used as keypad.

GPIO 3 (GPIO alternate function: LB1). This pin functions as Row 2 if used as a keypad.

GPIO 2 (GPIO alternate function: LA1). This pin functions as Row 1 if used as a keypad.

GPIO 1 (GPIO alternate function: LY1). This pin functions as Row 0 if used as a keypad.

GPIO 9. This pin functions as Column 0 if used as keypad.

GPIO 10. This pin functions as Column 1 if used as keypad.

GPIO 11. This pin functions as Column 2 if used as keypad.

GPIO 12. This pin functions as Column 3 if used as keypad.

GPIO 13 (GPIO alternate function: RESET2). This pin functions as Column 4 if used as keypad.

GPIO 14. This pin functions as Column 5 if used as keypad.

GPIO 15 (GPIO alternate function: LC2, PWM_IN, or CLK_IN). This pin functions as Column 6 if used as keypad.

GPIO 16 (GPIO alternate function: LB2). This pin functions as Column 7 if used as keypad.

Input Reset Signal.

Supply Voltage Input.

GPIO 17 (GPIO alternate function: LA2). This pin functions as Column 8 if used as keypad.

GPIO 18 (GPIO alternate function: LY2). This pin functions as Column 9 if used as keypad.

GPIO 19. This pin functions as Column 10 if used as keypad.

I2C Data Input/Output.

I2C Clock Input.

Open-Drain Interrupt Output.

Ground. The exposed pad of the LFCSP package must be connected to ground.

BALLA1 CORNER

234

VDD SDA SCL GND C

INT

R2 R1 C1 C2 C8

R5 R6 R7 C5

TOP VIEW

(BALL SI DE DOWN)

Not to Scale

C0 C9

RST

C3 C4 C7

Figure 4. WLCSP Pin Configuration

09714-104

Rev. A | Page 6 of 48

ADP5589

QUICK DEVICE OVERVIEW

ADP5589

RST

SDA

SCL

C10

I/O

CONFIGURATION

(R0) (R1) (R2) (R3) (R4) (R5) (R6) (R7) (C0) (C1) (C2) (C3) (C4) (C5) (C6) (C7) (C8) (C9) (C10)

(R1) (R2) (R3)

(R0)

(C8) (C7) (C6)

(C9)

(C6)

(R3)

(C6)

(R3)

UVLO

POR

I2C INTERFACE

ROW 0 ROW 1 ROW 2 ROW 3 ROW 4 ROW 5 ROW 6 ROW 7

COL 0 COL 1 COL 2 COL 3 COL 4 COL 5 COL 6 COL 7 COL 8 COL 9

COL 10

GPIO 1 GPIO 2 GPIO 3 GPIO 4 GPIO 5 GPIO 6 GPIO 7 GPIO 8

GPIO 9 GPIO 10 GPIO 11 GPIO 12 GPIO 13 GPIO 14 GPIO 15 GPIO 16 GPIO 17 GPIO 18 GPIO 19

LA1 LB1 LC1

LY1

LA2

LB2 LC2

LY2

CLK_IN

CLK_OUT

PWM_IN

PWM_OUT

OSCILLATOR

KEY SCAN

AND

DECODE

GPI SCAN

AND

DECODE

LOGIC 1

LOGIC 2

CLK DIV

PWM

C BUSY?

KEY EVENT

GPI EVENT

LOGIC EVENT

GND

UPDATE

INT

FIFO

REGISTERS

(R4)

RESET1

(C4)

RESET2

RESET1

GEN

RESET2

GEN

RST

9714-004

Figure 5. Internal Block Diagram

Rev. A | Page 7 of 48

ADP5589

DEVICE ENABLE

I/O

RST

pin is

When sufficient voltage is applied to VDD and the driven with a logic high level, the starts up in standby

ADP5589

mode with all settings at default. The user can configure the device via the I

ADP5589

The

enters a reset state and all settings return to default.

RST

pin features a debounce filter.

C interface. When the

RST

pin is low, the

DEVICE OVERVIEW

The ADP5589 contains 19 multiconfigurable input/output pins. Each pin can be programmed to enable the device to carry out its various functions, as follows:

• Keypad matrix decoding (11-column by 8-row matrix

maximum).

• General-purpose I/O expansion (up to 19 inputs/outputs).

• PWM generation.

• Clock division of externally supplied source.

• Dual logic function building blocks (up to three inputs,

one output).

• Two re s et generators.

All 19 input/output pins have an I/O structure, as shown in Figure 6.

100kΩ

300kΩ

I/O

DRIVE

300kΩ

Each I/O can be pulled up with a 100 kΩ or 300 kΩ resistor or pulled down with a 300 kΩ resistor. For logic output drive, each I/O has a 5 mA PMOS source and a 10 mA NMOS sink for push-pull type output. For open-drain output situations, the 5 mA PMOS source is not enabled. For logic input applications, each I/O can be sampled directly or, alternatively, sampled through a debounce filter.

The I/O structure shown in Figure 6 allows for all GPI and GPO functions, as well as PWM and clock divide functions. For key matrix scan and decode, the scanning circuit uses the 100 kΩ or 300 kΩ resistor for pulling up keypad row pins and the 10 mA NMOS sinks for grounding keypad column pins (see the Key Scan Control section for details about key decoding).

Configuration of the device is carried out by programming an array of internal registers via the I

C interface. Feedback of device status and pending interrupts can be flagged to an external processor via the

INT

pin.

The ADP5589 is offered with three feature sets. Ta b le 5 lists the options that are available for each model of the ADP5589.

Table 5. Available Options

Models Description

ADP5589ACPZ-00-R7

All GPIOs pulled up (default option)

ADP5589ACBZ-00-R7 ADP5589ACPZ-01-R7

Reset pass-through1

ADP5589ACBZ-01-R7 ADP5589ACPZ-02-R7

ADP5589ACBZ-02-R7

Reset pass-through implies that the RESET1 output (R4) follows the logic

level of the reset input pin,

Special function pins are defined as R0 (Row 0), R3 (Row 3), R4 (Row 4), C4

(Column 4), C6 (Column 6), and C9 (Column 9).

Pull-down on special function pins

RST

, after the oscillator has been enabled.

DEBOUNCE

Figure 6. I/O Structure

09714-005

Rev. A | Page 8 of 48

ADP5589

DETAILED DESCRIPTION

EVENT FIFO

It is important to understand the function of the event FIFO. The ADP5589 features an event FIFO that can record as many as 16 events. By default, the FIFO primarily records key events, such as key press and key release. However, it is possible to configure the general-purpose input (GPI) and logic activity to generate event information on the FIFO as well. An event count, EC[4:0], is composed of five bits and works in tandem with the FIFO so that the user knows how much of the FIFO must be read back at any given time.

The FIFO is composed of 16 eight-bit sections that the user accesses by reading the FIFO_x registers. The actual FIFO is not in user accessible registers until a read occurs. The FIFO can be thought of as a “first in, first out” buffer used to fill Register 0x03 to Register 0x12.

The event FIFO is made up of 16 eight-bit registers. In each register, Bits[6:0] hold the event identifier, and Bit 7 holds the event state. With seven bits, 127 different events can be identified. See Tab le 1 1 for event decoding.

OVRFLOW_INT

KEY EVENTS

GPI EVENTS

LOGIC EVENTS

When events are available on the FIFO, the user should first read back the event count, EC[4:0], to determine how many events must be read back. Events can be read from the top of the FIFO only. When an event is read back, all remaining events in the FIFO are shifted up one location, and the EC[4:0] count is decremented.

FIFO

UPDATE

EVENT1[7:0]

EVENT2[7:0]

EVENT3[7:0]

EVENT4[7:0]

EVENT5[7:0]

EVENT6[7:0]

EVENT7[7:0]

EVENT8[7:0]

EVENT9[7:0]

EVENT10[7:0]

EVENT11[7:0]

EVENT12[7:0]

EVENT13[7:0]

EVENT14[7:0]

EVENT15[7:0]

EVENT16[7:0]

Figure 7. Breakdown of Eventx[7:0] Bits

EC[4:0]

6543210

EVENT8_ID ENTIF IER[6:0]

EVENT8_STATE

FIRST READ

The FIFO registers (0x03 to 0x12) always point to the top of the FIFO (that is, the location of EVENT1[7:0]). If the user tries to read back from any location in a FIFO, data is always obtained from the top of that FIFO. This ensures that events can only be read back in the order in which they occurred, thus ensuring the integrity of the FIFO system.

Some of the onboard functions of ADP5589 can be programmed to generate events on the FIFO. A FIFO update control block manages updates to the FIFO. If an I accessing any of the FIFO address locations, updates are paused until the I

A FIFO overflow event occurs when more than 16 events are generated prior to an external processor reading a FIFO and clearing it.

If an overflow condition occurs, the overflow status bit is set. An interrupt is generated if overflow interrupt is enabled, signaling to the processor that more than 16 events have occurred.

KEY SCAN CONTROL

General

The 19 input/output pins can be configured to decode a keypad

09714-006

matrix up to a maximum size of 88 switches (11 × 8 matrix). Smaller matrices can also be configured, freeing up the unused row and column pins for other I/O functions.

The R0 through R7 I/O pins comprise the rows of the keypad matrix. The C0 through C10 I/O pins comprise the columns of the keypad matrix. Pins used as rows are pulled up via the internal 300 k (or 100 k) resistors. Pins used as columns are driven low via the internal NMOS current sink.

EC = 3

KEY 3 PRESSED

KEY 3 RELEASED

GPI 7 ACTIVE

SECOND

READ

C transaction has completed.

EC = 2

KEY 3 RELEASED

GPI 7 ACTIVE

THIRD

READ

Figure 8. FIFO Operation

EC = 1

GPI 7 ACTIVE

C transaction is

EC = 0

09714-007

Rev. A | Page 9 of 48

ADP5589

Figure 9. Simplified Key Scan Block

VDD

KEY

SCAN

CONTROL

R0 R1 R2C2C0 C1

3 × 3 KEYPAD MATRIX

09714-008

Figure 9 shows a simplified representation of the key scan block using three row and three column pins connected to a small 3 × 3, nine-switch keypad matrix. When the key scanner is idle, the row pins are pulled high and the column pins are driven low. The key scanner operates by checking the row pins to see if they are low.

If Switch 6 in the matrix is pressed, R1 connects to C2. The key scan circuit senses that one of the row pins is pulled low, and a key scan cycle begins. Key scanning involves driving all column pins high, then driving each column pin, one at a time, low and sensing whether a row pin is low or not. All row/column pairs are

scanned; therefore, if multiple keys are pressed, they are detected.

To prevent glitches or narrow press times being registered as a valid key press, the key scanner requires the key be pressed for two scan cycles. The key scanner has a wait time between each scan cycle; therefore, the key must be pressed and held for at least this wait time to register as being pressed. If the key is continuously pressed, the key scanner continues to scan, wait, scan, wait, and so forth.

If Switch 6 is released, the connection between R1 and C2 breaks, and R1 is pulled up high. The key scanner requires that the key be released for two scan cycles because the release of a key is not necessarily in sync with the key scanner, it may take up to two full wait/scan cycles for a key to register as released. When the key is registered as released, and no other keys are pressed, the key scanner returns to idle mode.

For the remainder of this document, the press/release status of a key is represented as simply a logic signal in the figures. A logic high level represents the key status as pressed, and a logic low represents released. This eliminates the need to draw individual row/column signals when describing key events.

KEY PRESSED

KEY x KEY RELEASED KEY RELEASE D

Figure 10. Logic Low: Released; Logic High: Pressed

9714-009

Figure 11 shows a detailed representation of the key scan block and its associated control and status signals. When all row and column pins are used, a matrix of 88 unique keys can be scanned.

Rev. A | Page 10 of 48

ADP5589

PIN_CONF IG_A[7:0] PIN_CONF IG_B[7:0] PIN_CONF IG_C[2:0]

RESET_TRIGGER_TIME[2:0]

RESET1_EVENT _A[7:0] RESET1_EVENT _B[7:0] RESET1_EVENT _C[7:0] RESET2_EVENT _A[7:0] RESET2_EVENT _B[7:0]

EXT_LOCK_EVENT[7:0]

UNLOCK1[7:0] UNLOCK2[7:0]

UNLOCK_TIMER[2: 0]

INT_MASK_TIMER[4:0]

LOCK_EN

SINK ON/OFF

16 17 18 19 20 21 2215141312

27 28 29 30 31 32 3326252423

38 39 40 41 42 43 4437363534

49 50 51 52 53 54 5548474645

60 61 62 63 64 65 6659585756

71 72 73 74 75 76 7770696867

82 83 84 85 86 87 8881807978

COLUMN

I/O CONFIG URATION

5678910114321

KEY SCAN CONTROL

Figure 11. Detailed Key Scan Block

Use Registers PIN_CONFIG_A[7:0] (0x49), PIN_CONFIG_B[7:0] (0x4A), and PIN_CONFIG_C[2:0] (0x4B) to configure I/Os for keypad decoding. The number label on each key switch represents the event identifier that is recorded if that switch is pressed. If all row/column pins are configured, it is possible to observe all 88 key identifiers on the FIFO.

If a smaller 3 × 3 matrix is configured, for example, using the C5, C6, and C7 column pins and the R1, R2, and R3 row pins, only the nine event identifiers (17, 18, 19, 28, 29, 30, 39, 40, and 41) can possibly be observed on the FIFO, as shown in Figure 11.

By default, the ADP5589 records key presses and releases on the FIFO. Figure 12 illustrates what happens when a single key is pressed and released. Initially, the key scanner is idle. When Key 32 is pressed, the scanner begins scanning through all configured row/column pairs. After the scan wait time, the scanner again scans through all configured row/column pairs and detects that Key 32 has remained pressed, which sets the EVENT_INT interrupt. The event counter, EC[4:0], is incremented to 1, EVENT1[7:0] of the FIFO is updated with its event identifier set to 32, and its Event1_State bit is set to 1, indicating a press.

RESET 1_INITIATE RESET 2_INITIATE

LOCK_STAT LOCK_INT

KEY EVENT

GPI EVENT

LOGIC EVENT

ROW

SENSE

EVENT_INT

C BUSY?

R0 R3R1 R2 R4 R7R5 R6C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10

KEY 32

KEY SCAN

EVENT_INT

EC[4:0]

FIFO

UPDATE

OVRFLOW_INT

EC[4:0]

FIFO

KEY 32 PRESS

KEY 32 RELEAS E

09714-010

1 2

FIFO 1

Figure 12. Press and Release Event

The key scanner continues the scan/wait cycles while the key remains pressed. If the scanner detects that the key has been released for two consecutive scan cycles, the event counter EC[4:0] is incremented to 2, and EVENT2[7:0] of the FIFO is updated with its event identifier set to 32. Its Event2_State bit is set to 0, indicating a release. The key scanner goes back to idle mode because no other keys are pressed.

The EVENT_INT interrupt can be triggered by both press and release key events. As shown in Figure 13, if Key 32 is pressed, EVENT_INT is asserted, EC[4:0] is updated, and the FIFO is updated. During the time that the key is still pressed, it is possible for the FIFO to be read, the event counter decremented to 0, and EVENT_INT cleared. When the key is finally released, EVENT_INT is asserted, the event counter incremented, and the FIFO updated with the release event information.

09714-011

Rev. A | Page 11 of 48

ADP5589

KEY 32

KEY SCAN

EVENT_INT

EC[4:0]

KEY 32 PRESS KEY 32 RELEASE

Figure 13. Asserting the EVENT_INT Interrupt

101

FIFO 1

FIFO

READ

EVENT_INT CLEARED

FIFO

FIFO 0 0 0 0

0 0 0

Key Pad Extension

As shown in Figure 11, the keypad can be extended if each row is connected directly to ground by a switch. If the switch placed between R0 and ground is pressed, the whole row is grounded. When the key scanner completes scanning, it normally detects Key 1 to Key 11 as being pressed; however, this unique condition is decoded by the ADP5589, and Key Event 89 is assigned to it. Up to eight more key event assignments are possible, allowing the keypad size to extend up to 96. However, if one of the extended keys is pressed, none of the keys on that row is detectable. Activation of a ground key causes all other keys sharing that row to be undetectable.

Ghosting

Ghosting is an occurrence where, given certain key press combinations on a keypad matrix, a false positive reading of an additional key is detected. Ghosting is created when three or more keys are pressed simultaneously on multiple rows or columns (see Figure 14). Key combinations that form a right angle on the keypad matrix can cause ghosting.

The solution to ghosting is to select a keypad matrix layout that takes into account three key combinations that are most likely to be pressed together. Multiple keys pressed across one row or across one column do not cause ghosting. Staggering keys so that they do not share a column also avoids ghosting. The most common practice is to place keys that are likely to be pressed together in the same row or column. Some examples of keys that are likely to be pressed together are as follows:

• The navigation keys in combination with Select.

• The navigation keys in combination with the space bar.

• The reset combination keys, such as CTRL + ALT + DEL.

COL0

ROW0

ROW1

ROW2

09714-012

Figure 14. COL0-ROW3 is a Ghost Key Due to Short Between ROW0, COL0,

ROW3

PRESS

GHOST

COL2 and ROW3 During Key Press

COL1 COL2

PRESS

09714-013

FIFO Lock/Unlock

The ADP5589 features a lock mode, whereby events are prevented from updating the FIFO or the event counter or from generating EVENT_INT interrupts until an unlock event is detected.

The lock feature is enabled by setting the LOCK_EN (0x37[0]) bit or, alternatively, by a user programmable key or GPI event (set via EXT_LOCK_EVENT[7:0], Address 0x35). If the lock feature is enabled by the LOCK_EN bit, the LOCK_STAT (0x02[5]) bit is set. If the lock feature is enabled by an external event, then the LOCK_STAT bit is set, and a LOCK_INT interrupt is generated.

Unlock events are programmed via the UNLOCK1[7:0] (0x33) and UNLOCK2[7:0] (0x34) registers. Bits[6:0] comprise the even number. Bit 7 determines the active/inactive event (see the UNLOCK1 Register 0x33 (Tabl e 59 ) and the UNLOCK2 Register 0x34 (Tabl e 60 ).

If the user chooses to use only one unlock event, only the UNLOCK1[7:0] register should be programmed. Unlock events can be key press events (Event 1 to Event 88). Key release events are ignored when the keypad is locked and should not be used as unlock events.

GPIs configured to generate FIFO updates can also be used as unlock events (Event 97 to Event 115, either active or inactive). If either UNLOCKx register is programmed with Value 127 (Event 127), this means that any allowable event (key or GPI) is the unlock event. For example, if UNLOCK1[6:0] is programmed with 17, and UNLOCK2[6:0] is programmed with 127, the unlock sequence is Key 17 press followed by any other allowable event.

If the first unlock event is detected, partial unlock has occurred. If the next event after the first unlock event is not the second unlock event, then a full lock state is entered again. If the next event after the first unlock event is the second unlock event, then LOCK_STAT is cleared, and a LOCK_INT interrupt is generated. The user can at any stage clear LOCK_EN. This clears the LOCK_STAT bit but does not cause a LOCK_INT interrupt to be generated.

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ADP5589

When full unlock is achieved, FIFO and event count updates resume. Note that if a key press is used as the second unlock event, the release of that key is captured on the FIFO after unlocking is completed.

The ADP5589 features an unlock timer, UNLOCK_TIMER[2:0] (0x36[2:0]). When enabled, after the first unlock event occurs, the unlock timer begins counting, and the second unlock event must occur before the unlock timer expires. If the unlock timer expires, the first unlock event must occur again to restart the unlock process. Figure 15 shows a simple state diagram of the unlocking process.

UNLOCK EVENT

LOCKED

EVENT

DETECTED?

YES

FIRST

UNLOCK

EVENT?

YES

SECOND

REQUIR ED?

YES

LOCK_STAT = 1

When lock mode is enabled, no EVENT_INT interrupts can be generated until the unlock events occur.

The ADP5589 features an interrupt mask timer, INT_MASK_ TIMER[4:0] (0x36[7:3]). When this timer and lock mode are enabled, a single EVENT_INT is generated if any key is pressed or any GPI (programmed to update the FIFO) is active. When the EVENT_INT is generated, the mask timer begins counting. No additional EVENT_INT interrupts are generated until the mask timer expires and a new key is pressed or any GPI (programmed to update the FIFO) is active, unless the unlock events occur, in which case, normal operation is resumed.

Allowing a single EVENT_INT interrupt is useful to alert the processor to turn on its screen and display an unlock message to the user. Blanking out additional key presses ensures that the processor is not unnecessarily interrupted until the unlock events occur. Figure 16 shows the unlock sequence when the interrupt mask timer is enabled.

UNLOCK

TIMER

ENABLED?

EVENT

DETECTED?

YES

LOCK_STAT = 0

START UNLOCK TIMER

YES

EVENT

DETECTED?

YES

UNLOCK

TIMER

EXPIRED?

SECOND

UNLOCK EVEN T?

YES

UNLOCK

YES

09714-014

Figure 15. State Diagram of Unlocking Process

Rev. A | Page 13 of 48

ADP5589

LOCKED

EVENT

DETECTED?

YES

MASK

TIMER ENABLED?

FIRST

UNLOCK

EVENT?

YES

SECOND

UNLOCK EVENT

REQUIRED ?

YES

UNLOCK

TIMER

ENABLED?

YES

START UNLOCK TIMER

EVENT

DETECTED?

YES

SET

EVENT_INT = 1

START MASK TIMER

LOCK_STAT = 1

YES

MASK

TIMER EXPI RED?

LOCK_STAT = 1

SET

EVENT_INT = 1

START MASK TIMER

YES

YES NO

TIMER EX PIRED?

TIMER E NABLED?

MASK

Figure 16. Unlock Sequence

MASK

EVENT_INT = 1

START MASK TIM ER

YES NO

SET

LOCK_STAT = 0

YES

MASK

TIMER E XPIRED?

EVENT

DETECTED?

YES

MASK

TIMER ENABLED?

UNLOCK

TIMER

EXPIRED?

SECOND

UNLOCK EVENT ?

YES

UNLOCK

YES

09714-015

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ADP5589

GPI Input

Each of the 19 I/O lines can be configured as a general-purpose logic input line. Figure 17 shows a detailed representation of the GPI scan and detect block and all its associated control and status signals.

PIN_CONFIG _A[7:0]

PIN_CONFIG _B[7:0]

PIN_CONFIG _C[2:0]

EXT_LOCK_EVENT[7:0]

INT_MASK_TIMER[4:0]

GPIO_DIRECTION_A[7:0]

GPIO_DIRECTION_B[7:0]

GPIO_DIRECTION_C[2:0]

GPI_INT_LEVEL_A[7:0]

GPI_INT_LEVEL_B[7:0]

GPI_INT_LEVEL_C[2:0]

GPI_I NTERRUPT_EN_A[7:0]

GPI_I NTERRUPT_EN_B[7:0]

GPI_I NTERRUPT_EN_C[2:0]

GPI_EVENT_EN_A[ 7:0]

GPI_EVENT_EN_B[ 7:0]

GPI_EVENT_EN_C[ 2:0]

RESET_TRIGGER_TIME[2:0]

RESET1_EVENT_A[7: 0]

RESET1_EVENT_B[7: 0]

RESET1_EVENT_C[7: 0]

RESET2_EVENT_A[7: 0]

RESET2_EVENT_B[7: 0]

LOCK_EN

UNLOCK1[7:0]

UNLOCK2[7:0]

UNLOCK_T IMER[2:0 ]

LCK_TRK_GPI

GPIO 1

(R0)

GPIO 2

(R1)

GPIO 3

(R2)

GPIO 4

(R3)

GPIO 5

(R4)

GPIO 6

(R5)

GPIO 7

(R6)

GPIO 8

(R7)

GPIO 9

(C0)

GPIO 10

(C1)

GPIO 11

(C2)

GPIO 12

(C3)

GPIO 13

(C4)

GPIO 14

(C5)

GPIO 15

(C6)

GPIO 16

(C7)

GPIO 17

(C8)

GPIO 18

(C9)

GPIO 19

(C10)

GPI SCAN

CONTROL

LOCK_STAT

LOCK_INT

EVENT_INT

GPI_INT

GPI_INT_STAT_A[7:0]

GPI_INT_STAT_B[7:0]

GPI_INT_STAT_C[2:0]

GPI_ STATUS_A[7:0 ]

GPI_ STATUS_B[7:0 ]

GPI_ STATUS_C[2:0 ]

C BUSY?

KEY EVENT

GPI EVENT

LOGI C EVENT

FIFO

UPDATE

OVRFLOW_INT

EC[4:0]

FIFO

Figure 17. GPI Scan and Detect Block

The current input state of each GPI can be read back using the GPI_STATUS_x registers. Each GPI can be programmed to generate an interrupt via the GPI_INTERRUPT_EN_x registers. The interrupt status is stored in the GPI_INT_STAT_x registers. GPI interrupts can be programmed to trigger on inputs being high or on inputs being low via the GPI_INT_LEVEL_x registers. If any of the GPI interrupts is triggered, the master GPI_INT interrupt is also triggered.

Figure 18 demonstrates a single GPI and how it affects its corresponding status and interrupt status bits.

GPI 6

GPI_INT_LEVEL_A[5]

PI_INTERRUPT_ EN_A[5]

GPI_STATUS_A[ 5]

GPI_INT_STAT_A[5]

GPI_INT

CLEARED BY READ

CLEARED BY WRITE ‘1’

09714-017

Figure 18. Single GPI Example

GPIs can be programmed to generate FIFO events via the GPI_EVENT_EN_x registers. GPIs in this mode do not generate GPI_INT interrupts and instead generate EVENT_INT interrupts. Figure 19 shows several GPI lines and their effects on the FIFO and event count, EC[4:0].

GPI 6

GPI 14

GPI 2

GPI SCAN

EVENT_INT

EC[4:0]

GPI 2 ACTIVE GPI 6 ACTIVE

GPI 14 ACTIVE

GPI 14 INACT IVE

GPI 6 ACTIVE GPI 2 ACTIVE

FIFO

101 105

113

105

101

234 5

09714-018

Figure 19. Multiple GPI Lines Example

The GPI scanner is idle until it detects a level transition. It scans the GPI inputs and updates accordingly. It then returns to idle immediately; it does not scan/wait, like the key scanner. As such, the GPI scanner can detect narrow pulses once they get past the 50 s input debounce filter.

09714-016

GPIs (programmed for FIFO updating) can be used as keypad unlock events via the UNLOCKx registers (see the FIFO Lock/Unlock section). The LCK_TRK_GPI bit can be used to allow GPIs (programmed for FIFO updating) to be tracked when the keypad is locked.

GPO OUTPUT

Each of the 19 I/O lines can be configured as a general-purpose output (GPO) line. Figure 6 shows a detailed diagram of the I/O structure. See the Detailed Register Descriptions section for GPO configuration and usage.

Rev. A | Page 15 of 48

+ 33 hidden pages

ANALOG DEVICES ADP5589 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

QUICK DEVICE OVERVIEW

DEVICE ENABLE

DEVICE OVERVIEW

DETAILED DESCRIPTION

EVENT FIFO

KEY SCAN CONTROL

General

Key Pad Extension

Ghosting

FIFO Lock/Unlock

GPI Input

GPO OUTPUT