ANALOG DEVICES ADP5585 Service Manual

V

Keypad Decoder and I/O Expansion

Data Sheet

FEATURES

16-element FIFO for event recording
10 configurable I/Os allowing functions such as

Key pad decoding for a matrix of up to 5 × 5

11 GPIOs (5 × 6) with ADP5585ACxZ-01-R7 models
Key press/release interrupts
GPIO functions
GPI with selectable interrupt level
100 kΩ or 300 kΩ pull-up resistors
300 kΩ pull-down resistors
GPO with push-pull or open-drain
Programmable logic block
PWM generator

Internal PWM generation
External PWM with internal PWM AND function

Reset generators

2

I

C interface with fast mode plus (Fm+) support of up to 1 MHz
Open-drain interrupt output
16-ball WLCSP, 1.59 mm × 1.59 mm
16-lead LFCSP, 3 mm × 3 mm

RST/R5

SDA

SCL

R0

R1

R2

R3

R4

C0

C1

C2

C3

C4

ADP5585

FUNCTIONAL BLOCK DIAGRAM

ADP5585

I/O

CONFIG

DD

UVLO

POR

I2C INTERFACE

KEY SCAN

AND

DECODE

GPI SCAN

AND

DECODE

LOGIC

PWM

RESET1

GEN

RESET2

GEN

Figure 1.

OSCILLATOR

GND

REGISTERS

INT

09841-001

APPLICATIONS

Keypad entries and input/output expansion capabilities
Smart phones, remote controls, and cameras
Healthcare, industrial, and instrumentation

GENERAL DESCRIPTION

The ADP5585 is a 10 input/output port expander with a built in
keypad matrix decoder, programmable logic, reset generator, and
PWM generator. Input/output expander ICs are used in portable
devices (phones, remote controls, and cameras) and nonportable
applications (healthcare, industrial, and instrumentation). I/O
expanders can be used to increase the number of I/Os available
to a processor or to reduce the number of I/Os required through
interface connectors for front panel designs.

The ADP5585 handles all key scanning and decoding and can
flag the main processor via an interrupt line that new key events
have occurred. GPI changes and logic changes can also be tracked

as events via the FIFO, eliminating the need to monitor different
registers for event changes. The ADP5585 is equipped with a
FIFO to store up to 16 events. Events can be read back by the
processor via an I

2

C-compatible interface.

The ADP5585 frees up the main processor from having to
monitor the keypad, thereby reducing power consumption
and/or increasing processor bandwidth for performing other
functions.

The programmable logic functions allow common logic require­ments to be integrated as part of the GPIO expander, thus saving
board area and cost.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

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Tel: [phone] www.analog.com
Fax: [phone] ©2011 Analog Devices, Inc. All rights reserved.

ADP5585 Data Sheet

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Diagram........................................................................... 4

Absolute Maximum Ratings............................................................ 5

Thermal Resistance ...................................................................... 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Theory of Operation ........................................................................ 7

Device Enable................................................................................ 8

Device Overview .......................................................................... 8

Functional Description.....................................................................9

Event FIFO.....................................................................................9

Key Scan Control...........................................................................9

GPI Input..................................................................................... 12

GPO Output................................................................................ 12

Logic Blocks ................................................................................ 12

PWM Block................................................................................. 13

Reset Blocks ................................................................................ 14

Register Interface............................................................................ 15

Register Map ................................................................................... 17

Detailed Register Descriptions................................................. 19

Applications Diagram.................................................................... 35

Outline Dimensions....................................................................... 36

Ordering Guide .......................................................................... 36

REVISION HISTORY

10/11—Rev. Sp0 to Rev. A

Added 16-Lead LFCSP_WQ Package..............................Universal

Changes to Features Section............................................................ 1

Added Figure 4; Renumbered Sequentially .................................. 6

Changes to Table 4............................................................................ 6

Changes to Device Enable Section and Table 5............................ 8

Change to General Section............................................................ 11

Changes to Logic Blocks Section.................................................. 12

Changes to PWM Block Section................................................... 13

Changes to Interrupts Section ...................................................... 14

Changes to Register Interface Section ......................................... 15

Changes to Figure 27...................................................................... 35

Updated Outline Dimensions....................................................... 36

Changes to Ordering Guide.......................................................... 38

5/11—Revision Sp0: Initial Version

Rev. A | Page 2 of 36

Data Sheet ADP5585

SPECIFICATIONS

VDD = 1.8 V to 3.3 V, TA = TJ = −40°C to +85°C, unless otherwise noted1.

Table 1.

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

SUPPLY VOLTAGE

VDD Input Voltage Range VDD 1.65 3.6 V

Undervoltage Lockout Threshold UVLO
UVLO inactive, VDD rising 1.4 1.6 V
SUPPLY CURRENT

Standby Current I

VDD = 3.3 V 1 10 µA

Operating Current (One Key Press) I

I

I

I

PULL-UP, PULL-DOWN RESISTANCE

Pull-Up

Option 1 50 100 150 kΩ
Option 2 150 300 450 kΩ

Pull-Down 150 300 450 kΩ
INPUT LOGIC LEVEL (RST, SCL, SDA, R0, R1, R2,

R3, R4, R5, C0, C1, C2, C3, C4)

Input Voltage

Logic Low VIL 0.3 VDD V
Logic High VIH 0.7 VDD V

Input Leakage Current (Per Pin) V
PUSH-PULL OUTPUT LOGIC LEVEL (R0, R1, R2, R3,

R4, R5, C0, C1, C2, C3, C4)

Output Voltage

Logic Low V

V

Logic High VOH Source current = 5 mA 0.7 VDD V

Logic High Leakage Current (Per Pin) V
OPEN-DRAIN OUTPUT LOGIC LEVEL (INT, SDA)

Output Voltage

Logic Low

INT

V

SDA V
Logic High Leakage Current (Per Pin) V
Logic Propagation Delay 125 300 ns
FF Hold Time2 0 ns
FF Setup Time2 175 ns
GPIO Debounce2 70 µs
Internal Oscillator Frequency3 OSC

UVLO active, VDD falling 1.2 1.3 V

VDD

VDD = 1.65 V 1 4 A

STNBY

SCAN1

Scan = 10 ms, CORE_FREQ = 50 kHz,

30 40 µA

scan active, 300 kΩ pull-up, VDD = 1.65 V

SCAN2

Scan = 10 ms, CORE_FREQ = 50 kHz,

35 45 µA

scan active, 100 kΩ pull-up, VDD = 1.65 V

SCAN3

Scan = 10 ms, CORE_FREQ = 50 kHz,

75 85 A

scan active, 300 kΩ pull-up, VDD = 3.3 V

SCAN4

Scan = 10 ms, CORE_FREQ = 50 kHz,

80 90 A

scan active, 100 kΩ pull-up, VDD = 3.3 V

0.1 1 µA

I-Leak

OL1

Sink current = 10 mA, maximum of five

0.4 V

GPIOs active simultaneously

OL2

Sink current = 10 mA, all GPIOs active

0.5 V

simultaneously

0.1 1 µA

OH-Leak

I

OL3

I

OL4

0.1 1 µA

OH-Leak

FREQ

= 10 mA 0.4 V

SINK

= 20 mA 0.4 V

SINK

900 1000 1100 kHz

Rev. A | Page 3 of 36

ADP5585 Data Sheet

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

I2C TIMING SPECIFICATIONS

Delay from UVLO/Reset Inactive to I2C Access 60 µs
SCL Clock Frequency f
SCL High Time t
SCL Low Time t
Data Setup Time t
Data Hold Time t
Setup Time for Repeated Start t
Hold Time for Start/Repeated Start t
Bus Free Time for Stop and Start Condition t
Setup Time for Stop Condition t
Data Valid Time t
Data Valid Acknowledge t
Rise Time for SCL and SDA tR 120 ns
Fall Time for SCL and SDA tF 120 ns
Pulse Width of Suppressed Spike tSP 0 50 ns
Capacitive Load for Each Bus Line C

1

All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). Typical values are at TA = 25°C, VDD = 1.8 V.

2

Guaranteed by design.

3

All timers are referenced from the base oscillator and have the same ±10% accuracy.

4

CB is the total capacitance of one bus line in picofarads.

TIMING DIAGRAM

SDA

SCL

SDA

70%

30%

t

F

S

t

R

t

t

F

HD; DAT

70%

30%

t

HD; STA

f

1/

SCL

FIRST CLOCK CYCLE

0 1000 kHz

SCL

0.26 µs

HIGH

0.5 µs

LOW

50 ns

SU; DAT

0 µs

HD; DAT

0.26 µs

SU; STA

0.26 µs

HD; STA

0.5 µs

BUF

0.26 µs

SU; STO

0.45 µs

VD; DAT

0.45 µs

VD; ACK

70%
30%

70%

30%

4

B

t

SU; DAT

550 pF

t

70%

30%

VD; DAT

NINTH CL OCK

t

BUF

t

t

R

70%

30%

t

LOW

HIGH

t

VD; ACK

t

SU; STO

70%

30%

NINTH CLOCK

C Interface Timing Diagram

09841-002

SCL

VIL = 0.3VDD

= 0.7VDD

V

IH

t

SU; STA

t

HD; STA

t

SP

Sr PS

Figure 2. I

2

Rev. A | Page 4 of 36

Data Sheet ADP5585

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

VDD to GND −0.3 V to +4 V
SCL, SDA, RST, INT, R0, R1, R2, R3, R4,

−0.3 V to (VDD + 0.3 V)

C0, C1, C2, C3, C4 to GND

Temperature Range

Operating (Ambient) −40°C to +85°C

1

Operating (Junction) −40°C to +125°C
Storage −65°C to +150°C

1

In applications where high power dissipation and poor thermal resistance

are present, the maximum ambient temperature may need to be derated.
Maximum ambient temperature (T
operating junction temperature (T
dissipation of the device (P
resistance of the device/package in the application (θ
equation: T

A (MAX)

= T

J (MAXOP)

D (MAX)

− (θJA × P

) is dependent on the maximum

A (MAX)

= 125°C), the maximum power

J (MAXOP)

), and the junction-to-ambient thermal

).

D (MAX)

), using the following

JA

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Absolute maximum ratings apply individually only, not in
combination. Unless otherwise specified, all other voltages are
referenced to GND.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a printed circuit board (PCB) for surface-mount
packages.

Table 3.

Thermal Resistance θJA Unit

16-Ball WLCSP 62 °C/W
Maximum Power Dissipation 70 mW
16-Lead LFCSP 67.154 °C/W
Maximum Power Dissipation 70 mW

ESD CAUTION

Rev. A | Page 5 of 36

ADP5585 Data Sheet

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

A

B

C

D

BALL A1
CORNER

1

VDD

R0

R4

234

SDA

SCL

INT

RST/R5

C1R2

R1

C3

R3

TOP VIEW

(BALL SIDE DOW N)

Not to Scale

GND

C0

C2

C4

INT

16

1

R4

2

R3

3

R2

4

R1

5

R0

TOP VIEW

Not to Scale

NOTES

1. THE EXPOSED PAD IS NOT CONNECTED.
IT IS RE COMMENDED TO CONNECT THE
EXPOSED PAD TO GROUND FOR THERMAL

09841-003

DISSIPATION.

GND

SDA

SCL

13

14

15

VDD

12

11

RST(R5)

10

C4

9

C3

8

7

6

C0

C1

C2

09841-027

Figure 3. WLCSP Pin Configuration Figure 4. LFCSP Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

WLCSP LFCSP Mnemonic Description

D1 1 R4 GPIO 5 (GPIO Alternate Function: RESET1). This pin functions as Row 4 when used as a keypad.
D2 2 R3

GPIO 4 (GPIO Alternate Function: Logic Block Input LC, PWM_OUT). This pin functions as Row 3
when used as a keypad.

C1 3 R2

GPIO 3 (GPIO Alternate Function: Logic Block Input LB). This pin functions as Row 2 when used as a
keypad.

C2 4 R1

GPIO 2 (GPIO Alternate Function: Logic Block Input LA). This pin functions as Row 1 when used as a
keypad.

B1 5 R0

GPIO 1 (GPIO Alternate Function: Logic Block Output LY). This pin functions as Row 0 when used as a

keypad.
B4 6 C0 GPIO 7. This pin functions as Column 0 when used as a keypad.
C3 7 C1 GPIO 8. This pin functions as Column 1 when used as a keypad.
C4 8 C2 GPIO 9. This pin functions as Column 2 when used as a keypad.
D3 9 C3 GPIO 10 (GPIO Alternate Function: PWM_IN). This pin functions as Column 3 when used as a keypad.
D4 10 C4 GPIO 11 (GPIO Alternate Function: RESET2). This pin functions as Column 4 when used as a keypad.
B3 11

/R5 Input Reset Signal. To expand the keypad matrix, select the ADP5585ACBZ-01-R7 or the

RST

ADP5585ACPZ-01-R7 device model for this pin to function as GPIO 6/Row 5.
A1 12 VDD Supply Voltage Input.
A4 13 GND Ground.
A2 14 SDA I2C Data Input/Output.
A3 15 SCL I2C Clock Input.
B2 16

INT

EP EP

Open-Drain Interrupt Output.

Exposed Pad. The exposed pad is not connected. It is recommended to connect the exposed pad to

ground for thermal dissipation.

Rev. A | Page 6 of 36

Data Sheet ADP5585

V

THEORY OF OPERATION

ADP5585

RST/R5

SDA

SCL

R0

R1

R2

R3

R4

C0

C1

C2

C3

C4

I/O

CONFIGURATION

UVLO

POR

(R0)
(R1)
(R2)
(R3)
(R4)

(RST/R5 )

(C0)
(C1)
(C2)
(C3)
(C4)

(R0)
(R1)
(R2)
(R3)
(R4)
(RST/R5 )

(C0)
(C1)
(C2)
(C3)
(C4)

(R1)
(R2)
(R3)

(R0)

(C3)

(R3)

DD

I2C INTERFACE

ROW 0
ROW 1
ROW 2
ROW 3
ROW 4
ROW 5

COL 0
COL 1
COL 2
COL 3
COL 4

GPIO 1
GPIO 2
GPIO 3
GPIO 4
GPIO 5
GPIO 6

GPIO 7
GPIO 8

GPIO 9
GPIO 10
GPIO 11

LA
LB
LC

LY

PWM_IN

PWM_OUT

OSCILLATOR

KEY SCAN

AND

DECODE

GPI SCAN

AND

DECODE

LOGIC

PWM

2

I

C BUSY?

KEY EVENT

GPI EVENT

LOGIC EVENT

GND

FIFO

UPDATE

INT

REGISTERS

(R4)

RESET1

(C4)

RESET2

RESET1

GEN

RESET2

GEN

RST (R5)

09841-004

Figure 5. Internal Block Diagram

Rev. A | Page 7 of 36

ADP5585 Data Sheet

V

DEVICE ENABLE

When sufficient voltage is applied to VDD and the
driven with a logic high level, the ADP5585 starts up in standby
mode with all settings at default. The user can configure the
device via the I

2

C interface. When the

RST

pin is low, the

ADP5585 enters a reset state and all settings return to default.

RST

The

pin features a debounce filter.

If using the ADP5585ACBZ-01-R7 or ADP5585ACPZ-01-R7
device model, the

RST

pin acts as an extra row pin. Without a
reset pin, the only method to reset the device is by bringing
VDD below the UVLO threshold.

RST

pin is

DEVICE OVERVIEW

The ADP5585 contains 10 multiconfigurable input/output pins.
Each pin can be programmed to enable the device to carry out
its various functions, as follows:

• Keypad matrix decoding (five-column by five-row matrix

maximum).

• General-purpose I/O expansion (up to 10 inputs/outputs).

• PWM generation.

• Logic function building blocks (up to three inputs and one

output).

• Two reset g e n e r at o r s .

All 10 input/output pins have an I/O structure as shown in
Figure 6.

DD

100kΩ

300kΩ

I/O

DRIVE

Figure 6. I/O Structure

300kΩ

DEBOUNCE

I/O

09841-005

Each I/O can be pulled up with a 100 k or 300 k resistor or
pulled down with a 300 k resistor. For logic output drive, each
I/O has a 5 mA PMOS source and a 10 mA NMOS sink for a push­pull type output. For open-drain output situations, the 5 mA
PMOS source is not enabled. For logic input applications, each
I/O can be sampled directly or, alternatively, sampled through a
debounce filter.

The I/O structure shown in Figure 6 allows for all GPI and GPO
functions, as well as PWM and clock divide functions. For key
matrix scan and decode, the scanning circuit uses the 100 k or
300 k resistor for pulling up keypad row pins and the 10 mA
NMOS sinks for grounding keypad column pins (see the Key
Scan Control section for details about key decoding).

Configuration of the device is carried out by programming an
array of internal registers via the I

2

C interface. Feedback of
device status and pending interrupts can be flagged to an
external processor by using the

INT

pin.

The ADP5585 is offered with three feature sets. Tab le 5 lists the
options that are available for each model of the ADP5585.

Table 5. Matrix Options by Device Model

Model Description

ADP5585ACBZ-00-R7 GPIO pull up (default option)
5-row × 5-column matrix
ADP5585ACBZ-01-R7 Row 5 added to GPIOs
6-row × 5-column matrix
ADP5585ACBZ-02-R7

No pull-up resistors to special function

1

pins
5-row × 5-column matrix
ADP5585ACPZ-00-R7 GPIO pull up (default option)
5-row × 5-column matrix
ADP5585ACPZ-01-R7 Row 5 added to GPIOs
6-row × 5-column matrix
ADP5585ACPZ-03-R7 Alternate I2C address (0x30)
5-row × 5-column matrix

1

Special function pins are defined as R0, R3, R4, and C4. See Table 4 for

details.

Rev. A | Page 8 of 36

Data Sheet ADP5585

FUNCTIONAL DESCRIPTION

EVENT FIFO

Before going into detail on the various ADP5585 blocks, it is
important to understand the function of the event FIFO. The
ADP5585 features an event FIFO that can record as many as 16
events. By default, the FIFO primarily records key events, such as
key press and key release. However, it is possible to configure
the general-purpose input (GPI) and logic activity to generate
event information on the FIFO as well. An event count, EC[4:0],
is composed of five bits and works in tandem with the FIFO so
that the user knows how much of the FIFO must be read back at
any given time.

The FIFO is composed of 16 eight-bit sections that the user
accesses by reading the FIFO_x registers. The actual FIFO is
not in user accessible registers until a read occurs. The FIFO
can be thought of as a “first in first out” buffer that is used to
fill Register 0x03 to Register 0x12.

The event FIFO is made up of 16 eight-bit registers. In each
register, Bits[6:0] hold the event identifier, and Bit 7 holds the
event state. With seven bits, 127 different events can be identified.
See Tab le 1 1 for event decoding.

OVRFLOW_INT

KEY EVENTS

GPI EVENTS

LOGIC EVENTS

When events are available on the FIFO, the user should first
read back the event count, EC[4:0], to determine how many
events must be read back. Events can be read from the top of
the FIFO only. When an event is read back, all remaining events
in the FIFO are shifted up one location, and the EC[4:0] count
is decremented.

FIFO

UPDATE

EVENT1[7:0]

EVENT2[7:0]

EVENT3[7:0]

EVENT4[7:0]

EVENT5[7:0]

EVENT6[7:0]

EVENT7[7:0]

EVENT8[7:0]

EVENT9[7:0]

EVENT10[7:0]

EVENT11[7:0]

EVENT12[7:0]

EVENT13[7:0]

EVENT14[7:0]

EVENT15[7:0]

EVENT16[7:0]

Figure 7. Breakdown of Eventx[7:0] Bits

EC[4:0]

7

6543210

EVENT 8_IDENTIFIER[6:0]

EVENT8_STATE

FIRST
READ

The FIFO registers (0x03 to 0x12) always point to the top of the
FIFO (that is, the location of EVENT1[7:0]). If the user tries to
read back from any location in a FIFO, data is always obtained
from the top of that FIFO. This ensures that events can only be
read back in the order in which they occurred, thus ensuring
the integrity of the FIFO system.

As stated above, some of the onboard functions of ADP5585
can be programmed to generate events on the FIFO. A FIFO
update control block manages updates to the FIFO. If an I
transaction is accessing any of the FIFO address locations,
updates are paused until the I

A FIFO overflow event occurs when more than 16 events are
generated prior to an external processor reading a FIFO and
clearing it.

If an overflow condition occurs, the overflow status bit is set.
An interrupt is generated if overflow interrupt is enabled,
signaling to the processor that more than 16 events have
occurred.

KEY SCAN CONTROL

General

The 10 input/output pins can be configured to decode a keypad

09841-006

matrix up to a maximum size of 25 switches (5 × 5 matrix). Smaller
matrices can also be configured, freeing up the unused row and
column pins for other I/O functions.

The R0 through R4 I/O pins comprise the rows of the keypad
matrix. The C0 through C4 I/O pins comprise the columns of
the keypad matrix. Pins used as rows are pulled up via the internal
300 k (or 100 k) resistors. Pins used as columns are driven
low via the internal NMOS current sink.

EC = 3

KEY 3 PRESSED

KEY 3 RELEASED

GPI 7 ACTIVE

SECOND

READ

EC = 2

KEY 3 RELEASED

GPI 7 ACTIVE

THIRD

READ

Figure 8. FIFO Operation

2

C transaction has completed.

EC = 1

GPI 7 ACTIVE

EC = 0

2

C

09841-007

Rev. A | Page 9 of 36

ADP5585 Data Sheet

VDD

KEY

SCAN

CONTROL

R0 R1 R2C2C0 C1

1

23

4

56

7

89

3 × 3 KEYPAD MATRIX

09841-008

Figure 9. Simplified Key Scan Block

Figure 9 shows a simplified representation of the key scan block
using three row and three column pins connected to a small 3 × 3,
nine-switch keypad matrix. When the key scanner is idle, the
row pins are pulled high and the column pins are driven low.
The key scanner operates by checking the row pins to see if they
are low.

If Switch 6 in the matrix is pressed, R1 connects to C2. The key
scan circuit senses that one of the row pins has been pulled low,
and a key scan cycle begins. Key scanning involves driving all
column pins high, then driving each column pin, one at a time,

PIN_CON FIG_A[7:0]
PIN_CON FIG_B[7:0]
PIN_CON FIG_C[7:0]

RESET_TRIG_TIME[2:0]

RESET1_EVENT_A[7:0]
RESET1_EVENT_B[7:0]
RESET1_EVENT_C[7:0]
RESET2_EVENT_A[7:0]
RESET2_EVENT_B[7:0]

KEY SCAN
CONTROL

low and sensing whether a row pin is low or not. All row/column
pairs are scanned; therefore, if multiple keys are pressed, they
are detected.

To prevent glitches or narrow press times being registered as a
valid key press, the key scanner requires the key be pressed for
two scan cycles. The key scanner has a wait time between each
scan cycle; therefore, the key must be pressed and held for at
least this wait time to register as being pressed. If the key is
continuously pressed, the key scanner continues to scan, wait,
scan, wait, and so forth.

If Switch 6 is released, the connection between R1 and C2
breaks, and R1 is pulled up high. The key scanner requires that
the key be released for two scan cycles because the release of a
key is not necessarily in sync with the key scanner, it may take
up to two full wait/scan cycles for a key to register as released.
When the key is registered as released, and no other keys are
pressed, the key scanner returns to idle mode.

For the remainder of this document, the press/release status of a
key is represented as simply a logic signal in the figures. A logic
high level represents the key status as pressed, and a logic low
represents released. This eliminates the need to draw individual
row/column signals when describing key events.

KEY PRESSED

KEY x KEY RELEASED KEY RELEASED

Figure 10. Logic Low: Released, Logic High: Pressed

Figure 11 shows a detailed representation of the key scan block
and its associated control and status signals. When all row and
column pins are used, a matrix of 25 unique keys can be
scanned.

RESET 1_INITIATE
RESET 2_INITIATE

EVENT_INT

2

C BUSY?

I

KEY EVENT

GPI EVENT

LOGIC EVENT

FIFO

UPDATE

OVRFLOW_INT

EC[4:0]

9841-009

COLUMN

SINK ON/OF F

I/O CONF IGURATION

31

32

33

34

35

36

ROW

SENSE

R0 R3R1 R2 R4 R5C0 C1 C2 C3 C4

54321

109876

1514131211

2019181716

2524232221

3029282726

FIFO

09841-010

Figure 11. Detailed Key Scan Block

Rev. A | Page 10 of 36

Data Sheet ADP5585

Use Registers PIN_CONFIG_A[7:0] and PIN_CONFIG_B[7:0]
to configure I/Os for keypad decoding. The number label on
each key switch represents the event identifier that is recorded
if that switch was pressed. If all row/column pins are config­ured, it is possible to observe all 25 key identifiers on the
FIFO. A larger 6 × 5 matrix can be configured by using the
ADP5585ACBZ-01-R7 or the ADP5585ACPZ-01-R7.

If a smaller 2 × 2 matrix is configured, for example, by using the
C2 and C3 column pins and the R1 and R2 row pins, only the
four event identifiers (8, 9, 13, and 14) can possibly be observed
on the FIFO, as shown in Figure 11.

By default, ADP5585 records key presses and releases on the
FIFO. Figure 12 illustrates what happens when a single key is
pressed and released. Initially, the key scanner is idle. When
Key 3 is pressed, the scanner begins scanning through all
configured row/column pairs. After the scan wait time, the
scanner again scans through all configured row/column pairs
and detects that Key 3 has remained pressed, which sets the
EVENT_INT interrupt. The event counter, EC[4:0], is incre­mented to 1, EVENT1_IDENTIFIER[6:0] of the FIFO is
updated with its event identifier set to 3, and its
EVENT1_STATE bit is set to 1, indicating a press.

KEY 3

KEY SCAN

EVENT_INT

EC[4:0]

KEY 3 PRESS

KEY 3 RELEASE

1 2

FIFO
1

3

0

3

0

0

0

0

Figure 12. Press and Release Event

The key scanner continues the scan/wait cycles while the key
remains pressed. If the scanner detects that the key has been
released for two consecutive scan cycles, the event counter,
EC[4:0], is incremented to 2, and EVENT2_IDENTIFIER[6:0]
of the FIFO is updated with its event identifier set to 3. Its
EVENT2_STATE bit is set to 0, indicating a release. The key
scanner returns to idle mode because no other keys are pressed.

The EVENT_INT interrupt can be triggered by both press and
release key events. As shown in Figure 14, if Key 3 is pressed,
EVENT_INT is asserted, EC[4:0] is updated, and the FIFO is
updated. During the time that the key remains pressed, it is
possible for the FIFO to be read, the event counter decremented
to 0, and EVENT_INT cleared. When the key is finally released,
EVENT_INT is asserted, the event counter is incremented, and
the FIFO is updated with the release event information.

KEY 3

KEY SCAN

EVENT_INT

EC[4:0]

KEY 3 PRESS KEY 32 RELEASE

101

FIFO

3

1

0

0

0

0

FIFO

READ

0

0

EVENT_INT CLEARED

FIFO

0

0

0

0

0

0

0

0

FIFO
0
0
0
0

3
0
0
0

09841-012

Figure 13. Asserting the EVENT_INT Interrupt Key Pad Extension

As shown in Figure 11, the keypad can be extended if each row
is connected directly to ground by a switch. If the switch placed
between R0 and ground is pressed, the entire row is grounded.
When the key scanner completes scanning, it normally detects
Key 1 to Key 5 as being pressed; however, this unique condition
is decoded by the ADP5585, and Key Event 31 is assigned to it.
Up to eight more key event assignments are possible, allowing the
keypad size to extend up to 30. However, if one of the extended
keys is pressed, none of the keys on that row is detectable.
Activation of a ground key causes all other keys sharing that
row to be undetectable.

Ghosting

Ghosting is an occurrence where, given certain key press com­binations on a keypad matrix, a false positive reading of an
additional key is detected. Ghosting is created when three or
more keys are pressed simultaneously on multiple rows or
columns (see Figure 14). Key combinations that form a right
angle on the keypad matrix can cause ghosting.

The solution to ghosting is to select a keypad matrix layout that
takes into account three key combinations that are most likely
to be pressed together. Multiple keys pressed across one row or

09841-011

across one column do not cause ghosting. Staggering keys so that
they do not share a column also avoids ghosting. The most
common practice is to place keys that are likely to be pressed
together in the same row or column. Some examples of keys
that are likely to be pressed together are as follows:

• The navigation keys in combination with Select.

• The navigation keys in combination with the space bar.

• The reset combination keys, such as CTRL + ALT + DEL.

COL0

ROW0

ROW1

ROW2

ROW3

PRESS

GHOST

Figure 14. COL0: ROW3 is a Ghost Key Due to a Short Among ROW0, COL0,

COL2, and ROW3 During Key Press

COL1 COL2

PRESS

PRESS

09841-013

Rev. A | Page 11 of 36