ANALOG DEVICES ADP5043 Service Manual

Micro PMU with 800 mA Buck, 300 mA LDO,

Supervisory, Watchdog, and Manual Reset

ADP5043

Rev. A

rights of third parties that may result from its use. Specifications subject to change without notice. No

Tra demarks and registered trademarks a re the property of their respec tive owners.

VIN

WD1 MODE SELECTION

FPWM

PSM/PWM

MODE

SW VOUT1 PGND

C6 10µF

L1

1µH

EN_BK

BUCK

EN_LDO

LDO

VIN1

EN1

VIN2

EN2

C2 1µF

VOUT2

GND GND

C5

4.7µF

ON

OFF

ON

OFF

NC

VIN1 = 2.3V

TO 5.5V

AVIN

R

FILT

30Ω

VIN2 = 1.7V

TO 5.5V

MR

C1

1µF

MICROPROCESSOR

SUPERVISOR

WSTAT

WMOD

WDI1 WDI2

nRSTO

NC

AGND

AVIN

ADP5043

V

OUT1

@

800mA

V

OUT2

@

300mA

09682-001

Data Sheet

FEATURES

Input voltage range: 2.3 V to 5.5 V One 800 mA buck regulator One 300 mA LDO 20-lead, 4 mm × 4 mm LFCSP package Initial regulator accuracy: ±1% Overcurrent and thermal protection Soft start Undervoltage lockout Open-drain processor reset with threshold monitoring ±1.5% threshold accuracy over the full temperate range Guaranteed reset output valid to V Dual watchdog for secure systems

Watchdog 1 controls reset Watchdog 2 controls reset and regulators power cycle

Buck regulator key specifications

Current-mode topology for excellent transient response 3 MHz operating frequency Uses tiny multilayer inductors and capacitors Mode pin selects forced PWM or auto PFM/PSM modes 100% duty cycle low dropout mode

LDO key specifications

Low V

from 1.7 V to 5.5 V

IN

Stable with1 µF ceramic output capacitors High PSRR, 60 dB up to 1 kHz/10 kHz Low output noise Low dropout voltage: 150 mV at 300 mA load

−40°C to +125°C junction temperature range

= 1 V

CC

GENERAL DESCRIPTION

The ADP5043 combines one high performance buck regulator and one low dropout regulator (LDO) in a small 20-lead LFCSP to meet demanding performance and board space requirements.

The high switching frequency of the buck regulator enables use of tiny multilayer external components and minimizes board space.

The MODE pin selects the buck’s mode of operation. When set to logic high, the buck regulator operates in forced PWM mode. When the MODE pin is set to logic low, the buck regulator operates in PWM mode when the load is around the nominal value. When the load current falls below a predefined threshold, the regulator operates in power save mode (PSM) improving the light-load efficiency.

The low quiescent current, low dropout voltage, and wide input voltage range of the ADP5043 LDO extend the battery life of portable devices. The LDO maintains a power supply rejection of greater than 60 dB for frequencies as high as 10 kHz while operating with a low headroom voltage.

Each regulator is activated by a high level on the respective enable pin. The ADP5043 is available with factory programmable default output voltages and can be set to a wide range of options.

The ADP5043 contains supervisory circuits that monitor power supply voltage levels and code execution integrity in microprocessor-based systems. The ADP5043 also provides power-on reset signals. An on-chip dual watchdog timer can reset the microprocessor or power cycle the system (Watchdog 2) if it fails to strobe within a preset timeout period.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

HIGH LEVEL BLOCK DIAGRAM

Figure 1.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com

ADP5043 Data Sheet

REVISION HISTORY

10/11—Rev. 0 to Re v. A

Updated Outline Dimensions ....................................................... 30

Changes to Ordering Guide .......................................................... 30

11—Revision 0: Initial Version

4/

Rev. A | Page 2 of 32

Data Sheet ADP5043

Option A

2.25

V

mV

SPECIFICATIONS

GENERAL SPECIFICATIONS

AVIN, VIN1 = (V are enabled.

Table 1.

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

AVIN UNDERVOLTAGE LOCKOUT UVLO

Input Voltage Rising UVLO

Option B 3.9 V

Input Voltage Falling UVLO

Option A 1.95 V

Option B 3.1 V SHUTDOWN CURRENT I ENx = GND, TJ = −40°C to +125°C 2 µA

Thermal Shutdown Threshold TSSD TJ rising 150 °C Thermal Shutdown Hysteresis TS

ENx, WDIx, MODE, WMOD,

Input Logic High VIH 2.5 V ≤ AVIN ≤ 5.5 V 1.2 V Input Logic Low VIL 2.5 V ≤ AVIN ≤ 5.5 V 0.4 V Input Leakage Current (WMOD Excluded) V ENx = AVIN or GND, TJ = −40°C to +125°C 1 µA WMOD Input Leakage Current V

OPEN-DRAIN OUTPUTS

nRSTO, WSTAT Output Voltage VOL AVIN = 2.3 V to 5.5 V, I Open-Drain Reset Output Leakage Current 1 µA

+ 0.5 V) or 2.3 V, whichever is greater, AVIN, VIN1 ≥ VIN2, TA = 25°C, unless otherwise noted. Regulators

OUT1

TJ = −40°C to +125°C

AVIN

AVINRISE

AVI NFAL L

ENx = GND 0.1 µA

GND-SD

20 °C

SD-HYS

MR

INPUTS

ENx = AVIN or GND 0.05 µA

I-LEAKAGE

I-LKG-WMOD

VWMOD = 3.6 V, TJ = −40°C to +125°C 50 µA

nRSTO/WSTAT

= 3 mA 30

SUPERVISORY SPECIFICATIONS

AVIN, VIN1 = full operating range, TJ = −40°C to +125°C, unless otherwise noted.

Table 2.

Parameter Min Typ Max Unit Test Conditions/Comments

SUPPLY

Supply Current (Supervisory Circuit Only) 45 55 µA AVIN = 5.5 V, EN1 = EN2 = VIN1 43 52 µA AVIN = 3.6 V, EN1 = EN2 = VIN1 RESET THRESHOLD ACCURACY VTH − 0.8% VTH VTH + 0.8% V TA = 25°C, sensed on VOUTx VTH − 1.5% VTH VTH + 1.5% V TJ = −40°C to +125°C, sensed on V RESET THRESHOLD TO OUTPUT DELAY

GLITCH IMMUNITY (t

UOD

)

RESET TIMEOUT PERIOD WATCHDOG1 (t

RP1

50 125 400 µs VTH = V

) Option A 24 30 36 ms Option B 160 200 240 ms

RESET TIMEOUT PERIOD WATCHDOG2 (t

) 3.5 5 7 ms

RP2

VCC TO RESET DELAY (tRD) 150 µs VIN1 falling at 1 mV/µs REGULATORS SEQUENCING DELAY (tD1, tD2) 2 ms WATCHDOG INPUTS

Watchdog 1 Timeout Period (t

)

WD1

Option A 81.6 102 122.4 ms Option B 1.28 1.6 1.92 sec

− 50 mV

OUT

OUTx

Rev. A | Page 3 of 32

ADP5043 Data Sheet

Option D

6.4 8 9.6

min

Option A

210 ms

MANUAL RESET INPUT

Parameter Min Typ Max Unit Test Conditions/Comments

Watchdog 2 Timeout Period (t

Option A 6 7.5 9 sec Option B Watchdog 2 disabled Option C 3.2 4 4.8 min

Option E 11.2 16 19.2 min Option F 25.6 32 38.4 min Option G 51.2 64 76.8 min Option H 102.4 128 153.8 min

Watchdog 2 Power Off Period (t

Option B 400 ms WDI1 Pulse Width 80 ns VIL = 0.4 V, VIH = 1.2 V WDI2 Pulse Width 8 µs VIL = 0.4 V, VIH = 1.2 V Watchdog Status Timeout Period (t WDI1 Input Current (Source) 8 15 20 µA V WDI1 Input Current (Sink) −30 −25 −14 µA V WDI2 Internal Pull-Down 45 kΩ

)

WD2

)

POFF

) 11.2 sec

WDCLEAR

= VCC, time average

WDI1

= 0, time average

WDI1

MR Input Pulse Width MR Glitch Rejection MR Pull-Up Resistance MR to Reset Delay

1 µs 220 ns 25 52 80 kΩ 280 ns V

= 5 V

CC

Rev. A | Page 4 of 32

Data Sheet ADP5043

NFET, AVIN = VIN1 = 5 V

150

210

mΩ

OPERATING SUPPLY CURRENT (per LDO)

I

= 0 µA, VOUT = 3.3 V

15 µA

100 µA < I

< 300 mA

−2 +2

%

BUCK SPECIFICATIONS

AVIN, VIN1 = 3.6 V, V

for typical specifications, unless otherwise noted.

Table 3.

Parameter Test Conditions/Comments Min Ty p Max Unit

INPUT CHARACTERISTICS

Input Voltage Range (VIN1) 2.3 5.5 V

OUTPUT CHARACTERISTICS

Output Voltage Accuracy PWM mode, I

PSM mode −2 +2 %

PWM TO POWER SAVE MODE CURRENT THRESHOLD 100 mA INPUT CURRENT CHARACTERISTICS

DC Operating Current I Shutdown Current ENx = 0 V, TA = TJ = −40°C to +125°C 0.2 1.0 μA

SW CHARACTERISTICS

SW On Resistance PFET 180 240 mΩ PFET, AVIN = VIN1 = 5 V 140 190 mΩ

NFET 170 235 mΩ

= 1.8 V, TJ = −40°C to +125°C for minimum/maximum specifications, L = 1 µH, C

OUT1

1

= 100 mA −1 +1 %

LOAD

VIN1 = 2.3 V to 5.5 V, PWM mode,

= 1 mA to 800 mA

I

LOAD

= 0 mA, device not switching 21 35 μA

LOAD

−3 +3 %

= 10 µF, and TA = 25°C

OUT

Current Limit PFET switch peak current limit 1100 1360 1600 mA ACTIVE PULL-DOWN EN1 = 0 V 75 Ω OSCILLATOR FREQUENCY 2.5 3.0 3.5 MHz STA RT-UP TIME 250 μs

1

All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).

LDO SPECIFICATIONS

AVIN = 3.6 V, VIN2 = (VOUT2 + 0.2 V) or 2.3 V, whichever is greater; AVIN, VIN1 ≥ VIN2; I T

= 25°C, unless otherwise noted.

A

Table 4.

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

INPUT VOLTAGE RANGE V

I I I I FIXED OUTPUT VOLTAGE ACCURACY V

TJ = −40°C to +125°C 1.7 5.5 V

IN2

GND

I

OUT2

OUT

= 0 µA, VOUT = 3.3 V,

I

OUT

= −40°C to +125°C

T

J

= 10 mA 67 µA

OUT

= 10 mA, TJ = −40°C to +125°C 105 µA

OUT

= 200 mA 100 µA

OUT

= 200 mA, TJ = −40°C to +125°C 245 µA

OUT

= 10 mA −1 +1 %

OUT

VIN2 = (VOUT2 + 0.5 V) to 5.5 V 100 µA < I

< 300 mA −3 +3 %

OUT

VIN2 = (VOUT2 + 0.5 V) to 5.5 V TJ = −40°C to +125°C

= 10 mA; CIN = C

OUT

= 1 µF;

OUT

50 µA

Rev. A | Page 5 of 32

ADP5043 Data Sheet

Load Regulation1

∆V

/∆I

= 1 mA to 200 mA

0.002

%/mA

DROPOUT VOLTAGE2

V

VOUT2 = 3.3 V

CAPACITOR ESR

R

TJ = −40°C to +125°C

0.001

1 Ω

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

REGULATION

Line Regulation ∆V I TJ = −40°C to +125°C

I TJ = −40°C to +125°C

I I I

I ACTIVE PULL-DOWN R STA RT-UP TIME T CURRENT-LIMIT THRESHOLD3 I OUTPUT NOISE OUT

POWER SUPPLY REJECTION RATIO PSRR

1

Based on an end-point calculation using 1 mA and 100 mA loads.

2

Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output

voltages above 2.3 V.

3

Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V

output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V.

/∆V

OUT2

DROPOUT

EN2 = 0 V 600 Ω

PDLDO

VOUT2 = 3.3 V 85 µs

STA RT-UP

TJ = −40°C to +125°C 335 470 mA

LIMIT

LDONOISE

VIN2= (VOUT2 + 0.5 V) to 5.5 V −0.03 +0.03 %/V

IN2

= 1 mA

OUT2

OUT2 IOUT2

= 1 mA to 200 mA 0.0075 %/mA

OUT2

= 10 mA 4 mV

OUT2

= 10 mA, TJ = −40°C to +125°C 5 mV

OUT2

= 200 mA 60 mV

OUT2

= 200 mA, TJ = −40°C to +125°C 100 mV

OUT2

10 Hz to 100 kHz, VIN2 = 5 V,

123 µV rms

VOUT2 = 3.3 V 10 Hz to 100 kHz, VIN2 = 5 V,

110 µV rms

VOUT2 = 2.8 V 10 Hz to 100 kHz, VIN2 = 5 V,

59 µV rms

VOUT2 = 1.5 V 1 kHz, VIN2 = 3.3 V, VOUT2 = 2.8 V,

I

= 100 mA

OUT

100 kHz, VIN2 = 3.3 V, VOUT2 = 2.8 V,

= 100 mA

I

OUT

1 MHz, VIN2 = 3.3 V, VOU T2 = 2.8 V,

= 100 mA

I

OUT

66 dB

57 dB

60 dB

INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS

Table 5.

Parameter Symbol Test Conditions/Comments Min Ty p Max Unit

OUTPUT CAPACITANCE (BUCK)1 C MINIMUM INPUT AND OUTPUT CAPACITANCE2 (LDO) C

1

The minimum output capacitance should be greater than 4.7 µF over the full range of operating conditions. The full range of operating conditions in the application

must be considered during device selection to ensure that the minimum capacitance specification is met.

2

The minimum input and output capacitance should be greater than 0.70 µF over the full range of operating conditions. The full range of operating conditions in the

application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended, Y5V and Z5U capacitors are not recommended for use with LDOs or the buck.

TJ = −40°C to +125°C 7 40 µF

MIN1

TJ = −40°C to +125°C 0.70 µF

MIN2

ESR

Rev. A | Page 6 of 32

Data Sheet ADP5043

ESD Machine Model

100 V

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter Rating

AVIN, VINx, VOUTx, ENx, MODE, MR, WDIx, WMOD, WSTAT, nRSTO to GND

Storage Temperature Range −65°C to +150°C Operating Junction Temperature Range −40°C to +125°C Soldering Conditions JEDEC J-STD-020 ESD Human Body Model 3000 V ESD Charged Device Model 1500 V

−0.3 V to +6 V

Junction-to-ambient thermal resistance (θ based on modeling and calculation using a 4-layer board. The junction-to-ambient thermal resistance is highly dependent on the application and board layout. In applications where high maximum power dissipation exists, close attention to thermal board design is required. The value of θ PCB material, layout, and environmental conditions. The specified value of θ

is based on a four-layer, 4” × 3”, 2.5 oz copper board,

JA

as per JEDEC standard. For additional information, see the

AN-772 Application Note, A Design and Manufacturing Guide

for the Lead Frame Chip Scale (LFCSP).

) of the package is

JA

may vary, depending on

JA

Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL DATA

Absolute maximum ratings apply individually only, not in combination.

The ADP5043 can be damaged when the junction temperature limits are exceeded. Monitoring ambient temperature does not guarantee that the junction temperature is within the specified temperature limits. In applications with high power dissipation and poor thermal resistance, the maximum ambient temperature may have to be derated. In applications with moderate power dissipation and low PCB thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. The junction temperature of the device is dependent on the ambient temperature, the power dissipation of the device (P junction-to-ambient thermal resistance of the package. Maximum junction temperature is calculated from the ambient temperature and power dissipation using the formula

T

= TA + (PD × θJA)

J

), and the

D

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.

Table 7. Thermal Resistance

Package Type θJA θJC Unit

20-Lead, 0.5 mm pitch LFCSP 38 4.2 °C/W

ESD CAUTION

Rev. A | Page 7 of 32

ADP5043 Data Sheet

NOTES

1. EXPOS E D P AD S HOULD BE CONNECT E D TO AGND.

2. NC = NO CONNECT. DO NOT CONNECT T O THIS PIN. THE PIN SHOULD BE LEFT FLOATING.

14 13 12

1

3 4

NC

15

WSTAT

GND WDI2

11

VOUT1

NC

VIN2

2

VOUT2

EN2

5

nRSTO

7

VIN1

6

AVIN

8

SW

9

PGND

10 EN1

19

WDI1

20

18 WMOD

17

MODE

16

GND

ADP5043

MR

TOP VIEW

(Not to S cale)

09682-002

5

nRSTO

Open-Drain Reset Output, Active Low.

11

VOUT1

Buck Sensing Node.

19

WDI1

Watchdog 1 Refresh Input from Processor. If WDI1 is in high-Z and WMOD is low, Watchdog 1 is disabled.

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 2. Pin Configuration

Table 8. Pin Function Descriptions

Pin No. Mnemonic Description

1 NC Do not connect to this pin. The pin should be left floating. 2 VOUT2 LDO Output Voltage and Sensing Input. 3 VIN2 LDO Input Supply (1.7 V to 5.5 V). 4 EN2 Enable LDO. EN2 = high: turn on the LDO; EN2 = low: turn off the LDO.

6 AVIN Regulators Housekeeping and Supervisory Input Supply (2.3 V to 5.5 V). 7 VIN1 Buck Input Supply (2.3 V to 5.5 V). 8 SW Buck Switching Node. 9 PGND Dedicated Power Ground for Buck Regulator. 10 EN1 Enable Buck. EN1 = high: turn on buck; EN1 = low: turn off buck.

12 WDI2 Watchdog 2 (Long Timeout) Refresh Input from Processor. This pin can be disabled only by a factory option. 13 GND Connect to the ground plane. 14 NC Do not connect to this pin. The pin should be left floating. 15 WS TAT

Open-Drain Watchdog Timeout Status. WSTAT = high: Watchdog 1 timeout or power-on reset; WSTAT = low:

Watchdog 2 timeout. Auto cleared after one second. 16 GND Connect to the ground plane. 17 MODE

Buck Mode. MODE = high: buck regulator operates in fixed PWM mode; MODE = low: (auto mode) buck

regulator operates in power save mode (PSM) at light load and in constant PWM at higher load. 18 WMOD

Watchdog Mode. WMOD = low: Watchdog 1 normal mode; WMOD = high: Watchdog 1 cannot be disabled by a

three-state condition applied on WDI1. WMOD has an internal 200 kΩ pull-down resistor connected to AGND.

20

MR

Manual Reset Input, Active Low. TP AGND Analog Ground (TP = Exposed Thermal Pad). Exposed pad should be connected to AGND.

Rev. A | Page 8 of 32

Data Sheet ADP5043

CH1 2.0V/DIV 1MΩ

B

W

20.0M

CH2 2.0V/DIV 1MΩ

B

W

20.0M

A CH1 1.76V 200µs/DIV

20.0ns/pt

1

2

VOUT1

VOUT2

09682-003

0

0.1

0.2

0.3

0.4

0.5

0.6

1.0

0.9

0.8

0.7

2.3 2.8 3.3 3.8 4.3 4.8 5.3

SYSTEM QUIESCENT CURRE NT (mA)

INPUT VOLTAGE (V)

V

OUT1

= 1.5V,

V

OUT2

= 3.3V

09682-004

CH1 2.0V/DIV 1MΩ

B

W

20.0M

CH2 2.0V/DIV 1MΩ

B

W

500M

CH3 100mA/DIV 1MΩ

B

W

20.0M

CH4 5.0V/DIV 1MΩ

B

W

500M

A CH1 2.92V 50µs/DIV

50.0MS/s

20.0ns/pt

2

4

1

3

SW

VOUT1

EN

IIN

09682-005

3.22

3.24

3.26

3.28

3.30

3.32

3.34

OUTPUT VOLTAGE (V)

OUTPUT CURRE NT (A)

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

+25°C

–40°C +85°C

09682-007

1.775

1.780

1.785

1.790

1.795

1.800

1.805

1.810

1.815

1.820

1.825

1.830

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

OUTPUT CURRE NT (A)

OUTPUT VOLTAGE (V)

+25°C

–40°C +85°C

09682-008

1.784

1.785

1.786

1.787

1.788

1.789

1.790

1.791

1.792

1.793

1.794

1.795

0 0.

1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

–40°C

+25

°C

+85°C

OUTPUT CURRE NT (A)

OUTPUT VOLTAGE (V)

09682-009

TYPICAL PERFORMANCE CHARACTERISTICS

VIN1 = VIN2 = AVIN = 5.0 V, TA = 25°C, unless otherwise noted.

Figure 3. 3-Channel Start-Up Waveforms

Figure 4. System Quiescent Current (Sum of All the Input Currents) vs. Input

Voltage, V

OUT1

= 1.5 V, V

OUT2

= 3.3 V

Figure 6. Buck Load Regulation Across Temperature, V

Figure 7. Buck Load Regulation Across Temperature, V

= 3.3 V, Auto Mode

OUT1

= 1.8 V, Auto Mode

OUT1

Figure 5. Buck Startup, V

OUT1

= 1.8 V, I

OUT1

= 20 mA

Rev. A | Page 9 of 32

Figure 8. Buck Load Regulation Across Temperature, V

PWM Mode

OUT1

= 1.8 V,

ADP5043 Data Sheet

1.790

1.791

1.792

1.793

1.794

1.795

1.796

1.797

0 0.

1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

OUTPUT CURRE NT (A)

OUTPUT VOLTAGE (V)

VIN = 5.5V

VIN = 4.5V

V

IN

= 3.6V

09682-010

0

10

20

30

40

50

60

70

80

90

100

0.0001 0.001 0.01 0.1 1

EFFICIENCY (%)

OUTPUT CURRE NT (A)

3.6V

4.5V

5.5V

09682-011

0

10

20

30

40

50

60

70

80

90

100

0.001 0.01 0.1 1

EFFICIENCY (%)

OUTPUT CURRE NT (A)

3.6V

4.5V

5.5V

09682-012

0

10

20

30

40

50

60

70

80

90

100

0.0001 0.001 0.01 0.1 1

EFFICIENCY (%)

OUTPUT CURRE NT (A)

2.4V

3.6V

4.5V

5.5V

09682-013

0

10

20

30

40

50

60

70

80

90

100

0.001 0.

01 0.1 1

EFFICIENCY (%)

OUTPUT CURRE NT (A)

2.4V

3.6V

4.5V

5.5V

09682-014

0

10

20

30

40

50

60

70

80

90

100

0.001 0.01 0.1 1

EFFICIENCY (%)

OUTPUT CURRE NT (A)

+25°C

–40°C +85°C

09682-015

Figure 9. Buck Load Regulation Across Input Voltage, V

OUT1

= 1.8 V,

PWM Mode

Figure 10. Buck Efficiency vs. Load Current, Across Input Voltage,

= 3.3 V, Auto Mode

V

OUT1

Figure 12. Buck Efficiency vs. Load Current, Across Input Voltage,

= 1.8 V, Auto Mode

V

OUT1

Figure 13. Buck Efficiency vs. Load Current, Across Input Voltage,

= 1.8 V, PWM Mode

V

OUT1

Figure 11. Buck Efficiency vs. Load Current, Across Input Voltage,

= 3.3 V, PWM Mode

V

OUT1

Figure 14. Buck Efficiency vs. Load Current, Across Temperature, V

OUT1

= 1.8 V,

PWM Mode

Rev. A | Page 10 of 32

ANALOG DEVICES ADP5043 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

GENERAL DESCRIPTION

HIGH LEVEL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

GENERAL SPECIFICATIONS

SUPERVISORY SPECIFICATIONS

BUCK SPECIFICATIONS

LDO SPECIFICATIONS

INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

THERMAL DATA

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS