ANALOG DEVICES ADP5042 Service Manual

Supervisory, Watchdog and Manual Reset

ADP5042

Rev. A

rights of third parties that may result from its use. Specifications subject to change without notice. No

Trademarks and registered trademarks are the property of their respec tive owners.

FPWM

PSM/PWM

MODE

SW VOUT1 PGND

C6 10µF

V

OUT1

AT

800mA

L1

1µH

EN_BK

BUCK

EN_LDO1

LDO1

(DIGITAL)

EN_LDO2

LDO2

(ANALOG)

SUPERVISOR

MICROPROCESSOR

VIN1

EN3

AVIN

EN1

VIN2

VIN3

EN2

AGND

C2 1µF

VOUT2

VOUT3

WSTAT

WDI1 WDI2

nRSTO

V

OUT2

AT

300mA

C4 1µF

V

OUT3

AT

300mA

C5

4.7µF

ON

OFF

ON

OFF

ON

OFF

VIN1 = 2.3V

TO 5.5V

AVIN

R

FILT

= 30Ω

VIN2 = 1.7V

TO 5.5V

MR

C1

1µF

VIN3 = 1.7V

TO 5.5V

C3

1µF

08811-001

Data Sheet

FEATURES

Input voltage range: 2.3 V to 5.5 V One 0.8 A buck regulator Two 300 mA LDOs 20-lead, 4 mm × 4 mm LFCSP package Initial regulator accuracy: ±1% Overcurrent and thermal protection Soft start Undervoltage lockout Open drain processor reset with threshold monitoring ±1.5% threshold accuracy over the full temperate range Guaranteed reset output valid to V Dual watchdog for secure systems

Watchdog 1 controls reset Watchdog 2 controls reset and regulators power cycle

Buck key specifications

Current mode topology for excellent transient response 3 MHz operating frequency Uses tiny multilayer inductors and capacitors Mode pin selects forced PWM or auto PFM/PSM modes 100% duty cycle low dropout mode

LDOs key specifications

Low V

from 1.7 V to 5.5 V

IN

Stable with1 µF ceramic output capacitors High PSRR, 60 dB PSRR up to 1 kHz/10 kHz Low output noise

110 µV rms typical output noise at V

Low dropout voltage: 150 mV at 300 mA load

−40°C to +125°C junction temperature range

= 1 V

CC

= 2.8 V

OUT

Micro PMU with 0.8 A Buck, Two 300 mA LDOs

HIGH LEVEL BLOCK DIAGRAM

Figure 1.

GENERAL DESCRIPTION

The ADP5042 combines one high performance buck regulator and two low dropout regulators (LDO) in a small 20-lead LFCSP to meet demanding performance and board space requirements.

The high switching frequency of the buck regulator enables use of tiny multilayer external components and minimizes the board space.

The MODE pin selects the buck mode of operation. When set to logic high, the buck regulators operate in forced PWM mode. When the MODE pin is set to logic low, the buck regulators operate in PWM mode when the load is around the nominal value. When the load current falls below a predefined threshold the regulator operates in power save mode (PSM) improving the light-load efficiency.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringement s of patents or other

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

The low quiescent current, low dropout voltage, and wide input voltage range of the ADP5042 LDOs extend the battery life of portable devices. The two LDOs maintain power supply rejection greater than 60 dB for frequencies as high as 10 kHz while operating with a low headroom voltage.

Each regulator is activated by a high level on the respective enable pin. The ADP5042 is available with factory programmable default output voltages and can be set to a wide range of options.

The ADP5042 contains supervisory circuits that monitor power supply voltage levels and code execution integrity in microprocessor-based systems. They also provide power-on reset signals. An on-chip dual watchdog timer can reset the microprocessor or power cycle the system (Watchdog 2) if it fails to strobe within a preset timeout period.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com

ADP5042 Data Sheet

REVISION HISTORY

10/11—Rev. 0 to Rev. A

Updated Outline Dimensions ....................................................... 30

Changes to Ordering Guide .......................................................... 30

12/10—Revision 0: Initial Version

Rev. A | Page 2 of 32

Data Sheet ADP5042

Input Voltage Falling

UVLO

1.95

V

Thermal Shutdown Threshold

TSSD

TJ rising

150 °C

mV

SUPPLY

RESET THRESHOLD ACCURACY

VTH − 0.8%

VTH

VTH + 0.8%

V

TA = 25°C, sensed on VOUTx

RESET TIMEOUT PERIOD WATCHDOG2 (t

)

SPECIFICATIONS

GENERAL SPECIFICATION

AVIN, VIN1 = (V are enabled.

Table 1.

Parameter Symbol Description Min Typ Max Unit

AVIN UNDERVOLTAGE LOCKOUT UVLO

Input Voltage Rising UVLO

SHUTDOWN CURRENT I ENx = GND, TJ = −40°C to +125°C 2 µA

+ 0.5 V) or 2.3 V, whichever is greater, AVIN, VIN1 ≥ VIN2, VIN3, TA = 25°C, unless otherwise noted. Regulators

OUT1

TJ = −40°C to +125°C

AVIN

2.25 V

AVINRISE

AVIN FALL

ENx = GND 0.1 µA

GND-SD

Thermal Shutdown Hysteresis TS

ENx, WDIx, MODE, WMOD,

MR

INPUTS

20 °C

SD-HYS

Input Logic High VIH 2.5 V ≤ AVIN ≤ 5.5 V 1.2 V Input Logic Low VIL 2.5 V ≤ AVIN ≤ 5.5 V 0.4 V

ENx = AVIN or GND 0.05 µA

Input Leakage Current (WMOD

V

I-LEAKAGE

Excluded) ENx = AVIN or GND, TJ = −40°C to +125°C 1 µA WMOD Input Leakage Current V

I-LKG-WMOD

VWMOD = 3.6 V, TJ = −40°C to +125°C 50 µA

OPEN-DRAIN OUTPUTS

nRSTO, WSTAT Output Voltage VOL AVIN = 2.3 V to 5.5 V, I Open-Drain Reset Output Leakage

1 µA

nRSTO/WSTAT

= 3 mA 30

Current

SUPERVISORY SPECIFICATION

AVIN, VIN1 = full operating range, TJ = −40°C to +125°C, unless otherwise noted.

Table 2.

Parameter Min Typ Max Unit Test Conditions/Comments

Supply Current (Supervisory Circuit Only) 45 55 µA AVIN = 5.5 V, EN1 = EN2 = EN3 = VIN

43 52 µA AVIN = 3.6 V, EN1 = EN2 = EN3 = VIN

VTH − 1.5% VTH VTH + 1.5% V

RESET THRESHOLD TO OUTPUT DELAY

GLITCH IMMUNITY (t

UOD

)

RESET TIMEOUT PERIOD WATCHDOG1 (t

RP1

50 125 400 µs V

) Option A 24 30 36 ms Option B 160 200 240 ms

RP2

3.5 5 7 ms VCC TO RESET DELAY (tRD) 150 µs VIN1 falling at 1 mV/µs REGULATORS SEQUENCING DELAY (tD1, tD2) 2 ms WATCHDOG INPUTS

Watchdog 1 Timeout Period (t

)

WD1

Option A 81.6 102 122.4 ms Option B 1.28 1.6 1.92 sec

= −40°C to +125°C, sensed on

T

J

V

OUTx

= V

TH

− 50 mV

UOT

Rev. A | Page 3 of 32

ADP5042 Data Sheet

Option D

6.4 8 9.6

min

Option A

210 ms

MANUAL RESET INPUT

Parameter Min Typ Max Unit Test Conditions/Comments

Watchdog 2 Timeout Period (t

Option A 6 7.5 9 sec Option B Watchdog 2 disabled Option C 3.2 4 4.8 min

Option E 11.2 16 19.2 min Option F 25.6 32 38.4 min Option G 51.2 64 76.8 min Option H 102.4 128 153.8 min

Watchdog 2 Power Off Period (t

Option B 400 ms WDI1 Pulse Width 80 ns VIL = 0.4 V, VIH = 1.2 V WDI2 Pulse Width 8 µs VIL = 0.4 V, VIH = 1.2 V Watchdog Status Timeout Period (t WDI1 Input Current (Source) 8 15 20 µA V WDI1 Input Current (Sink) −30 −25 −14 µA V WDI2 Internal Pull-Down 45 kΩ

)

WD2

)

POFF

) 11.2 sec

WDCLEAR

= VCC, time average

WDI1

= 0, time average

WDI1

MR Input Pulse Width MR Glitch Rejection MR Pull-Up Resistance MR to Reset Delay

1 µs 220 ns 25 52 80 kΩ 280 ns V

= 5 V

CC

Rev. A | Page 4 of 32

Data Sheet ADP5042

NFET, AVIN = VIN1 = 5 V

150

210

mΩ

I

= 1 mA

BUCK SPECIFICATIONS

AVIN, VIN1 = 3.6 V, V

for typical specifications, unless otherwise noted.

Table 3.

Parameter Test Conditions/Comments Min Typ Max Unit

INPUT CHARACTERISTICS

Input Voltage Range (VIN1) 2.3 5.5 V

OUTPUT CHARACTERISTICS

Output Voltage Accuracy PWM mode, TA= 25 °C , I

PWM mode −2 +2 %

PWM TO POWER SAVE MODE CURRENT THRESHOLD 100 mA INPUT CURRENT CHARACTERISTICS

DC Operating Current I Shutdown Current ENx = 0 V, TA = TJ = −40°C to +125°C 0.2 1.0 μA

SW CHARACTERISTICS

SW On Resistance PFET 180 240 mΩ PFET, AVIN = VIN1 = 5 V 140 190 mΩ

NFET 170 235 mΩ

= 1.8 V, TJ= −40°C to +125°C for minimum/maximum specifications, L = 1 µH, C

OUT1

1

VIN1 = 2.3 V to 5.5 V, PWM mode,

= 1 to 800 mA

I

LOAD

= 0 mA, device not switching 21 35 μA

LOAD

= 100 mA −1 +1 %

LOAD

−3 +3 %

= 10 µF, and TA = 25°C

OUT

Current Limit PFET switch peak current limit 1100 1360 1600 mA ACTIVE PULL-DOWN EN1 = 0 V 75 Ω OSCILLATOR FREQUENCY 2.5 3.0 3.5 MHz STA RT-UP TIME 250 μs

1

All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).

LDO1, LDO2 SPECIFICATIONS

AVIN = 3.6 V, V T

= 25°C, unless otherwise noted.

A

Table 4.

Parameter Symbol Conditions Min Typ Max Unit

INPUT VOLTAGE RANGE V OPERATING SUPPLY CURRENT (per

LDO) I I I I I FIXED OUTPUT VOLTAGE ACCURACY V 100 µA < I V 100 µA < I V TJ = −40°C to +125°C REGULATION

Line Regulation ∆V

TJ = −40°C to +125°C

IN2, VIN3

= (V

+ 0.2 V) or 2.3 V, whichever is greater; AVIN, VIN1 ≥ VIN2, VIN3; I

OUT3

, V

TJ = −40°C to +125°C 1.7

IN2

IN3

I

GND

OUT2, VOUT3

/∆V

OUT2

∆V

/∆V

OUT3

I

IN2

IN3

= 0 µA, V

OUT

= 0 µA, V

OUT

= 10 mA 67 µA

OUT

= 10 mA, TJ = −40°C to +125°C 105 µA

OUT

= 200 mA 100 µA

OUT

= 200 mA, TJ = −40°C to +125°C 245 µA

OUT

= 10 mA −1 +1 %

OUT

IN2, VIN3

V

IN2, VIN3

OUT3

= 3.3 V 15 µA

OUT

= 3.3 V, TJ = −40°C to +125°C 50 µA

OUT

< 300 mA −2 +2 %

OUT

= (V

OUT2, VOUT3

< 300 mA −3 +3 %

OUT

= (V

OUT2, VOUT3

= (V

OUT2, VOUT3

+ 0.5 V) to 5.5 V

+ 0.5 V) to 5.5 V −0.03 +0.03 %/V

= 10 mA; CIN = C

OUT

= 1 µF;

OUT

5.5 V

Rev. A | Page 5 of 32

ADP5042 Data Sheet

I

= 200 mA

60 mV

µV rms

Parameter Symbol Conditions Min Typ Max Unit

Load Regulation1 ∆V

∆V

OUT2

OUT3

/∆I /∆I

OUT2

OUT3

I TJ = −40°C to +125°C

DROPOUT VOLTAGE2 V

DROPOUT

V I I

I

ACTIVE PULL-DOWN R STA RT-UP TIME T CURRENT-LIMIT THRESHOLD3 I OUTPUT NOISE OUT

EN2/EN3 = 0 V 600 Ω

PDLDO

V

STA RT-UP

TJ = −40°C to +125°C 335 470 mA

LIMIT

LDO2NOISE

10 Hz to 100 kHz, V 10 Hz to 100 kHz, V OUT

LDO1NOISE

10 Hz to 100 kHz, V 10 Hz to 100 kHz, V POWER SUPPLY REJECTION RATIO PSRR

1

Based on an end-point calculation using 1 mA and 100 mA loads.

2

Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output

voltages above 2.3 V.

3

Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V

output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V.

I

OUT2, VOUT3

= 1 mA to 200 mA 0.002 %/mA

OUT2, VOUT3

OUT2, IOUT3

OUT2, VOUT3

= 1 mA to 200 mA 0.0075 %/mA

= 3.3 V = 10 mA 4 mV = 10 mA, TJ = −40°C to +125°C 5 mV

= 200 mA, TJ = −40°C to +125°C 100 mV

= 3.3 V 85 µs

10 Hz to 100 kHz, V

IN2, VIN3

, V

IN2

= 3.3 V, V

IN3

1 kHz, V

= 100 mA

I

OUT

100 kHz, V

= 100 mA

I

OUT

1 MHz, V

= 100 mA

I

OUT

= 5 V, V

IN3

= 5 V, V

IN3

= 5 V, V

IN3

= 5 V, V

IN2

= 5 V, V

IN2

= 5 V, V

IN2

OUT3

OUT2

OUT2, OUT3

OUT2, VOUT3

= 3.3 V 123 µV rms = 2.8 V 110 µV rms = 1.5 V 59 µV rms = 3.3 V 140 µV rms = 2.8 V 129 µV rms = 1.5 V 66

= 2.8 V,

66 dB

57 dB

60 dB

INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS

Table 5.

Parameter Symbol Conditions Min Typ Max Unit

MINIMUM OUTPUT CAPACITANCE (BUCK)1 C MINIMUM INPUT AND OUTPUT CAPACITANCE2 (LDO1, LDO2) C CAPACITOR ESR R

1

The minimum output capacitance should be greater than 4.7 µF over the full range of operating conditions. The full range of operating conditions in the application

must be considered during device selection to ensure that the minimum capacitance specification is met.

2

The minimum input and output capacitance should be greater than 0.70 µF over the full range of operating conditions. The full range of operating conditions in the

application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended, Y5V and Z5U capacitors are not recommended for use with LDOs or the buck.

TJ = −40°C to +125°C 7 40 µF

MIN1

TJ = −40°C to +125°C 0.70 µF

MIN23

TJ = −40°C to +125°C 0.001 1 Ω

ESR

Rev. A | Page 6 of 32

Data Sheet ADP5042

ESD Machine Model

100 V

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter Rating

AVIN, VINx, VOUTx, ENx, MODE, MR, WDIx, WMOD, WSTAT, nRSTO to GND Storage Temperature Range −65°C to +150°C

Operating Junction Temperature Range −40°C to +125°C Soldering Conditions JEDEC J-STD-020 ESD Human Body Model 3000 V ESD Charged Device Model 1500 V

−0.3 V to +6 V

Junction-to-ambient thermal resistance (θ based on modeling and calculation using a 4-layer board. The junction-to-ambient thermal resistance is highly dependent on the application and board layout. In applications where high maximum power dissipation exists, close attention to thermal board design is required. The value of θ PCB material, layout, and environmental conditions. The specified value of θ

is based on a four-layer, 4” × 3”, 2.5 oz copper board,

JA

as per JEDEC standard. For additional information, see the

AN-772 Application Note, A Design and Manufacturing Guide

for the Lead Frame Chip Scale (LFCSP).

) of the package is

JA

may vary, depending on

JA

Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL DATA

Absolute maximum ratings apply individually only, not in combination.

The ADP5042 can be damaged when the junction temperature limits are exceeded. Monitoring ambient temperature does not guarantee that the junction temperature is within the specified temperature limits. In applications with high power dissipation and poor thermal resistance, the maximum ambient temperature may have to be derated. In applications with moderate power dissipation and low PCB thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. The junction temperature of the device is dependent on the ambient temperature, the power dissipation of the device (P

), and the junction-to-ambient thermal resistance of the

D

package. Maximum junction temperature is calculated from the ambient temperature and power dissipation using the formula

T

= TA + (PD × θJA)

J

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.

Table 7. Thermal Resistance

Package Type θJA θJC Unit

20-Lead, 0.5 mm pitch LFCSP 38 4.2 °C/W

ESD CAUTION

Rev. A | Page 7 of 32

ADP5042 Data Sheet

D

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DI1

MO

W

MODE

W

MR 20

EN2

19

16

17

18

1

NC

2

VOUT3

VIN3

EN3

nRSTO

NOTES

1. EXPOSED PAD SHOULD BE CONNECTED TO AGND.

2. NC = NO CONNE CT. DO NOT CONNECT TO THIS PIN.

3 4 5

ADP5042

TOP VIEW

(Not to S cale)

8

6

7

SW

VIN1

AVIN

15 WSTAT

VOUT2

14 13

VIN2

12

WDI2

11

VOUT1

9

10 EN1

PGND

08811-002

Figure 2. Pin Configuration—View from Top of the Die

Table 8. Preliminary Pin Function Descriptions

Pin No. Mnemonic Description

1 NC Do not connect to this pin. 2 VOUT3 LDO2 Output Voltage and Sensing Input. 3 VIN3 LDO2 Input Supply (1.7 V to 5.5 V). 4 EN3 Enable LDO2. EN3 = high: turn on LDO2; EN3 = low: turn off LDO2. 5 nRSTO Open-Drain Reset Output, Active Low. 6 AVIN Regulators Housekeeping and Supervisory Input Supply (2.3 V to 5.5 V). 7 VIN1 Buck Input Supply (2.3 V to 5.5 V). 8 SW Buck Switching Node. 9 PGND Dedicated Power Ground for Buck Regulator. 10 EN1 Enable Buck. EN1 = high: turn on buck; EN1 = low: turn off buck. 11 VOUT1 Buck Sensing Node. 12 WDI2 Watchdog 2 (Long Timeout) Refresh Input from Processor. Can be disabled only by factory option. 13 VIN2 LDO1 Input Supply (1.7 V to 5.5 V). 14 VOUT2 LDO1 Output Voltage and Sensing Input. 15 WSTAT

Open-Drain Watchdog Timeout Status. WSTAT = high: Watchdog 1 timeout or power-on reset; WSTAT = low:

Watchdog 2 timeout. Auto cleared after one second. 16 EN2 Enable LDO1. EN2 = high: turn on LDO1. EN2 = low: turn off LDO1. 17 MODE

Buck Mode. MODE = high: buck regulator operates in fixed PWM mode; MODE = low: buck regulator operates

in pulse skipping mode (PSM) at light load and in constant PWM at higher load. 18 WMOD

Watchdog Mode. WMOD = low: Watchdog 1 normal mode; WMOD = high: Watchdog 1 cannot be disabled by

a three-state condition applied on WDI1. 19 WDI1 Watchdog 1 Refresh Input from Processor. If WDI1 is in high-Z and WMOD is low, Watchdog 1 is disabled. 20

MR

Manual Reset Input, Active Low. TP AGND Analog Ground (TP = Thermal Pad). Exposed pad should be connected to AGND.

Rev. A | Page 8 of 32

Data Sheet ADP5042

08811-003

CH1 2.0V/DIV 1MΩ

B

W

20.0M

CH2 2.0V/DIV 1MΩ

B

W

500M

CH3 2.0V/DIV 1MΩ

B

W

20.0M

A CH1 1.76V 200µs/DIV

50.0MS/s

20.0ns/pt

1

2

3

VOUT1

VOUT2

VOUT3

0

0.1

0.2

0.3

0.4

0.5

0.6

1.0

0.9

0.8

0.7

2.3 2.8 3.3 3.8 4.3 4.8 5.3

SYSTEM QUIESCENT CURRE NT (mA)

INPUT VOLTAGE (V)

08811-004

VOUT1 = 1.8V ,

VOUT2 = VO UT = 3.3V

08811-005

CH1 2.0V/DIV 1MΩ

B

W

20.0M

CH2 2.0V/DIV 1MΩ

B

W

500M

CH3 100mA/DIV 1MΩ

B

W

20.0M

CH4 5.0V/DIV 1MΩ

B

W

500M

A CH1 2.92V 50µs/DIV

50.0MS/s

20.0ns/pt

2

4

1

3

SW

VOUT1

EN

IIN

08811-006

CH1 4.0V/DIV 1MΩ

B

W

20.0M

CH2 3.0V/DIV 1MΩ

B

W

500M

CH3 200mA/DIV 1MΩ

B

W

20.0M

CH4 5.0V/DIV 1MΩ

B

W

500M

A CH1 2.24V 50µs/DIV

20.0MS/s

50.0ns/pt

4

2

1

3

SW

VOUT1

LOAD

EN

3.22

3.24

3.26

3.28

3.30

3.32

3.34

OUTPUT VOLTAGE (V)

OUTPUT CURRE NT (A)

0 0.1 0.2 0.3 0.4 0.5 0.6

0.7 0.8 0.9 1.0

08811-007

+25°C

–40°C +85°C

1.775

1.780

1.785

1.790

1.795

1.800

1.805

1.810

1.815

1.820

1.825

1.830

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

OUTPUT CURRE NT (A)

OUTPUT VOLTAGE (V)

+25°C

–40°C +85°C

08811-008

TYPICAL PERFORMANCE CHARACTERISTICS

VIN1 = VIN2 = VIN3 = AVIN = 5.0 V, TA = 25°C, unless otherwise noted.

Figure 3. 3-Channel Start-Up Waveforms

Figure 4. System Quiescent Current (Sum of All the Input Currents) vs. Input Voltage,

VOUT1 = 1.8 V, VOUT2 = VOUT3 = 3.3 V

Figure 6. Buck Startup, VOUT1 = 1.8 V, I

OUT2

= 20 mA

Figure 7. Buck Load Regulation Across Temperature, VOUT1 = 3.3 V, Auto Mode

Figure 5. Buck Startup, VOUT1 = 1.8 V, I

= 20 mA

OUT1

Rev. A | Page 9 of 32

Figure 8. Buck Load Regulation Across Temperature, VOUT1 = 1.8 V, Auto Mode

ADP5042 Data Sheet

1.784

1.785

1.786

1.787

1.788

1.789

1.790

1.791

1.792

1.793

1.794

1.795

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

–40°C

+25°C

+85°C

OUTPUT CURRE NT (A)

OUTPUT VOLTAGE (V)

08811-009

1.790

1.791

1.792

1.793

1.794

1.795

1.796

1.797

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

OUTPUT CURRE NT (A)

OUTPUT VOLTAGE (V)

VIN = 5.5V

VIN = 4.5V

VIN = 3.6V

08811-010

0

10

20

30

40

50

60

70

80

90

100

0.0001 0.001 0.01 0.1 1

EFFICIENCY (%)

OUTPUT CURRE NT (A)

3.6V

4.5V

5.5V

08811-011

0

10

20

30

40

50

60

70

80

90

100

0.001 0.01 0.1 1

EFFICIENCY (%)

OUTPUT CURRE NT (A)

3.6V

4.5V

5.5V

08811-012

0

10

20

30

40

50

60

70

80

90

100

0.0001 0.001

0.01 0.1 1

EFFICIENCY (%)

OUTPUT CURRE NT (A)

2.4V

3.6V

4.5V

5.5V

08811-013

0

10

20

30

40

50

60

70

80

90

100

0.001 0.01 0.1 1

EFFICIENCY (%)

I

OUT

(A)

2.4V

3.6V

4.5V

5.5V

08811-014

Figure 9. Buck Load Regulation Across Temperature, VOUT1 = 1.8 V, PWM Mode

Figure 10. Buck Load Regulation Across Input Voltage, VOUT1 = 1.8 V, PWM Mode

Figure 12. Buck Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 3.3 V,

PWM Mode

Figure 13. Buck Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 1.8 V,

Auto Mode

Figure 11. Buck Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 3.3 V,

Auto Mode

Figure 14. Buck Efficiency vs. Load Current, Across Input Voltage, VOUT2 = 1.8 V,

PWM Mode

Rev. A | Page 10 of 32

ANALOG DEVICES ADP5042 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

HIGH LEVEL BLOCK DIAGRAM

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

GENERAL SPECIFICATION

SUPERVISORY SPECIFICATION

BUCK SPECIFICATIONS

LDO1, LDO2 SPECIFICATIONS

INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

THERMAL DATA

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS