ANALOG DEVICES ADP5034 Service Manual

Dual 3 MHz, 1200 mA Buck

Data Sheet

FEATURES

Main input voltage range: 2.3 V to 5.5 V
Two 1200 mA buck regulators and two 300 mA LDOs
24-lead, 4 mm × 4 mm LFCSP package
Regulator accuracy: ±3%
Factory programmable or external adjustable VOUTx
3 MHz buck operation with forced PWM and auto PWM/PSM

modes
BUCK1/BUCK2: output voltage range from 0.8 V to 3.8 V
LDO1/LDO2: output voltage range from 0.8 V to 5.2 V
LDO1/LDO2: low input supply voltage from 1.7 V to 5.5 V
LDO1/LDO2: high PSRR and low output noise

APPLICATIONS

Power for processors, ASICS, FPGAs, and RF chipsets
Portable instrumentation and medical devices
Space constrained devices

GENERAL DESCRIPTION

The ADP5034 combines two high performance buck regulators
and two low dropout (LDO) regulators in a small, 24-lead 4 mm ×

Regulators with Two 300 mA LDOs

ADP5034

4 mm LFCSP to meet demanding performance and board space
requirements.

The high switching frequency of the buck regulators enables tiny
multilayer external components and minimizes the board space.
When the MODE pin is set to high, the buck regulators operate in
forced PWM mode. When the MODE pin is set to low, the buck
regulators operate in PWM mode when the load is above a pre­defined threshold. When the load current falls below a predefined
threshold, the regulator operates in power save mode (PSM),
improving the light load efficiency.

The two bucks operate out of phase to reduce the input capaci­tor requirement. The low quiescent current, low dropout voltage,
and wide input voltage range of the ADP5034 LDOs extend the
battery life of portable devices. The ADP5034 LDOs maintain
power supply rejection greater than 60 dB for frequencies as
high as 10 kHz while operating with a low headroom voltage.

Regulators in the ADP5034 are activated through dedicated
enable pins. The default output voltages can be externally set in
the adjustable version, or factory programmable to a wide range
of preset values in the fixed voltage version.

TYPICAL APPLICATION CIRCUIT

AVIN

0.1µF

C1

C2

ON

1µF

ON

1µF

AVIN

VIN1

EN1

VIN2

EN2

EN3

VIN3

C3

EN4

VIN4

C4

C

2.3V TO

5.5V

1.7V TO

5.5V

4.7µF

OFF

4.7µF

OFF

HOUSEKEEPING

EN1

EN2

EN3

(ANALOG)

EN4

(DIGITAL)

ADP5034

BUCK1

MODE

MODE

BUCK2

LDO1

LDO2

AGND

Figure 1.

VOUT1

SW1

FB1

PGND1

MODE

VOUT2

SW2

FB2

PGND2

VOUT3

FB3

VOUT4

FB4

L1 1µH

R1

R2

PWM

L2 1µH

R3

R4

R5

R6

R7

R8

C5
10µF

PSM/PWM

C6
10µF

C7
1µF

C8
1µF

V

OUT1

1200mA

V

OUT2

1200mA

V

OUT3

300mA

V

OUT4

300mA

AT

AT

AT

AT

09703-001

Rev. A

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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: [phone] www.analog.com
Fax: [phone] ©2011 Analog Devices, Inc. All rights reserved.

ADP5034 Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

General Description ......................................................................... 1

Typical Application Circuit ............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

General Specifications ................................................................. 3

BUCK1 and BUCK2 Specifications ........................................... 4

LDO1 and LDO2 Specifications ................................................. 4

Input and Output Capacitor, Recommended Specifications .. 5

Absolute Maximum Ratings ............................................................ 6

Thermal Resistance ...................................................................... 6

ESD Caution .................................................................................. 6

Pin Configuration and Function Descriptions ............................. 7

Typical Performance Characteristics ............................................. 8

REVISION HISTORY

10/11—Rev. 0 to Rev. A

Change to Features Section ............................................................. 1

Changes to General Description Section ...................................... 1

Changes to Figure 1 .......................................................................... 1

Change to Table 1, Low UVLO Input Voltage Falling Parameter,

Symbol Column ................................................................................ 3

Change to Table 2, Output Voltage Accuracy Parameter, Test

Conditions/Comment Column ...................................................... 4

Change to Table 2, Line Regulation Parameter, Symbols

Column .............................................................................................. 4

Change to Table 2, Load Regulation Parameter, Symbols

Column .............................................................................................. 4

Changes to Table 2, Reversed the R
the SW On Resistance Parameter and Changes to Typ and Max

Columns ............................................................................................. 4

Changes to Table 3, Output Accuracy Parameter, Test

Conditions/Comments Column ..................................................... 4

Changes to Table 3, Line Regulation Parameter, Symbols

Column and Test Conditions/Comments Column ..................... 4

Change to Table 3, Changes to Dropout Voltage Parameter and

Added Specification to Dropout Voltage Parameter.................... 5

Change to Table 3, Endnote 3 ......................................................... 5

Change to Table 4, BUCK1, BUCK2 Output Capacitor

Parameter, Min Column Value ....................................................... 5

PFET

and R

Symbols for

NFET

Theory of Operation ...................................................................... 15

Power Management Unit ........................................................... 15

BUCK1 and BUCK2 .................................................................. 17

LDO1 and LDO2 ........................................................................ 18

Applications Information .............................................................. 19

Buck External Component Selection ....................................... 19

LDO External Component Selection ...................................... 21

Power Dissipation and Thermal Considerations ....................... 22

Buck Regulator Power Dissipation .......................................... 22

Junction Temperature ................................................................ 23

PCB Layout Guidelines .................................................................. 24

Typical Application Schematics .................................................... 25

Bill of Materials ........................................................................... 25

Outline Dimensions ....................................................................... 26

Ordering Guide .......................................................................... 26

Change to Table 4, Endnote 1 .......................................................... 5

Changes to Absolute Maximum Ratings, Table 5 ......................... 6

Changes to Table 7, Pin Function Descriptions ............................ 7

Changes to TPC Section ................................................................... 8

Moved Power Dissipation and Thermal Considerations

Section .............................................................................................. 22

Change to Equation 5 Where Statement ..................................... 22

Change to Equation 6..................................................................... 22

Change to Undervoltage Lockout Section .................................. 16

Changes to Figure 46 ...................................................................... 16

Change to Figure 47 ....................................................................... 17

Changes to LDO1/LDO2 Section ................................................ 18

Changes to Output Capacitor Section and Table 8 .................... 19

Change to V

Changes to Input and Output Capacitor Properties Section .... 21

Changes to Equation 3 ................................................................... 22

Changes to Junction Temperature Section .................................. 23

Changes to LDO Regulator Power Dissipation Section ............ 23

Changes to Figure 52 and Figure 53............................................. 25

Moved Bill of Materials Section .................................................... 25

Changes to Ordering Guide .......................................................... 26

6/11—Revision 0: Initial Version

Equation, Table 9, and Figure 50 ................... 20

RIPPLE

Rev. A | Page 2 of 28

Data Sheet ADP5034

SPECIFICATIONS

GENERAL SPECIFICATIONS

V

= V

= V

AVI N

IN1

= 2.3 V to 5.5 V; V

IN2

25°C for typical specifications, unless otherwise noted.

Table 1.

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

INPUT VOLTAGE RANGE V
THERMAL SHUTDOWN

Threshold TSSD T

Hysteresis TS

START-UP TIME1

BUCK1, LDO1, LDO2 t

BUCK2 t

EN1, EN2, EN3, EN4, MODE INPUTS

Input Logic High VIH 1.1 V

Input Logic Low VIL 0.4 V

Input Leakage Current V

INPUT CURRENT

All Channels Enabled I

All Channels Disabled I

VIN1 UNDERVOLTAGE LOCKOUT

High UVLO Input Voltage Rising UVLO

High UVLO Input Voltage Falling UVLO

Low UVLO Input Voltage Rising UVLO

Low UVLO Input Voltage Falling UVLO

1

Start-up time is defined as the time from EN1 = EN2 = EN3 = EN4 from 0 V to V

times are shorter for individual channels if another channel is already enabled. See the Typi section for more information. cal Performance Characteristics

IN3

= V

= 1.7 V to 5.5 V; TJ = −40°C to +125°C for minimum/maximum specifications, and TA =

IN4

, V

, V

AVIN

SD-HYS

START1

START2

I-LEAKAGE

STBY-NOSW

SHUTDOWN

2.3 5.5 V

IN1

IN2

rising 150 °C

J

20 °C

250 µs
300 µs

0.05 1 µA

No load, no buck switching 108 175 µA

T

3.9 V

VIN1RISE

VIN1FALL

2.275 V

VIN1RISE

VIN1FALL

= −40°C to +85°C 0.3 1 µA

J

3.1 V

1.95 V

to VOUT1, VOUT2, VOUT3, and VOUT4 reaching 90% of their nominal level. Start-up

AVIN

Rev. A | Page 3 of 28

ADP5034 Data Sheet

BUCK1 AND BUCK2 SPECIFICATIONS

V

= V

= V

AVI N

IN1

specifications, unless otherwise noted.

Table 2.

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

OUTPUT CHARACTERISTICS

Output Voltage Accuracy V

Line Regulation

Load Regulation

VOLTAGE FEEDBACK V
OPERATING SUPPLY CURRENT MODE = ground

BUCK1 Only IIN

BUCK2 Only IIN

BUCK1 and BUCK2 IIN

PSM CURRENT THRESHOLD I
SW CHARACTERISTICS

SW On Resistance R
R
R
R

Current Limit I
ACTIVE PULL-DOWN R
OSCILLATOR FREQUENCY fSW 2.5 3.0 3.5 MHz

1

All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).

= 2.3 V to 5.5 V; TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical

IN2

OUT1

, V

1

OUT2

PWM mode; I

LOAD1

= I

= 0 mA to

LOAD2

−3 +3 %

1200 mA

(∆V
(∆V

(∆V
(∆V

FB1

OUT1/VOUT1

OUT2/VOUT2

OUT1/VOUT1

OUT2/VOUT2

, V

)/∆V
)/∆V

)/∆I
)/∆I

Models with adjustable outputs 0.485 0.5 0.515 V

FB2

PWM mode −0.05 %/V

,

IN1

IN2

= 0 mA to 1200 mA, PWM mode −0.1 %/A

I

,

LOAD

OUT1

OUT2

= 0 mA, device not switching, all

I

LOAD 1

44 A

other channels disabled

= 0 mA, device not switching, all

I

LOAD 2

55 A

other channels disabled
I

LOAD 1

= I

= 0 mA, device not switching,

LOAD 2

67 A

LDO channels disabled

PSM to PWM operation 100 mA

PSM

V

NFET

V

PFET

V

NFET

V

PFET

, I

LIMIT1

LIMIT2

Channel disabled 75 Ω

PDWN-B

= V

= 3.6 V 155 240 mΩ

IN1

IN2

= V

= 3.6 V 205 310 mΩ

IN1

IN2

= V

= 5.5 V 137 204 mΩ

IN1

IN2

= V

= 5.5 V 162 243 mΩ

IN1

IN2

pFET switch peak current limit 1600 1950 2300 mA

LDO1 AND LDO2 SPECIFICATIONS

V

= (V

IN3

1 µF; T

Table 3.

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

INPUT VOLTAGE RANGE V
OPERATING SUPPLY CURRENT

Bias Current per LDO2 I
I
I

Total System Input Current

LDO1 or LDO2 Only I
LDO1 and LDO2 Only I

OUTPUT CHARACTERISTICS

Output Voltage Accuracy V

Line Regulation

Load Regulation3

+ 0.5 V) or 1.7 V (whichever is greater) to 5.5 V, V

OUT3

= −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted.1

J

, V

1.7 5.5 V

IN3

IN4

VIN3BIAS/IVIN4BIAS

IIN

I

OUT3

OUT3

OUT3

Includes all current into AVIN, VIN1, VIN2, VIN3,

= (V

IN4

= I

= 0 µA 10 30 µA

OUT4

= I

= 10 mA 60 100 µA

OUT4

= I

= 300 mA 165 245 µA

OUT4

+ 0.5 V) or 1.7 V (whichever is greater) to 5.5 V; CIN = C

OUT4

and VIN4

= I

= 0 µA, all other channels disabled 53 µA

OUT4

= I

= 0 µA, buck channels disabled 74 µA

OUT4

< 300 mA, 100 µA < I

OUT3

OUT4

<

−3 +3 %

OUT3

, V

OUT4

OUT3

OUT3

100 µA < I
300 mA

= I

(∆V
(∆V

(∆V
(∆V

OUT3/VOUT3

OUT4/VOUT4

OUT3/VOUT3

OUT4/VOUT4

)/∆V
)/∆V

)/∆I
)/∆I

IN3

IN4

OUT3

OUT4

I

,

OUT3

I

,

OUT3

= 1 mA −0.03 +0.03 %/V

OUT4

= I

= 1 mA to 300 mA 0.001 0.003 %/mA

OUT4

Rev. A | Page 4 of 28

OUT

=

Data Sheet ADP5034

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

V

, V

VOLTAGE FEEDBACK
DROPOUT VOLTAGE4 V
V
V
V
CURRENT-LIMIT THRESHOLD5 I
ACTIVE PULL-DOWN R
OUTPUT NOISE

Regulator LDO1 NOISE
Regulator LDO2 NOISE

POWER SUPPLY REJECTION

RATIO
Regulator LDO1 10 kHz, V
100 kHz, V
1 MHz, V

Regulator LDO2 10 kHz, V
100 kHz, V
1 MHz, V

1

All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).

2

This is the input current into VIN3/VIN4, which is not delivered to the output load.

3

Based on an endpoint calculation using 1 mA and 300 mA loads.

4

Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only to output voltages

above 1.7 V.

5

Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V

output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V.

FB3

FB4

V

DROPOUT

, I

LIMIT3

PDWN-L

335 600 mA

LIMIT4

Channel disabled 600 Ω

10 Hz to 100 kHz, V

LDO1

10 Hz to 100 kHz, V

LDO2

0.485 0.5 0.515 V
= V

OUT3

OUT3

OUT3

OUT3

= V
= V
= V

OUT4

OUT4

OUT4

OUT4

= 5.2 V, I
= 3.3 V, I
= 2.5 V, I
= 1.8 V, I

OUT3

OUT3

OUT3

OUT3

= 5 V, V

IN3

= 5 V, V

IN4

= I

= 300 mA 50 mV

OUT4

= I

= 300 mA 75 140 mV

OUT4

= I

= 300 mA 100 mV

OUT4

= I

= 300 mA 180 mV

OUT4

= 2.8 V 100 µV rms

OUT3

= 1.2 V 60 µV rms

OUT4

PSRR

= 3.3 V, V

IN3

= 3.3 V, V

IN3

= 3.3 V, V

IN3

= 1.8 V, V

IN4

= 1.8 V, V

IN4

= 1.8 V, V

IN4

OUT3

OUT3

OUT3

OUT4

OUT4

OUT4

= 2.8 V, I

= 2.8 V, I

= 2.8 V, I

= 1.2 V, I

= 1.2 V, I

= 1.2 V, I

= 1 mA 60 dB

OUT3

= 1 mA 62 dB

OUT3

= 1 mA 63 dB

OUT3

= 1 mA 54 dB

OUT4

= 1 mA 57 dB

OUT4

= 1 mA 64 dB

OUT4

INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS

TA = −40°C to +125°C, unless otherwise specified.

Table 4.

Parameter Symbol Min Typ Max Unit

SUGGESTED INPUT AND OUTPUT CAPACITANCE

BUCK1, BUCK2 Input Capacitor C
BUCK1, BUCK2 Output Capacitor C
LDO1, LDO21 Input and Output Capacitor C

CAPACITOR ESR R

1

The minimum input and output capacitance should be greater than 0.70 µF over the full range of operating conditions. The full range of operating conditions in the

application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R- and X5R-type capacitors are
recommended; Y5V and Z5U capacitors are not recommended for use because of their poor temperature and dc bias characteristics.

, C

MIN1

MIN1

MIN3

ESR

4.7 40 µF

MIN2

, C

7 40 µF

MIN2

, C

0.70 µF

MIN4

0.001 1 Ω

Rev. A | Page 5 of 28

ADP5034 Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

AVIN to AGND −0.3 V to +6 V
VIN1, VIN2 to AVIN −0.3 V to +0.3 V
PGND1, PGND2 to AGND −0.3 V to +0.3 V
VIN3, VIN4, VOUT1, VOUT2, FB1, FB2,

FB3, FB4, EN1, EN2, EN3, EN4, MODE
to AGND

VOUT3 to AGND −0.3 V to (VIN3 + 0.3 V)
VOUT4 to AGND −0.3 V to (VIN4 + 0.3 V)
SW1 to PGND1 −0.3 V to (VIN1 + 0.3 V)
SW2 to PGND2 −0.3 V to (VIN2 + 0.3 V)
Storage Temperature Range −65°C to +150°C
Operating Junction Temperature

Range

Soldering Conditions JEDEC J-STD-020

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

For detailed information on power dissipation, see the Power
Dissipation and Thermal Considerations section.

−0.3 V to (AVIN + 0.3 V)

−40°C to +125°C

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 6. Thermal Resistance

Package Type θJA θJC Unit

24-Lead, 0.5 mm pitch LFCSP 35 3 °C/W

ESD CAUTION

Rev. A | Page 6 of 28

Data Sheet ADP5034

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VOUT4

24

PIN 1
INDICATOR

1

FB4
EN4

2
3
4
5
6

ADP5034

TOP VIEW

(Not to Scale)

7

EN2

VIN2
SW2

PGND2

NC

NOTES

1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.

2. IT IS RECOMMENDED THAT THE EXPOSED PAD
BE SOLDERED TO THE GROUND PLANE.

FB3

VOUT3

VIN3

EN3

VIN4

20

19

23

22

21

AGND

18

AVIN

17

VIN1

16

SW1

15
14

PGND1
MODE

13

9

8

11

12

10

FB1

FB2

EN1

VOUT1

VOUT2

09703-003

Figure 2. Pin Configuration—View from the Top of the Die

Table 7. Pin Function Descriptions

Pin No. Mnemonic Description

1 FB4

LDO2 Feedback Input. For device models with a adjustable output voltage, connect this pin to the middle of the
LDO2 resistor divider. For device models with a factory programmed output voltage, connect FB4 to the top of the

capacitor on VOUT4.
2 EN4 LDO2 Enable Pin. High level turns on this regulator, and low level turns it off.
3 VIN2 BUCK2 Input Supply (2.3 V to 5.5 V). Connect VIN2 to VIN1 and AVIN.
4 SW2 BUCK2 Switching Node.
5 PGND2 Dedicated Power Ground for BUCK2.
6 NC No Connect. Leave this pin unconnected.
7 EN2 BUCK2 Enable Pin. High level turns on this regulator, and low level turns it off.
8 FB2

BUCK2 Feedback Input. For device models with an adjustable output voltage, connect this pin to the middle of the

BUCK2 resistor divider. For device models with a fixed output voltage, leave this pin unconnected.
9 VOUT2 BUCK2 Output Voltage Sensing Input. Connect VOUT2 to the top of the capacitor on VOUT2.
10 VOUT1 BUCK1 Output Voltage Sensing Input. Connect VOUT1 to the top of the capacitor on VOUT1.
11 FB1

BUCK1 Feedback Input. For device models with an adjustable output voltage, connect this pin to the middle of the

BUCK1 resistor divider. For device models with a fixed output voltage, leave this pin unconnected.
12 EN1 BUCK1 Enable Pin. High level turns on this regulator, and low level turns it off.
13 MODE BUCK1/BUCK2 Operating Mode. MODE = high: forced PWM operation. MODE = low: auto PWM/PSM operation.
14 PGND1 Dedicated Power Ground for BUCK1.
15 SW1 BUCK1 Switching Node.
16 VIN1 BUCK1 Input Supply (2.3 V to 5.5 V). Connect VIN1 to VIN2 and AVIN.
17 AVIN Analog Input Supply (2.3 V to 5.5 V). Connect AVIN to VIN1 and VIN2.
18 AGND Analog Ground.
19 FB3

LDO1 Feedback Input. For device models with an adjustable output voltage, connect this pin to the middle of the

LDO1 resistor divider. For device models with a factory programmed output voltage, connect FB3 to the top of the

capacitor on VOUT3.
20 VOUT3 LDO1 Output Voltage.
21 VIN3 LDO1 Input Supply (1.7 V to 5.5 V).
22 EN3 LDO1 Enable Pin. High level turns on this regulator, and low level turns it off.
23 VIN4 LDO2 Input Supply (1.7 V to 5.5 V).
24 VOUT4 LDO2 Output Voltage.
EPAD EP Exposed Pad. It is recommended that the exposed pad be soldered to the ground plane.

Rev. A | Page 7 of 28

ADP5034 Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

V

= V

= V

= V

IN1

140

IN2

IN3

= 3.6 V, TA = 25°C, unless otherwise noted.

IN4

3.35

120

100

80

60

40

QUIESCENT CURRENT (µA)

20

0

2.3 2.8 3.3 3.8 4.3 4.8 5.3

INPUT VOLTAGE (V)

Figure 3. System Quiescent Current vs. Input Voltage, V

V

OUT2

4

2

1

3

= 1.8 V, V

= 1.2 V, V

OUT3

T

SW

IOUT

VOUT

EN

= 3.3 V, All Channels Unloaded

OUT4

OUT1

= 3.3 V,

3.33

VIN = 4.2V, +25°C

3.31

(V)

OUT

V

3.29

3.27

3.25
0 0.2 0.4 0.6 0.8 1.0 1.2

09703-039

Figure 6. BUCK1 Load Regulation Across Temperature, V

VIN = 4.2V, +85°C

= 4.2V, –40°C

V

IN

I

OUT

(A)

OUT1

= 3.3 V,

09703-025

Auto Mode

1.864

(V)

OUT

V

1.844

1.824

1.804

1.784

VIN = 3.6V, +2 5°C

VIN = 3.6V, +8 5°C

V

= 3.6V, –40° C

IN

CH1 2.00V
CH3 5.00V

B

CH2 50.0mA 

W

B

CH4 5.00V

W

Figure 4. BUCK1 Startup, V

T

4

2

1

3

CH1 2.00V
CH3 5.00V

SW

IOUT

VOUT

EN

B

B

W

W

CH2 50.0mA 

CH4 5.00V

Figure 5. BUCK2 Startup, V

B

M 40.0µs A CH3 2.2V

W

B

W

T 11.20%

OUT1

= 1.8 V, I

OUT1

= 5 mA

B

M 40.0µs A CH3 2.2V

W

B

W

T 11.2 0%

= 3.3 V, I

OUT2

OUT2

= 10 mA

09703-049

09703-048

Rev. A | Page 8 of 28

1.764

0 0.2 0.4 0.6 0.8 1.0 1.2

I

(A)

OUT

Figure 7. BUCK2 Load Regulation Across Temperature, V

Auto Mode

0.799

0.798

0.797

0.796

0.795

(V)

0.794

OUT

V

0.793

0.792

0.791

0.790

0.789

0 0.2 0.4 0.6 0.8 1.0 1.2

VIN = 3.6V, +85° C

VIN = 3.6V, +25 °C

= 3.6V, –40° C

V

IN

I

OUT

(A)

Figure 8. BUCK1 Load Regulation Across Input Voltage, V

PWM Mode

OUT2

OUT1

= 1.8 V,

= 0.8 V,

09703-024

09703-026

Data Sheet ADP5034

C

C

C

100

VIN = 3.9V
V

= 4.2V

IN

90

= 5.5V

V

IN

80

70

60

Y (%)

50

40

EFFICIEN

30

20

10

0

0.0001 0.001 0.01 0.1 1

I

(A)

OUT

Figure 9. BUCK1 Efficiency vs. Load Current, Across Input Voltage,

= 3.3 V, Auto Mode

V

OUT1

100

90

80

70

VIN = 3.9V

60

50

40

EFFICIENCY (%)

30

20

10

0

0.001 0.01 0.1 1

VIN = 4.2V

I

OUT

(A)

VIN = 5.5V

Figure 10. BUCK1 Efficiency vs. Load Current, Across Input Voltage,

= 3.3 V, PWM Mode

V

OUT1

100

90

80

70

VIN = 3.6V

60

Y (%)

50

40

EFFICIEN

30

20

10

0

0.001 0.01 0.1 1

VIN = 4.2V

I

OUT

VIN = 5.5V

(A)

VIN = 2.3V

Figure 11. BUCK2 Efficiency vs. Load Current, Across Input Voltage,

V

= 1.8 V, Auto Mode

OUT2

09703-027

09703-018

09703-020

100

VIN = 2.3V

VIN = 3.6V

I

OUT

VIN = 5.5V

VIN = 4.2V

(A)

90

80

70

60

Y (%)

50

40

EFFICIEN

30

20

10

0

0.001 0.01 0.1 1

Figure 12. BUCK2 Efficiency vs. Load Current, Across Input Voltage,

= 1.8 V, PWM Mode

V

OUT2

100

90

80

70

60

50

VIN = 3.6V

40

EFFICIENCY(%)

30

20

10

0

0.001 0.01 0.1 1

VIN = 4.2V

I

OUT

VIN = 5.5V

(A)

VIN = 2.3V

Figure 13. BUCK1 Efficiency vs. Load Current, Across Input Voltage,

= 0.8 V, Auto Mode

V

OUT1

100

90

80

70

60

50

40

EFFICIENCY (%)

30

20

10

0

0.001 0.01 0.1 1

VIN = 2.3V

VIN = 3.6V

VIN = 4.2V

I

(A)

OUT

VIN = 5.5V

Figure 14. BUCK1 Efficiency vs. Load Current, Across Input Voltage,

= 0.8 V, PWM Mode

V

OUT1

09703-016

09703-015

09703-017

Rev. A | Page 9 of 28