ANALOG DEVICES ADP5033 Service Manual

Dual 3 MHz, 800 mA Buck

FEATURES

Main input voltage range: 2.3 V to 5.5 V Two 800 mA buck regulators and two 300 mA LDOs Tiny, 16-ball, 2 mm × 2 mm WLCSP package Regulator accuracy: ±3% Factory programmable VOUTx 3 MHz buck operation with forced PWM and auto PWM/PSM

modes BUCK1/BUCK2: output voltage range from 0.8 V to 3.3 V LDO1/LDO2: output voltage range from 0.8 V to 3.3V LDO1/LDO2: low input supply voltage from 1.7 V to 5.5 V LDO1/LDO2: high PSRR and low output noise

APPLICATIONS

Power for processors, ASICS, FPGAs, and RF chipsets Portable instrumentation and medical devices Space constrained devices

GENERAL DESCRIPTION

The ADP5033 combines two high performance buck regulators and two low dropout regulators (LDO) in a tiny, 16-ball, 2 mm × 2 mm WLCSP to meet demanding performance and board space requirements.

Regulators with Two 300 mA LDOs

ADP5033

The high switching frequency of the buck regulators enables tiny multilayer external components and minimizes the board space. When the MODE pin is set high, the buck regulators operate in forced PWM mode. When the MODE pin is set low,

the buck regulators operate in QPXFSTBWFNPEFP

UIFMPBEJT CFMPXB

around the nominal value and the load current falls

predefined threshold, the regulator operates in 14.

improving the light load efficiency.

o bucks operate out of phase to reduce the input capacitor

The tw requirement and noise.

The low quiescent current, low dropout voltage, and wide input voltage range of the ADP5033 LDO extend the battery life of portable devices. The ADP5033 LDOs maintain power supply rejection greater than 60 dB for frequencies as high as 10 kHz while operating with a low headroom voltage.

The regulators in the ADP5033 are activated by the ENA and ENB pins. The specific channels controlled by ENA and ENB are set by factory programming. A high voltage level applied to the enable pins activates the regulators. The default output voltages are factory programmable and can be set to a wide range of options.

4M. When

TYPICAL APPLICATION CIRCUIT

ADP5033

4.7µF

ON

4.7µF

C1

1µF

VIN1

ENA

ENB

VIN2

C2

VIN3

C3

VIN4

C4

UVLO

ACTIV. AND

EN2

EN3

EN4

2.3V TO 5.5V

OFF

1.7V TO 5. 5V

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

BUCK1

EN1

MODE

EN2 EN3 EN4

MODE

BUCK2

LDO1

(ANALOG)

LDO2

(DIGITAL)

AGND

Figure 1.

L1 1µH

SW1

VOUT1

PGND1

MODE

SW2

VOUT2

PGND2

VOUT3

VOUT4

PWM

L2 1µH

VOUT1 @ 800mA

C5 10µF

PSM/PWM

VOUT2 @ 800mA

C6 10µF

VOUT3 @ 300mA

C7 1µF

VOUT4 @ 300mA

C8 1µF

09788-001

ADP5033

REVISION HISTORY

5/11—Revision 0: Initial Version

Power Dissipation and Thermal Considerations....................... 15

Buck Regulator Power Dissipation .......................................... 15

Junction Temperature................................................................ 16

Theory of Operation ...................................................................... 17

Power Management Unit........................................................... 17

BUCK1 and BUCK2 .................................................................. 18

LDO1 and LDO2........................................................................ 19

Applications Information.............................................................. 20

Buck External Component Selection....................................... 20

LDO Capacitor Selection .......................................................... 22

PCB Layout Guidelines.................................................................. 23

Typical Application Schematic ..................................................... 24

Outline Dimensions....................................................................... 25

Ordering Guide .......................................................................... 25

Rev. 0 | Page 2 of 28

ADP5033

SPECIFICATIONS

GENERAL SPECIFICATIONS

V

= V

IN1

IN2

IN3

T

= 25°C for typical specifications, unless otherwise noted.

A

= 2.3 V to 5.5 V; V

IN4

Table 1.

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

INPUT VOLTAGE RANGE V THERMAL SHUTDOWN

Threshold TSSD T

Hysteresis TS

START-UP TIME1

BUCK1, LDO1, LDO2 t

BUCK2 t

ENA, ENB, MODE INPUTS

Input Logic High VIH 1.1 V

Input Logic Low VIL 0.4 V

Input Leakage Current V

STANDBY CURRENT

All Channels Enabled I

All Channels Disabled I

VIN1 UNDERVOLTAGE LOCKOUT

High UVLO Input Voltage Rising UVLO

High UVLO Input Voltage Falling UVLO

Low UVLO Input Voltage Rising UVLO

Low UVLO Input Voltage Falling UVLO

1

Start-up time is defined as the time from V

IN1

START1

START2

STBY-NOSW

SHUTDOWN

> UVLO

= V

IN3

IN1

SD-HYS

= 1.7 V to 5.5 V; TJ = −40°C to +125°C for minimum/maximum specifications, and

IN4

, V

2.3 5.5 V

IN2

rising 150 °C

J

20 °C

250 μs 300 μs

0.05 1 μA

I-LEAKAGE

No load, no buck switching 108 175 μA

T

VIN1RISE

VIN1FALL

VIN1RISE

VIN1FALL

to VOUT1, VOUT2, VOUT3, and VOUT4 reaching 90% of their nominal levels.

VIN1RISE

= −40°C to +85°C 0.3 1 μA

J

3.9 V

3.1 V

2.275 V

1.95 V

Rev. 0 | Page 3 of 28

ADP5033

BUCK1 AND BUCK2 SPECIFICATIONS

V

= V

IN1

otherwise noted.

Table 2.

Parameter

INPUT CHARACTERISTICS

Input Voltage Range V

OUTPUT CHARACTERISTICS

Output Voltage Accuracy V

Line Regulation Load Regulation

PSM CURRENT THRESHOLD

PSM to PWM Operation I

OPERATING SUPPLY CURRENT MODE = ground

BUCK1 Only I BUCK2 Only IIN I BUCK1 and BUCK2 IIN I

SW CHARACTERISTICS

SW On Resistance R

R

Current Limit I ACTIVE PULL-DOWN R OSCILLATOR FREQUENCY fSW 2.5 3.0 3.5 MHz

1

All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).

= 2.3 V to 5.5 V; TJ = −40°C to +125°C for minimum/maximum specications, and TA = 25°C for typical specifications, unless

IN2

1

Symbol

, V

IN1

, V

OUT1

, V

V

OUT1

, I

I

OUT1

100 mA

PSM

IN

pFET at VIN1 = 5 V 145 235 mΩ

PFET

R

pFET at VIN1 = 3.6 V 180 295 mΩ

PFET

R

nFET at VIN1 = 5 V 110 190 mΩ

NFET

nFET at VIN1 = 3.6 V 125 220 mΩ

NFET

, I

LIMIT1

PDWN-B

Test Conditions/Comments Min Typ Max Unit

PWM mode, I

IN2

PWM mode; V

OUT2

PWM mode

OUT2

I

OUT2

LIMIT2

= 0 mA to 800mA, PWM mode

LOAD

I

= 0 mA, device not switching, all other channels disabled. 44 A

LOAD1

= 0 mA, device not switching, all other channels disabled. 55 A

LOAD2

= I

LOAD1

LOAD2

pFET switch peak current limit 1100 1350 mA

Channel disabled

= I

LOAD 1

IN1

= V

= 0 mA to 800 mA

LOAD 2

= 2.3 V to 5.5 V; I

IN2

LOAD1 = ILOAD2

= 0 mA to 800 mA −3 +3 %

= 0 mA, device not switching, LDO channels disabled. 67 A

2.3 5.5 V

−0.05

−0.1

75 Ω

%/V %/A

LDO1 AND LDO2 SPECIFICATIONS

V

= (V

IN3

1 μF; T

Table 3.

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

INPUT VOLTAGE RANGE V OPERATING SUPPLY CURRENT

Bias Current per LDO2 I I I

Total System Input Current IIN Includes all current into VIN1, VIN2, VIN3, and VIN4

LDO1 or LDO2 Only I LDO1 and LDO2 Only I

OUTPUT CHARACTERISTICS

Output Voltage Accuracy V

Line Regulation

Load Regulation3

DROPOUT VOLTAGE4 V V V CURRENT-LIMIT THRESHOLD5 I ACTIVE PULL-DOWN R

+ 0.5 V) or 1.7 V (whichever is greater) to 5.5 V, V

OUT3

= −40°C to +125°C for minimum/maximum specications, and TA = 25°C for typical specifications, unless otherwise noted.1

J

, V

1.7 5.5 V

IN3

IN4

I

VIN3BIAS/IVIN4BIAS

, V

OUT3

V V

DROPOUT

LIMIT3

PDWN-L

OUT4

/V /V

/I /I

IN3

IN4

OUT3

OUT4

,

OUT3

OUT4

OUT3

OUT4

V

, I

335 600 mA

LIMIT4

Channel disabled 600 Ω

= I

OUT3

OUT4

= I

OUT3

OUT4

= I

OUT3

OUT4

= I

OUT3

OUT4

= I

OUT3

OUT4

100 µA < I V

= (V

IN3

V

= (V

IN3

5.5 V, I

OUT3

= I

I

OUT3

OUT4

= V

OUT3

= V

OUT3

= V

OUT3

= I

OUT4

IN4

= (V

+ 0.5 V) or 1.7 V (whichever is greater) to 5.5 V; CIN = C

OUT4

= 0 µA 10 30 µA = 10 mA 60 100 µA = 300 mA 165 245 µA

= 0 µA, all other channels disabled 53 µA = 0 µA, buck channels disabled 74 µA

< 300 mA, 100 µA < I

+ 0.5 V) to 5.5 V, V

= 1 mA

OUT4

IN4

= (V

IN4

OUT4

< 300 mA;

+ 0.5 V) to 5.5 V

+ 0.5 V) to

OUT4

−3 +3 %

−0.03 +0.03 %/V

= 1 mA to 300 mA 0.001 0.003 %/mA

= 3.3 V 65 110 mV = 2.5 V 85 mV = 1.8 V 165 mV

OUT

=

Rev. 0 | Page 4 of 28

ADP5033

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

POWER SUPPLY REJECTION

RATIO Regulator LDO1 10 kHz, V 100 kHz, V 1 MHz, V

Regulator LDO2 10 kHz, V 100 kHz, V 1 MHz, V

1

All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).2

2

This is the input current into VIN3/VIN4, which is not delivered to the output load.

3

Based on an endpoint calculation using 1 mA and 100 mA loads.

4

Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only to output voltages

above 1.7 V.

5

Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V

output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V.

INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS

TA = −40°C to +125°C, unless otherwise specified.

Table 4.

Parameter Symbol Min Typ Max Unit

SUGGESTED INPUT AND OUTPUT CAPACITANCE

BUCK1, BUCK2 Input Capacitor C

BUCK1, BUCK2 Output Capacitor C

LDO1, LDO21 Input and Output Capacitors C CAPACITOR ESR R

1

The minimum input and output capacitance should be greater than 0.70 μF over the full range of operating conditions. The full range of operating conditions in the

application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R- and X5R-type capacitors are recommended; Y5V and Z5U capacitors are not recommended for use with LDOs.

PSRR

= 3.3 V, V

IN3

= 3.3 V, V

IN3

= 3.3 V, V

IN3

= 1.8 V, V

IN4

= 1.8 V, V

IN4

= 1.8 V, V

IN4

OUT3

OUT4

= 2.8 V, I

= 1.2 V, I

= 1 mA 60 dB

OUT3

= 1 mA 62 dB

OUT3

= 1 mA 63 dB

OUT3

= 1 mA 54 dB

OUT4

= 1 mA 57 dB

OUT4

= 1 mA 64 dB

OUT4

, C

MIN1

MIN3

ESR

4.7 40 μF

MIN2

, C

10 40 μF

MIN2

, C

0.70 μF

MIN4

0.001 1 Ω

Rev. 0 | Page 5 of 28

ADP5033

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

VIN1, VIN2, VIN3, VIN4, VOUT1, VOUT2,

VOUT3, VOUT4, ENA, MODE, ENB to

Ground Storage Temperature Range –65°C to +150°C Operating Junction Temperature Range –40°C to +125°C Soldering Conditions JEDEC J-STD-020 ESD Human Body Model ±1500 V ESD Charged Device Model ±500 V ESD Machine Model ±100 V

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

For detailed information on power dissipation, see the Power Dissipation and Thermal Considerations section.

–0.3 V to +6 V

THERMAL RESISTANCE

θJA and ΨJB are specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.

Table 6. Thermal Resistance

Package Type θJA ΨJB Unit

16-Ball, 0.5 mm Pitch WLCSP 57 14 °C/W

ESD CAUTION

Rev. 0 | Page 6 of 28

ADP5033

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

BALL A1 INDICATOR

VOUT3

A

AGND

B

C

PGND1

D

Figure 2. Pin Configuration—View from the Top of the Die

Table 7. Pin Function Descriptions

Pin No. Mnemonic Description

A1 VOUT3 LDO1 Output Voltage and Sensing Input. A2 VIN3 LDO1 Input Supply (1.7 V to 5.5 V, VIN4 ≤ VIN1 = VIN2). A3 VIN4 LDO2 Input Supply (1.7 V to 5.5 V, VIN3 ≤ VIN1 = VIN2). A3 VOUT4 LDO2 Output Voltage and Sensing Input. B1 AGND Analog Ground. B2 MODE BUCK1/BUCK2 Operating Mode. MODE = high: forced PWM operation. MODE = low: auto PWM/PSM operation. B3 ENA Regulator Enable Pin A, Active High. The regulators turned on with ENA are factory programmed. B4 ENB Regulator Enable Pin B, Active High. The regulators turned on with ENB are factory programmed. C1 VIN1 BUCK1 Input Supply (2.3 V to 5.5 V) and UVLO Detection. Connect VIN1 to VIN2. C2 VOUT1 BUCK1 Output Voltage Sensing Input. C3 VOUT2 BUCK2 Output Voltage Sensing Input. C4 VIN2 BUCK2 Input Supply (2.3 V to 5.5 V). Connect VIN2 to VIN1. D1 PGND1 Dedicated Power Ground for BUCK1. D2 SW1 BUCK1 Switching Node. D3 SW2 BUCK2 Switching Node. D4 PGND2 Dedicated Power Ground for BUCK2.

234

1

VIN3

MODE

VIN1

VOUT1

SW1

TOP VIEW

(BALL SIDE DOWN)

Not to Scale

VIN4

ENA

VOUT2

SW2

VOUT4

ENB

VIN2

PGND2

09788-002

Rev. 0 | Page 7 of 28

ADP5033

TYPICAL PERFORMANCE CHARACTERISTICS

V

= V

IN1

IN2

IN3

= 5.0 V, TA = 25°C, unless otherwise noted.

IN4

140

120

100

80

60

40

QUIESCENT CURRENT (µA)

20

0

2.3 2.8 3.3 3.8 4.3 4.8 5.3

INPUT VOLTAGE (V)

Figure 3. System Quiescent Current vs. Input Voltage, V

V

OUT2

4

2

1

3

= 1.8 V, V

= 1.2 V, V

OUT3

T

SW

VOUT

EN

I

IN

= 3.3 V, All Channels Unloaded

OUT4

OUT1

= 3.3 V,

3.35

3.33

3.31

A (V)

OUT

V

3.29

3.27

3.25 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

09788-139

I

OUT

(A)

Figure 6. BUCK1 Load Regulation Across Temperature, V

VIN = 4.2V, +85°C VIN = 4.2V, +25°C VIN = 4.2V, –40°C

= 3.3 V,

OUT1

09788-058

Auto Mode

A (V)

V

OUT

1.864

1.844

1.824

1.804

1.784

VIN = 3.6V, + 85°C VIN = 3.6V, + 25°C

VIN = 3.6V, –40° C

CH1 2.00V CH3 5.00V

Figure 4. Buck1 Startup, V

T

4

2

1

3

CH1 2.00V CH3 5.00V

SW

VOUT

EN

I

IN

Figure 5. BUCK2 Startup, V

CH2 50.0mA Ω

CH4 5.00V

CH2 50.0mA Ω

CH4 5.00V

M 40.0µs A CH3 2. 2V

T 11.20%

OUT1

= 3.3 V, I

OUT1

= 10 mA

M 40.0µs A CH3 2.2V

T 11.20%

OUT2

= 1.8 V, I

OUT2

= 5 mA

09788-021

09788-020

Rev. 0 | Page 8 of 28

1.764 0 0.10.20.30.40.50.60.7 0.8

I

OUT

(A)

Figure 7. BUCK2 Load Regulation Across Temperature, V

Auto Mode

0.799

0.798

0.797

0.796

0.795

A (V)

0.794

OUT

V

0.793

0.792

0.791

0.790

0.789 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

I

OUT

(A)

VIN = 3.6V, + 85°C VIN = 3.6V, + 25°C VIN = 3.6V, –40° C

Figure 8. BUCK1 Load Regulation Across Input Voltage, V

PWM Mode

OUT2

OUT1

= 1.8 V,

= 3.3 V,

09788-057

09788-054

ADP5033

100

90

80

70

60

50

40

EFFICI ENCY (%)

30

20

10

0

0.0001 0.001 0.01 0.1 1 I

OUT

(A)

VIN = 3.9V

VIN = 4.2V

VIN = 5.5V

Figure 9. BUCK1 Efficiency vs. Load Current, Across Input Voltage,

= 3.3 V, Auto Mode

V

OUT1

100

90

80

70

60

50

40

EFFICI ENCY (%)

30

20

10

0

0.001 0.01 0.1 1 I

OUT

(A)

VIN = 3.9V

VIN = 4.2V

VIN = 5.5V

Figure 10. BUCK1 Efficiency vs. Load Current, Across Input Voltage,

= 3.3 V, PWM Mode

V

OUT1

100

90

80

70

60

50

40

EFFICI ENCY (%)

30

20

10

0

0.001 0.01 0.1 1 I

OUT

(A)

VIN = 2.3V VIN = 3.6V VIN = 4.2V VIN = 5.5V

Figure 11. BUCK2 Efficiency vs. Load Current, Across Input Voltage,

= 1.8 V, Auto Mode

V

OUT2

09788-038

09788-039

09788-036

100

90

80

70

60

50

40

EFFICI ENCY (%)

30

20

10

0

0.001 0.01 0.1 1 I

OUT

(A)

VIN = 2.4V V

= 3.6V

IN

V

= 4.5V

IN

V

= 5.5V

IN

Figure 12. BUCK2 Efficiency vs. Load Current, Across Input Voltage,

= 1.8 V, PWM Mode

V

OUT2

100

90

80

70

60

50

40

EFFICI ENCY (%)

30

20

10

0

0.001 0.01 0.1 1 I

OUT

(A)

VIN = 2.3V

= 3.6V

V

IN

= 4.2V

V

IN

= 5.5V

V

IN

Figure 13. BUCK1 Efficiency vs. Load Current, Across Input Voltage,

= 0.8 V, Auto Mode

V

OUT1

100

90

80

70

60

50

40

EFFI CIENCY (%)

30

20

10

0

0.001 0.01 0.1 1

I

OUT

(A)

VIN = 2.3V V

= 3.6V

IN

V

= 4.2V

IN

V

= 5.5V

IN

Figure 14. BUCK1 Efficiency vs. Load Current, Across Input Voltage,

= 0.8 V, PWM Mode

V

OUT1

09788-035

09788-034

09788-065

Rev. 0 | Page 9 of 28

ANALOG DEVICES ADP5033 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

TYPICAL APPLICATION CIRCUIT

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

GENERAL SPECIFICATIONS

BUCK1 AND BUCK2 SPECIFICATIONS

LDO1 AND LDO2 SPECIFICATIONS

INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS