ANALOG DEVICES ADP5023 Service Manual

Dual 3 MHz, 800 mA Buck

Data Sheet

FEATURES

Main input voltage range: 2.3 V to 5.5 V Two 800 mA buck regulators and one 300 mA LDO 24-lead, 4 mm × 4 mm LFCSP package Regulator accuracy: ±3% Factory programmable or external adjustable VOUTx 3 MHz buck operation with forced PWM and auto PWM/PSM

modes BUCK1/BUCK2: output voltage range from 0.8 V to 3.8 V LDO: output voltage range from 0.8 V to 4.75 V LDO: low input supply voltage from 1.7 V to 5.5 V LDO: high PSRR and low output noise

APPLICATIONS

Power for processors, ASIC, FPGAs, and RF chipsets Portable instrumentation and medical devices Space constrained devices

Regulators with One 300 mA LDO

ADP5023

GENERAL DESCRIPTION

The ADP5023 combines two high performance buck regulators and one low dropout (LDO) regulator in a small, 24-lead 4 mm × 4 mm LFCSP to meet demanding performance and board space requirements.

The high switching frequency of the buck regulators enables tiny multilayer external components and minimizes the board space. When the MODE pin is set high, the buck regulators operate in forced PWM mode. When the MODE pin is set low, the buck regulators operate in PWM mode when the load current is above a predefined threshold. When the load current falls below a predefined threshold, the regulator operates in power save mode (PSM) improving the light-load efficiency.

The two bucks operate out of phase to reduce the input capacitor requirement. The low quiescent current, low dropout voltage, and wide input voltage range of the ADP5023 LDO extends the battery life of portable devices. The ADP5023 LDO maintains power supply rejection greater than 60 dB for frequencies as high as 10 kHz while operating with a low headroom voltage.

Regulators in the ADP5023 are activated though dedicated enable pins. The default output voltages can be externally set in the adjustable version or factory programmable to a wide range of preset values in the fixed voltage version.

TYPICAL APPLICATION CIRCUIT

AVIN

C

FILT

0.1µF

2.3V TO

5.5V

1.7V TO

5.5V

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

4.7µF

OFF

4.7µF

OFF

1µF

VIN1

C1

ON

EN1

VIN2

C2

EN2

ON

EN3

VIN3

C3

HOUSEKEEPING

EN1

EN2

EN3

ADP5023

AGND

BUCK1

MODE

BUCK2

LDO

Figure 1.

VOUT1

SW1

FB1

PGND1

MODE

VOUT2

SW2

FB2

PGND2

VOUT3

FB3

L1 1µH

R1

R2

PWM

L2 1µH

R3

R4

R5

R6

C5 10µF

PSM/PWM

C6 10µF

C7 1µF

V

OUT1

800mA

V

OUT2

800mA

V

OUT3

300mA

AT

09889-001

ADP5023 Data Sheet

REVISION HISTORY

8/11—Revision 0: Initial Version

Power Dissipation and Thermal Considerations....................... 15

Buck Regulator Power Dissipation .......................................... 15

Junction Temperature................................................................ 16

Theory of Operation ...................................................................... 17

Power Management Unit........................................................... 17

BUCK1 and BUCK2 .................................................................. 19

LDO.............................................................................................. 20

Applications Information.............................................................. 21

Buck External Component Selection....................................... 21

LDO External Component Selection ...................................... 23

PCB Layout Guidelines.................................................................. 24

Typical Application Schematics.................................................... 25

Outline Dimensions....................................................................... 26

Ordering Guide .......................................................................... 27

Rev. 0 | Page 2 of 28

Data Sheet ADP5023

SPECIFICATIONS

GENERAL SPECIFICATIONS

V

= V

AVI N

IN1

= 2.3 V to 5.5 V; V

IN2

typical specifications, unless otherwise noted.

Table 1.

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

INPUT VOLTAGE RANGE V THERMAL SHUTDOWN

Threshold TSSD T

Hysteresis TS

START-UP TIME1

BUCK1, LDO t

BUCK2 t

EN1, EN2, EN3, MODE INPUTS

Input Logic High VIH 1.1 V

Input Logic Low VIL 0.4 V

Input Leakage Current V

INPUT CURRENT

All Channels Enabled I

All Channels Disabled I

VIN1 UNDERVOLTAGE LOCKOUT

High UVLO Input Voltage Rising UVLO

High UVLO Input Voltage Falling UVLO

Low UVLO Input Voltage Rising UVLO

Low UVLO Input Voltage Falling UVLO

1

Start-up time is defined as the time from EN1 = EN2 = EN3 from 0 V to V

shorter for individual channels if another channel is already enabled. See the section for more information. Typical Performance Characteristics

= 1.7 V to 5.5 V; TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for

IN3

, V

AVIN

SD-HYS

START1

START2

I-LEAKAGE

STBY-NOSW

SHUTDOWN

2.3 5.5 V

IN1

IN2

rising 150 °C

J

20 °C

250 µs 300 µs

0.05 1 µA

No load, no buck switching 108 175 µA

T

VIN1RISE

VIN1FALL

VIN1RISE

VIN1FALL

= −40°C to +85°C 0.3 1 µA

J

3.9 V

3.1 V

2.275 V

1.95 V

to VOUT1, VOUT2, and VOUT3 reaching 90% of their nominal level. Start-up times are

AVIN

Rev. 0 | Page 3 of 28

ADP5023 Data Sheet

BUCK1 AND BUCK2 SPECIFICATIONS

V

= V

AVI N

IN1

specifications, unless otherwise noted.

Table 2.

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

OUTPUT CHARACTERISTICS

Output Voltage Accuracy V Line Regulation

Load Regulation

VOLTAGE FEEDBACK V OPERATING SUPPLY CURRENT MODE = ground

BUCK1 Only IIN

BUCK2 Only IIN

BUCK1 and BUCK2 IIN

PSM CURRENT THRESHOLD I SW CHARACTERISTICS

SW On Resistance R R R R

Current Limit I ACTIVE PULL-DOWN R OSCILLATOR FREQUENCY fSW 2.5 3.0 3.5 MHz

1

All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).

= 2.3 V to 5.5 V; TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical

IN2

OUT1

(∆V (∆V

FB1

1

, V

PWM mode; I

OUT2

OUT1/VOUT1

OUT2/VOUT2

OUT1/VOUT1

OUT2/VOUT2

, V

)/∆V )/∆V

)/∆I )/∆I

Models with adjustable outputs 0.485 0.5 0.515 V

FB2

PWM mode −0.05 %/V

,

IN1

IN2

PWM mode; I

,

OUT1

OUT2

= 0 mA, device not switching, all

I

LOAD 1

= I

LOAD 1

LOAD

= 0 mA to 800 mA −3 +3 %

LOAD 2

= 0 mA to 800 mA −0.1 %/A

44 A

other channels disabled

= 0 mA, device not switching, all

I

LOAD 2

55 A

other channels disabled I

LOAD 1

= I

= 0 mA, device not switching,

LOAD 2

67 A

LDO channels disabled

PSM to PWM operation 100 mA

PSM

V

PFET

V

NFET

V

PFET

V

NFET

, I

LIMIT1

LIMIT2

Channel disabled 75 Ω

PDWN-B

= V

= 3.6 V 155 240 mΩ

IN1

IN2

= V

= 3.6 V 205 310 mΩ

IN1

IN2

= V

= 5.5 V 162 204 mΩ

IN1

IN2

= V

= 5.5 V 137 243 mΩ

IN1

IN2

pFET switch peak current limit 1600 1950 2300 mA

Rev. 0 | Page 4 of 28

Data Sheet ADP5023

LDO SPECIFICATIONS

V

= (V

IN3

specifications, and T

Table 3.

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

INPUT VOLTAGE RANGE V OPERATING SUPPLY CURRENT

Bias Current per LDO2 I I I

Total System Input Current

LDO Only I

OUTPUT CHARACTERISTICS

Output Voltage Accuracy

Line Regulation I

Load Regulation3 VOLTAGE FEEDBACK DROPOUT VOLTAGE4 V (∆V (∆V CURRENT-LIMIT THRESHOLD5 I ACTIVE PULL-DOWN R OUTPUT NOISE

Regulator LDO NOISE POWER SUPPLY REJECTION

RATIO

Regulator LDO 10 kHz, V

100 kHz, V

1 MHz, V

1

All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).

2

This is the input current into VIN3, which is not delivered to the output load.

3

Based on an endpoint calculation using 1 mA and 300 mA loads.

4

Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only to output voltages

above 1.7 V.

5

Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V

output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V.

+ 0.5 V) or 1.7 V (whichever is greater) to 5.5 V; CIN = C

OUT3

= 25°C for typical specifications, unless otherwise noted.1

A

1.7 5.5 V

IN3

I

VIN3BIAS

IIN

OUT3

Includes all current into AVIN, VIN1, VIN2, and VIN3

OUT3

V

100 µA < I

OUT3

V

FB3

V

DROPOUT

OUT3/VOUT3

LIMIT3

PDWN-L

)/∆V )/∆I

335 600 mA

Channel disabled 600 Ω

10 Hz to 100 kHz, V

LDO

I

OUT3

0.485 0.5 0.515 V

OUT3

V

IN3

OUT3

V

OUT3

PSRR

= 1 µF; TJ = −40°C to +125°C for minimum/maximum

OUT

= 0 µA 10 30 µA = 10 mA 60 100 µA = 300 mA 165 245 µA

= 0 µA, all other channels disabled 53 µA

< 300 mA −3 +3 %

OUT3

= 1 mA −0.03 +0.03 %/ V = 1 mA to 300 mA 0.001 0.003 %/mA

= 3.3 V, I = 2.5 V, I = 1.8 V, I

IN3

= 300 mA 75 140 mV

OUT3

= 300 mA 100 mV

OUT3

= 300 mA 180 mV

OUT3

= 3.3 V, V

IN3

= 3.3 V, V

= 5 V, V

IN3

OUT3

= 2.8 V, I

OUT3

= 2.8 V, I

= 2.8 V 100 µV rms

OUT3

= 1 mA 60 dB

OUT3

= 1 mA 62 dB

OUT3

= 1 mA 63 dB

OUT3

INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS

TA = −40°C to +125°C, unless otherwise specified.

Table 4.

Parameter Symbol Min Typ Max Unit

SUGGESTED INPUT AND OUTPUT CAPACITANCE

BUCK1, BUCK2 Input Capacitor C

BUCK1, BUCK2 Output Capacitor C

LDO1 Input and Output Capacitor C CAPACITOR ESR R

1

The minimum input and output capacitance should be greater than 0.70 µF over the full range of operating conditions. The full range of operating conditions in

the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R- and X5R-type capacitors are recommended; Y5V and Z5U capacitors are not recommended for use because of their poor temperature and dc bias characteristics.

Rev. 0 | Page 5 of 28

, C

MIN1

MIN3

ESR

4.7 40 µF

MIN2

, C

10 40 µF

MIN2

, C

0.70 µF

MIN4

0.001 1 Ω

ADP5023 Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

AVIN to AGND −0.3 V to +6 V VIN1, VIN2 to AVIN −0.3 V to +0.3 V PGND1, PGND2 to AGND −0.3 V to +0.3 V VIN3, VOUT1, VOUT2, VOUT3, FB1,

FB2, FB3, EN1, EN2, EN3, MODE to

AGND VOUT3 to AGND −0.3 V to (VIN3 + 0.3 V) SW1 to PGND1 −0.3 V to (VIN1 + 0.3 V) SW2 to PGND2 −0.3 V to (VIN2 + 0.3 V) Storage Temperature Range −65°C to +150°C Operating Junction Temperature

Range Soldering Conditions JEDEC J-STD-020

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

For detailed information on power dissipation, see the Power Dissipation and Thermal Considerations section.

−0.3 V to (AVIN + 0.3 V)

−40°C to +125°C

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.

Table 6. Thermal Resistance

Package Type θJA θJC Unit

24-Lead, 0.5 mm pitch LFCSP 35 3 °C/W

ESD CAUTION

Rev. 0 | Page 6 of 28

ADP5023

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AGND

EN3

VIN3

VOUT3

21

10

VOUT1

FB3

20

19

11

12

FB1

EN1

THE EX

18

AGND

AVIN

17

VIN1

16

SW

1

15

PGND1

14

MODE

13

POSED PAD

09889-002

24

23

22

1

AGND

2

3

VIN2

SW

PGND2

NC

NOTES

1. NC = NO CO

2. IT IS RECOMMENDED THAT BE SOLDERED TO

ADP5023

2

TOP VIEW

4

(Not to Scale)

5

6

9

8

7

FB2

EN2

VOUT2

NNECT. DO NOT CONNECT TO THIS PIN.

THE GROUND PLANE.

Figure 2. Pin Configuration—View from Top of Die

Table 7. Pin Function Descriptions

Pin No. Mnemonic Description

1 AGND Analog Ground. 2 AGND Analog Ground. 3 VIN2 BUCK2 Input Supply (2.3 V to 5.5 V). Connect VIN2 to VIN1 and AVIN. 4 SW2 BUCK2 Switching Node. 5 PGND2 Dedicated Power Ground for BUCK2. 6 NC No Connect. Leave this pin unconnected. 7 EN2 BUCK2 Enable Pin. High level turns on this regulator, and low level turns it off. 8 FB2

BUCK2 Feedback Input. For device models with adjustable output voltage, connect this pin to the middle of the

BUCK2 resistor divider. For device models with fixed output voltage, leave this pin unconnected. 9 VOUT2 BUCK2 Output Voltage Sensing Input. Connect VOUT2 to the top of the capacitor on VOUT2. 10 VOUT1 BUCK1 Output Voltage Sensing Input. Connect VOUT1 to the top of the capacitor on VOUT1. 11 FB1

BUCK1 Feedback Input. For device models with adjustable output voltage, connect this pin to the middle of the

BUCK1 resistor divider. For device models with fixed output voltage, leave this pin unconnected. 12 EN1 BUCK1 Enable Pin. High level turns on this regulator, and low level turns it off. 13 MODE BUCK1/BUCK2 Operating Mode. MODE = high: forced PWM operation. MODE = low: auto PWM/PSM operation. 14 PGND1 Dedicated Power Ground for BUCK1. 15 SW1 BUCK1 Switching Node 16 VIN1 BUCK1 Input Supply (2.3 V to 5.5 V). Connect VIN1 to VIN2 and AVIN. 17 AVIN Analog Input Supply (2.3 V to 5.5 V). Connect AVIN to VIN1 and VIN2. 18 AGND Analog Ground. 19 FB3

LDO Feedback Input. For device models with adjustable output voltage, connect this pin to the middle of the LDO

resistor divider. For device models with fixed output voltage, leave this pin unconnected. 20 VOUT3 LDO Output Voltage. 21 VIN3 LDO Input Supply (1.7 V to 5.5 V). 22 EN3 LDO Enable Pin. High level turns on this regulator, and low level turns it off. 23 AGND Analog Ground. 24 AGND Analog Ground. EPAD (EP) Exposed Pad. It is recommended that the exposed pad be soldered to the ground plane.

Rev. 0 | Page 7 of 28

ADP5023 Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

V

= V

IN1

IN2

= 3.6 V, TA = 25°C, unless otherwise noted.

IN3

140

120

100

80

60

40

QUIESCENT CURRENT (µA)

20

0

2.3 2.8 3.3 3.8 4.3 4.8 5.3

INPUT VOLTAGE (V)

Figure 3. System Quiescent Current vs. Input Voltage, V

V

4

2

1

3

= 1.8 V, V

OUT2

T

SW

IOUT

VOUT

EN

= 1.2 V, V

OUT3

= 3.3 V, All Channels Unloaded

OUT4

OUT1

= 3.3 V,

3.35

3.33

3.31

(V)

OUT

V

3.29

3.27

3.25 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

09889-139

I

OUT

(A)

Figure 6. BUCK1 Load Regulation Across Temperature, V

VIN = 4.2V, +85°C VIN = 4.2V, +25°C VIN = 4.2V, –40°C

= 3.3 V,

OUT1

09889-058

Auto Mode

(V)

OUT

V

1.864

1.844

1.824

1.804

1.784

VIN = 3.6V, +85°C

VIN = 3.6V, +25°C VIN = 3.6V, –40°C

CH1 2.00V CH3 5.00V

Figure 4. BUCK1 Startup, V

T

4

2

1

3

CH1 2.00V CH3 5.00V

SW

IOUT

VOUT

EN

Figure 5. BUCK2 Startup, V

CH2 50.0mA Ω

CH4 5.00V

CH2 50.0mA Ω

CH4 5.00V

M 40.0µs A CH3 2. 2V

T 11. 20%

= 1.8 V, I

OUT1

M 40.0µs A CH3 2.2V

T 11. 20%

= 3.3 V, I

OUT2

OUT1

OUT2

= 5 mA

= 10 mA

09889-021

09889-020

Rev. 0 | Page 8 of 28

1.764 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

I

OUT

(A)

Figure 7. BUCK2 Load Regulation Across Temperature, V

Auto Mode

0.799

0.798

0.797

0.796

0.795

(V)

0.794

OUT

V

0.793

0.792

0.791

0.790

0.789 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

I

OUT

(A)

VIN = 3.6V, +85°C VIN = 3.6V, +25°C VIN = 3.6V, –40°C

Figure 8. BUCK1 Load Regulation Across Input Voltage, V

PWM Mode

OUT2

OUT1

= 1.8 V,

= 3.3 V,

09889-057

09889-054

Data Sheet ADP5023

C

100

90

80

70

60

50

40

EFFICIENCY (%)

30

20

10

0

0.0001 0.001 0.01 0.1 1

I

OUT

(A)

VIN = 3.9V

VIN = 4.2V

VIN = 5.5V

Figure 9. BUCK1 Efficiency vs. Load Current, Across Input Voltage,

= 3.3 V, Auto Mode

V

OUT1

100

90

80

70

60

50

40

EFFICIENCY (%)

30

20

10

0

0.001 0.01 0.1 1

I

OUT

(A)

VIN = 3.9V

VIN = 4.2V

VIN = 5.5V

Figure 10. BUCK1 Efficiency vs. Load Current, Across Input Voltage,

= 3.3 V, PWM Mode

V

OUT1

100

90

80

70

60

50

40

EFFICIENCY (%)

30

20

10

0

0.001 0.01 0.1 1

I

OUT

(A)

VIN = 2.3V VIN = 3.6V VIN = 4.2V VIN = 5.5V

Figure 11. BUCK2 Efficiency vs. Load Current, Across Input Voltage,

= 1.8 V, Auto Mode

V

OUT2

09889-038

09889-039

09889-036

100

90

80

70

60

50

40

EFFICIENCY (%)

30

20

10

0

0.001 0.01 0.1 1

I

OUT

(A)

VIN = 2.4V V

= 3.6V

IN

V

= 4.5V

IN

V

= 5.5V

IN

Figure 12. BUCK2 Efficiency vs. Load Current, Across Input Voltage,

= 1.8 V, PWM Mode

V

OUT2

100

90

80

70

60

50

40

EFFICIENCY (%)

30

20

10

0

0.001 0.01 0.1 1

I

OUT

(A)

VIN = 2.3V V

= 3.6V

IN

V

= 4.2V

IN

V

= 5.5V

IN

Figure 13. BUCK1 Efficiency vs. Load Current, Across Input Voltage,

= 0.8 V, Auto Mode

V

OUT1

100

90

80

70

60

Y (%)

50

40

EFFICIEN

30

20

10

0

0.001 0.01 0.1 1 I

OUT

(A)

VIN = 2.3V V

= 3.6V

IN

V

= 4.2V

IN

V

= 5.5V

IN

Figure 14. BUCK1 Efficiency vs. Load Current, Across Input Voltage,

= 0.8 V, PWM Mode

V

OUT1

09889-035

09889-034

09889-035

Rev. 0 | Page 9 of 28

ANALOG DEVICES ADP5023 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

TYPICAL APPLICATION CIRCUIT

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

GENERAL SPECIFICATIONS

BUCK1 AND BUCK2 SPECIFICATIONS

LDO SPECIFICATIONS

INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS