Analog Devices ADP3820 a Datasheet

Lithium-Ion

C1

10mF

+
–

R1

10kV

V

IN

+5V

R

S

50mV

22mF

V

OUT

Li-Ion
BATTERY

I

O

= 1A

NDP6020P

GND

IS GATE

V

IN

SD

V

OUT

ADP3820-xx

a

FEATURES
ⴞ1% Total Accuracy
630 ␮A Typical Quiescent Current
Shutdown Current: 1 ␮A (Typical)
Stable with 10 ␮F Load Capacitor

4.5 V to 15 V Input Operating Range
Integrated Reverse Leakage Protection
6-Lead SOT-23-6 and 8-Lead SO-8 Packages
Programmable Charge Current
–20ⴗC to +85ⴗC Ambient Temperature Range
Internal Gate-to-Source Protective Clamp

APPLICATIONS
Li-Ion Battery Chargers
Desktop Computers
Hand-Held Instruments
Cellular Telephones
Battery Operated Devices

Battery Charger

ADP3820

FUNCTIONAL BLOCK DIAGRAM

V

SD

V

REF

ADP3820

BIAS

+
–

50mV

GND

IN

IS

GATE

V

OUT

GENERAL DESCRIPTION

The ADP3820 is a precision single cell Li-Ion battery charge
controller that can be used with an external Power PMOS de­vice to form a two-chip, low cost, low dropout linear battery
charger. It is available in two voltage options to accommodate
Li-Ion batteries with coke or graphite anodes. The ADP3820’s

high accuracy (±1%) low shutdown current (1 µA) and easy

charge current programming make this device especially attrac­tive as a battery charge controller.

Charge current can be set by an external resistor. For example,

50 mΩ of resistance can be used to set the charge current to

1 A. Additional features of this device include foldback current
limit, overload recovery, and a gate-to-source voltage clamp to
protect the external MOSFET. The proprietary circuit also
minimizes the reverse leakage current from the battery if the
input voltage of the charger is disconnected. This feature elimi­nates the need for an external serial blocking diode.

The ADP3820 operates with a wide input voltage range from

4.5 V to 15 V. It is specified over the industrial temperature

range of –20°C to +85°C and is available in the ultrasmall

6-lead surface mount SOT-23-6 and 8-lead SOIC packages.

Figure 1. Li-Ion Charger Application Circuit

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1999

1

WARNING!

ESD SENSITIVE DEVICE

ADP3820–SPECIFICATIONS

(VIN = [V

Parameter Conditions Symbol Min Typ Max Units

INPUT VOLTAGE V

OUTPUT VOLTAGE ACCURACY V

IN

= V

VSD = 2 V

QUIESCENT CURRENT

Shutdown Mode V

= 0 V I

SD

Normal Mode VSD = 2 V I

GATE TO SOURCE CLAMP VOLTAGE 6 10 V

GATE DRIVE MINIMUM VOLTAGE

2

GATE DRIVE CURRENT (SINK/SOURCE) 1 mA

+ 1 V] TA = –20ⴗC to +85ⴗC, unless otherwise noted)

OUT

IN

+ 1 V to 15 V V

OUT

OUT

GND

GND

4.5 15 V

–1 +1 %

115µA
630 800 µA

0.7 V



GAIN




CURRENT LIMIT THRESHOLD VOLTAGE VIN – V

LOAD REGULATION I



∆

V

GS



∆

V



OUT

IS

= 10 mA to 1 A,

OUT

Circuit of Figure 1 –10 +10 mV

LINE REGULATION V

I

OUT

IN

= V

OUT

= 0.1 A

+ 1 V to 15 V

Circuit of Figure 1 (No Battery) –10 +10 mV

SD INPUT VOLTAGE V

IH

V

IL

SD INPUT CURRENT VSD = 0 V to 5 V I

OUTPUT REVERSE LEAKAGE CURRENT VIN = Floating I

NOTES

1

All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC).

2

Provided gate-to-source clamp voltage is not exceeded.

Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS*

Input Voltage, V

Enable Input Voltage . . . . . . . . . . . . . . . 0.3 V to (V

Operating Ambient Temperature Range . . . . –20°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

, SO-8 Package . . . . . . . . . . . . . . . . . . . . . . . . 150°C/W

θ

JA

, SOT-23-6 Package . . . . . . . . . . . . . . . . . . . . 230°C/W

θ

JA

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . .+300°C

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . .+215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C

ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV

*This is a stress rating only; operation beyond these limits can cause the device

to be permanently damaged.

␣ . . . . . . . . . . . . . . . . . . . . . . . . . . . . ⴙ20 V

IN

+ 0.3 V)

IN

Model Output Option* Code

ADP3820ART-4.1 4.1 V RT-6 (SOT-23-6) BAC
ADP3820ART-4.2 4.2 V RT-6 (SOT-23-6) BBC
ADP3820AR-4.1 4.1 V SO-8
ADP3820AR-4.2 4.2 V SO-8

*SOT = Surface Mount Package. SO = Small Outline.

Contact the factory for availability of other output voltage options.

V

SD

SD

DISCH

ORDERING GUIDE

Voltage Package Marking

80 dB

40 75 mV

2.0 V

0.4 V

–15 +15 µA

35 µA

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADP3820 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

–2– REV. A

ADP3820

PIN FUNCTION DESCRIPTIONS

Pin Pin
SOT-23-6 SO-8 Name Function

18SD Shutdown. Pulling this pin low

will disable the output.

2 7 GND Device Ground. This pin should

be tied to system ground closest
to the load.

35V

OUT

Output Voltage Sense. This pin
is connected to the MOSFET’s
drain and directly to the load for
optimal load regulation. Bypass

to ground with a 10 µF or larger

capacitor.

4 3 GATE Gate drive for the external

MOSFET.

54V

IN

Input Voltage. This is also the
positive terminal connection of
the current sense resistor.

6 1 IS Current Sense. Used to sense the

input current by monitoring the
voltage across the current sense
resistor. It is connected to the
more negative terminal of the
resistor as well as the power
MOSFET’s source pin. IS pin
should be tied to the V

pin if

IN

the current limit feature is not
used.

2, 6 NC No Connect.

1

IS

2

NC

3

GATE

V

4

IN

NC = NO CONNECT

PIN CONFIGURATIONS

SO-8 RT-6 (SOT-23-6)

ADP3820

TOP VIEW

(Not to Scale)

8

SD

7

GND

6

NC

5

V

OUT

GND

V

OUT

SD

1

ADP3820

2

TOP VIEW

3

(Not to Scale)

6

5

4

IS
V

IN

GATE

–3–REV. A

ADP3820

–Typical Performance Characteristics

4.110

4.105

4.100

OUTPUT VOLTAGE – V

4.095

4.090

VIN = 5.1V

0 1000200

Figure 2. V

4.110

4.105

4.100

I

LOAD

= 1A

400 600 800

I

– mA

LOAD

OUT

vs. I

(VIN = 5.1 V)*

LOAD

0.760

0.740

0.720

0.700

– mA

0.680

GND

I

0.660

0.640

0.620

0.900

0.850

– mA

0.800

GND

I

I

= 10mA

LOAD

5157

Figure 5. I

I

= 1A

LOAD

91113

INPUT VOLTAGE – V

vs. VIN (I

GND

= 10 mA)*

LOAD

OUTPUT VOLTAGE – V

4.095

4.090

4.110

4.105

4.100

OUTPUT VOLTAGE – V

4.095

4.090

5157

Figure 3. V

I

= 10mA

LOAD

5157

Figure 4. V

91113

INPUT VOLTAGE – V

vs. VIN (I

OUT

91113

INPUT VOLTAGE – V

vs. VIN (I

OUT

LOAD

= 10 mA)*

LOAD

= 1 A)*

0.750

0.700
5157

Figure 6. I

1.200
VIN = 5.1V

1.100

1.000

0.900

– mA

GND

0.800

I

0.700

0.600

0.500

0.001 1000

Figure 7. I

9

INPUT VOLTAGE – V

vs. VIN (I

GND

I

LOAD

vs. I

GND

11 13

LOAD

100.1

– mA

(VIN = 5.1 V)*

LOAD

= 1 A)*

*Reference Figure 1.

–4– REV. A

ADP3820

1.100
VIN = 5.1V

= 10mA

I

1.000

0.900

– mA

0.800

GND

I

0.700

0.600

0.500

LOAD

–40 80–20

0

20 40 60

TEMPERATURE – 8C

Figure 8. Quiescent Current vs. Temperature*

4.5
I

= 10mA

LOAD

4.0

3.5

3.0

2.5

2.0

1.5

OUTPUT VOLTAGE – V

1.0

0.5

0

00123454321

INPUT VOLTAGE – V

Figure 9. Power-Up/Power-Down*

4.230

4.210

4.190

4.170

4.150

4.130

OUTPUT VOLTAGE – V

4.110

4.090

4.070
–40 80–20

Figure 11. V

0

–10

–20

–30

–40
–50

PSRR – dB

–60

–70

–80

–90

–100

V

= 4.2V

OUT

V

= 4.1V

OUT

0

20 40 60

TEMPERATURE – 8C

vs. Temperature, VIN = 5.1 V, I

OUT

C

= 10mF

LOAD

= 1mA

I

LOAD

100 1k 10k 100k

10 1M

FREQUENCY – Hz

LOAD

Figure 12. Ripple Rejection*

= 10 mA*

10M

7.0

INPUT

5.5

VOLTAGE – V

I

= 10mA

LOAD

= 10mF

C

OUT

4.2

4.1

OUTPUT

VOLTAGE – V

4.0

Figure 10. Line Transient Response (10 µF Output Cap)*

5.000

VIN = 5.1V

= 0.5V

R

4.000

3.000

2.000

OUTPUT VOLTAGE – V

1.000

0.000

S

0 14020

40 60 80 100 120

I

– mA

LOAD

Figure 13. Current Limit Foldback*

–5–REV. A

ADP3820

APPLICATION INFORMATION

The ADP3820 is very easy to use. A P-channel power MOS­FET and a small capacitor on the output is all that is needed to
form an inexpensive Li-Ion battery charger. The advantage of
using the ADP3820 controller is that it can directly drive a
PMOS FET to provide a regulated output current until the
battery is charged. When the specified battery voltage is reached,
the charge current is reduced and the ADP3820 maintains the
maximum specified battery voltage accurately.

When fully charged, the circuit in Figure 1 works like a well
known linear regulator, holding the output voltage within the
specified accuracy as needed by single cell Li-Ion batteries. The
output is sensed by the V

pin. When charging a discharged

OUT

battery, the circuit maintains a set charging current determined
by the current sense resistor until the battery is fully charged,
then reduces it to a trickle charge to keep the battery at the
specified voltage. The voltage drop across the R

current sense

S

resistor is sensed by the IS input of the ADP3820. At minimum
battery voltage or at shorted battery, the circuit reduces this
current (foldback) to limit the dissipation of the FET (see Fig­ure 13). Both the V

input and V

IN

sense pins of the IC need

OUT

to be bypassed by a suitable bypass capacitor.

A 6 V gate-to-source voltage clamp is provided by the ADP3820
to protect the MOSFET gates at higher source voltages. The
ADP3820 also has a TTL SD input, which may be connected to
the input voltage to enable the IC. Pulling it to low or to
ground will disable the FET-drive.

Design Approach

Due to the lower efficiency of Linear Regulator Charging, the
most important factor is the thermal design and cost, which is
the direct function of the input voltage, output current and
thermal impedance between the MOSFET and the ambient
cooling air. The worse-case situation is when the battery is
shorted since the MOSFET has to dissipate the maximum power.

A tradeoff must be made between the charge current, cost and
thermal requirements of the charger. Higher current requires a
larger FET with more effective heat dissipation leading to a
more expensive design. Lowering the charge current reduces
cost by lowering the size of the FET, possibly allowing a smaller
package such as SOT-23-6. The following designs consider both
options. Furthermore, each design is evaluated under two input
source voltage conditions.

Regarding input voltage, there are two options:

A. The input voltage is preregulated, e.g., 5 V ± 10%

B. The input voltage is not a preregulated source, e.g., a wall

plug-in transformer with a rectifier and capacitive filter.

Higher Current Option

A. Preregulated Input Voltage (5 V ⴞ 10%)

For the circuit shown in Figure 1, the required θ

thermal

JA

impedance can be calculated as follows: if the FET data sheet
allows a max FET junction temperature of T

= 150°C, then

JMAX

at 50°C ambient and at convection cooling, the maximum al­lowed ∆T junction temperature rise is thus, T

JMAX

– T

AMAX

=

150°C – 50°C = 100°C.

The maximum current for a shorted or discharged battery is
reduced from the set charge current by a multiplier factor shown
in Figure 13 due to the foldback current limiting feature of the

ADP3820. This k factor between V

of 0 V to about 2.5 V is:

O

k ~ 0.65.

θ

= ∆T/(I

JA

× k × VIN) = 100/(1 × 0.65 × 5) = 30.7

O

°

C/W

This thermal impedance can be realized using the transistor

shown in Figure 1 when surface mounted to a 40 × 40 mm

double-sided PCB with many vias around the tab of the surface­mounted FET to the backplane of the PCB. Alternatively, a
TO-220 packaged FET mounted to a heatsink could be used.

The θ or thermal impedance of a suitable heatsink is calculated

below:

θ < (θ

– θ

) = 30.7 – 2 = +28.7°C/W

JA

JC

Where the θ

, or junction-to-case thermal impedance of the

JC

FET can be read from the FET data sheet. A low cost such

heatsink is type PF430 made by Thermalloy, with a θ =
+25.3°C/W.

The current sense resistor for this application can be simply
calculated:

R

Where V

= VS /I

S

is specified on the data sheet as current limit threshold

S

= 0.05/1 = 50 mΩ

O

voltage at 40 mV–75 mV. For battery charging applications, it
is adequate to use the typical 50 mV midvalue.

B. Nonpreregulated Input Voltage

If the input voltage source is, for example, a rectified and
capacitor-filtered secondary voltage of a small wall plug-in
transformer, the heatsinking requirement is more demanding.
The V

should be specified 5 V, but at the lowest line volt-

INMIN

age and full load current. The required thermal impedance can
be calculated the same way as above, but here we have to use
the maximum output rectified voltage, which can be substan­tially higher than 5 V, depending on transformer regulation and
line voltage variation. For example, if V

θ

= ∆T/(I

JA

× k × V

O

) = 100/(1 × 0.65 × 10) = +15.3°C/W

INMAX

INMAX

is 10 V

The θ suitable heatsink thermal impedance:

θ < θ

– θJC = 15.3 – 2 = 13.3°C/W

JA

A low cost heatsink is Type 6030B made by Thermalloy, with a

θ = +12.5°C/W.

Lower Current Option

A. Preregulated Input Voltage (5 V ⴞ 10%)

If lower charging current is allowed, the θ

value can be increased,

JA

and the system cost decreased. The lower cost is assured by
using an inexpensive MOSFET with, for example, a NDT452P

in a SOT-23-6 package mounted on a small 40 × 40 mm area

on double-sided PCB. This provides a convection cooled ther-

mal impedance of θ

= +55°C/W, presuming many vias are

JA

used around the FET to the backplane. Allowing a maximum

FET junction temperature of +150°C, at +50°C ambient, and

at convection cooling the maximum allowed heat rise is thus

150°C–50°C = 100°C.

The maximum foldback current allowed:

I

= ∆T/(θ × VIN) = 100/(55 × 5) = 0.33 A

FB

Thus the full charging current:

I

OUTMAX

= IFB/k = 0.5 A

k is calculated in the above example.

–6– REV. A

ADP3820

The current sense resistor for this application:

R

= VS/IO = 0.05/0.5 = 100 m

S

Ω

FET Selection

The type and size of the pass transistor are determined by the
threshold voltage, input-output voltage differential and load
current. The selected PMOS must satisfy the physical and ther­mal design requirements. To ensure that the maximum V

GS

provided by the controller will turn on the FET at worst case
conditions, (i.e., temperature and manufacturing tolerances) the
maximum available V

must be determined. Maximum VGS is

GS

calculated as follows:

V

= VIN – VBE – I

GS

OUTMAX

× R

S

where

I

OUTMAX

R

S

V

BE

= Maximum Output Current
= Current Sense Resistor
~ 0.7 V (Room Temperature)
~ 0.5 V (Hot)
~ 0.9 V (Cold)

For example:

V

= 5 V, and I

IN

V

= 5 V – 0.7 V – 1 A × 50 m

GS

If V

< 5 V, logic level FET should be considered.

GS

> 5 V, either logic level or standard MOSFET can be

If V

GS

OUTMAX

= 1 A,

Ω

= 4.25 V

used.

The difference between V

and VO (VDS) must exceed the

IN

voltage drop due to the sense resistor plus the ON-resistance
of the FET at the maximum charge current. The selected
MOSFET must satisfy these criteria; otherwise, a different pass
device should be used.

V

= VIN – VO = 5 V – 4.2 V = 0.8 V

DS

The maximum R
and Drain-to-Source voltage (V

required at the available gate drive (VDR)

DS(ON)

R

DS(ON)

) is:

DS

= VDS/I

OUTMAX

From the Drain-to Source current vs. Drain-to-Source voltage
vs. gate drive graph off the MOSFET data sheet, it can be de­termined if the above calculated R

is higher than the graph

DS(ON)

indicates. However, the value read from the MOSFET data
sheet graph must be adjusted based on the junction temperature
of the MOSFET. This adjustment factor can be obtained from
the normalized R

vs. junction temperature graph in the

DS(ON)

MOSFET data sheet.

External Capacitors

The ADP3820 is stable with or without a battery load, and
virtually any good quality output filter capacitors can be used
(anyCAP™), independent of the capacitor’s minimum ESR
(Effective Series Resistance) value. The actual value of the
capacitor and its associated ESR depends on the g

and capaci-

m

tance of the external PMOS device. A 10 µF tantalum or alumi-

num electrolytic capacitor at the output is sufficient to ensure
stability for up to a 10 A output current.

Shutdown Mode

Applying a TTL high signal to the SD pin or tying it to the
input pin will enable the output. Pulling this pin low or tying
it to ground will disable the output. In shutdown mode, the
controller’s quiescent current is reduced to less than 1 µA.

Gate-to-Source Clamp

A 6 V gate-to-source voltage clamp is provided by the ADP3820 to
protect most MOSFET gates in the event the V

> VGS allowed

IN

and the output is suddenly shorted to ground. This allows use of
the new, low R

DS(ON)

MOSFETs.

Short Circuit Protection

The power FET is protected during short circuit conditions
with a foldback type of current limiting that significantly re­duces the current. See Figure 13 for foldback current limit
information.

Current Sense Resistor

Current limit is achieved by setting an appropriate current sense
resistor (R
limit sense resistor, R

) across the current limit threshold voltage. Current

S

, is calculated as shown above. Proper

S

derating is advised to select the power dissipation rating of the
resistor.

The simplest and cheapest sense resistor for high current appli­cations, (i.e., Figure 1) is a PCB trace. However, the tempera­ture dependence of the copper trace and the thickness tolerances of
the trace must be considered in the design. The resistivity of

copper has a positive temperature coefficient of +0.39%/°C.

Copper’s Tempco, in conjunction with the proportional-to-

absolute temperature (±0.3%) current limit voltage, can provide

an accurate current limit. Table I provides the typical resistance
values for PCB copper traces. Alternately, an appropriate sense
resistor, such as surface mount sense resistors, available from
KRL, can be used.

Table I. Printed Circuit Copper Resistance

Conductor Conductor Resistance
Thickness Width/Inch m⍀/In

2

1/2oz/ft

(18 µm) 0.025 39.3

0.050 19.7

0.100 9.83

0.200 4.91

0.500 1.97

2

1oz/ft

(35 µm) 0.025 19.7

0.050 9.83

0.100 4.91

0.200 2.46

0.500 0.98

2

2oz/ft

(70 µm) 0.025 9.83

0.050 4.91

0.100 2.46

0.200 1.23

0.500 0.49

2

3oz/ft

(106 µm) 0.025 6.5

0.050 3.25

0.100 1.63

0.200 0.81

0.500 0.325

anyCAP is a trademark of Analog Devices, Inc.

–7–REV. A

ADP3820

PCB Layout Issues

For optimum voltage regulation, place the load as close as pos­sible to the device’s V

and GND pins. It is recommended to

OUT

use dedicated PCB traces to connect the MOSFET’s drain to
the positive terminal and GND to the negative terminal of the
load to avoid voltage drops along the high current carrying PCB
traces.

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

6-Lead Plastic Surface Mount Package

RT-6 (SOT-23-6)

0.122 (3.10)

0.106 (2.70)

2

BSC

0.020 (0.50)

0.010 (0.25)

4 5 6

0.118 (3.00)

0.098 (2.50)

3

0.037 (0.95) BSC

0.057 (1.45)

0.035 (0.90)

SEATING
PLANE

0.071 (1.80)

0.059 (1.50)

0.051 (1.30)

0.035 (0.90)

1

PIN 1

0.075 (1.90)

0.006 (0.15)

0.000 (0.00)

If PCB layout is used as heatsink, adding many vias around the
power FET helps conduct more heat from the FET to the back­plane of the PCB, thus reducing the maximum FET junction
temperature.

108

0.022 (0.55)

0.009 (0.23)

0.003 (0.08)

08

0.014 (0.35)

C2986a–2–9/99

0.1574 (4.00)

0.1497 (3.80)

PIN 1

0.0098 (0.25)

0.0040 (0.10)
SEATING

8-Lead Narrow Body Package

SO-8

0.1 968 (5.00)

0.1 890 (4.80)

85

0.0500 (1.27)

PLANE

41

BSC

0.0192 (0.49)

0.0138 (0.35)

0.2440 (6.20)

0.2284 (5.80)

0.0688 (1.75)

0.0532 (1.35)

0.0098 (0.25)

0.0075 (0.19)

0.0196 (0.50)

0.0099 (0.25)

88

0.0500 (1.27)

08

0.0160 (0.41)

3 458

PRINTED IN U.S.A.

–8–

REV. A