Analog Devices ADP3522 Datasheet

GSM Power Management System

P

ADP3522

FEATURES

FUNCTIONAL BLOCK DIAGRAM

Handles all GSM Baseband Power Management
6 LDOs Optimized for Specific GSM Subsystems

VBAT VBAT2

VRTCIN

Li-Ion Battery Charge Function
Optimized for the AD20msp430 Baseband Chipset
Reduced Package Size: 5 mm  5 mm LFCSP-32

APPLICATIONS
GSM/GPRS Handsets

GENERAL DESCRIPTION

WRONKEY

ROWX

PWRONIN

POWER-UP

SEQUENCING

AND

PROTECTION

LOGIC

The ADP3522 is a multifunction power system chip optimized
for GSM/GPRS handsets, especially those based on the Analog
Devices AD20msp430 system solution with 1.8 V digital
baseband processors, such as the AD6525, AD6526, and
AD6528. It contains six LDOs, one to power each of the critical
GSM subblocks. Sophisticated controls are available for power-

TCXOEN

SIMEN

RESCAP

up during battery charging, keypad interface, and RTC alarm.
The charge circuit maintains low current charging during the
initial charge phase and provides an end of charge (EOC) signal
when a Li-Ion battery is being charged. This product also meets
the market trend of reduced size with a new LFCSP package.
Its footprint is only 5 mm  5 mm and yet offers excellent ther­mal performance due to the exposed die attached paddle.

The ADP3522 is specified over the temperature range of
–20°C to +85°C.

CHRDET

EOC

CHGEN

BATSNS

ISENSE

GATEIN

CHRIN

GATEDR

BATTERY

CHARGE

CONTROLLER

ADP3522

SIM

LDO

DIGITAL

CORE LDO

ANALOG

LDO

TCXO

LDO

MEMORY

LDO

RTC

LDO

REF

BUFFER

BATTERY
VOLTAGE

DIVIDER

VSIM

SIMVSEL

VCORE

VAN

VTCXO

VMEM

VRTC

REFOUT

RESET

MVBAT

DGND

AGND

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

ADP3522–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

Parameter Symbol Conditions Min Typ Max Unit

SHUTDOWN SUPPLY CURRENT ICC

VBAT ≤ 2.5 V VBAT = VBAT2 = 2.3 V 15 40 µA
(Deep Discharged Lockout Active)

2.5 V < VBAT ≤ 3.2 V VBAT = VBAT2 = 3.0 V 30 55 µA
(UVLO Active)
VBAT > 3.2 V VBAT = VBAT2 = 4.0 V 45 80 µA

OPERATING GROUND CURRENT IGND VBAT = 3.6 V

VSIM, VCORE, VMEM, VRTC On Minimum Loads 225 300 µA
All LDOs On Minimum Loads 345 450 µA
All LDOs On Maximum Loads 1.0 3.0 % of Max

UVLO ON THRESHOLD VUVLO Rising Edge 3.2 3.3 V

UVLO HYSTERESIS 200 mV

DEEP DISCHARGED LOCKOUT ON VDDLO Falling Edge 2.4 2.75 V

THRESHOLD

DEEP DISCHARGED LOCKOUT 100 mV

HYSTERESIS

INPUT HIGH VOLTAGE V

PWRONIN 1.0 V
TCXOEN, SIMEN, 1.5 V
CHGEN, GATEIN, SIMVSEL

INPUT LOW VOLTAGE V

(PWRONIN, TCXOEN, SIMEN,
CHGEN, SIMVSEL)

PWRONIN Pin Pull-Down Resistor R

INPUT HIGH BIAS CURRENT I

(TCXOEN, SIMEN, CHGEN,
SIMVSEL )

INPUT LOW BIAS CURRENT I

(PWRONIN, TCXOEN, SIMEN,

CHGEN, SIMVSEL)
PWRONKEY INPUT HIGH VOLTAGE V
PWRONKEY INPUT LOW VOLTAGE V
PWRONKEY INPUT PULL-UP 70 100 130 k

RESISTANCE TO VBAT

THERMAL SHUTDOWN 160 ºC

THRESHOLD

THERMAL SHUTDOWN 45 ºC

HYSTERESIS

2

1

IH

IL

PD

IH

IL

IH

IL

(–20C < TA < +85C, VBAT = VBAT2 = 3 V–5.5 V, CVSIM = CVCORE = CVAN =
CVMEM = 2.2 F, VTCXO = 0.22 F, CVRTC = 0.1 F, CVBAT = 10 F, minimum
loads applied on all outputs, unless otherwise noted.)

Load

0.3 V

200 1000 5000 k

1.0 µA

–1.0 µA

0.7  VBAT V

0.3  VBAT V

REV. 0–2–

ADP3522

Parameter Symbol Conditions Min Typ Max Unit

ROWX CHARACTERISTICS

ROWX Output Low Voltage V

ROWX Output High Leakage Current I

OL

IH

SIM CARD LDO (VSIM)

Output Voltage VSIM Line, Load, Temperature 1.70 1.80 1.90 V

Output Voltage VSIM Line, Load, Temperature 2.80 2.85 2.92 V

Line Regulation VSIM 2 mV
Load Regulation VSIM 50 µA ≤ I

Output Capacitor Required for C

O

Stability
Dropout Voltage V

DO

DIGITAL CORE LDO (VCORE)

Output Voltage VCORE Line, Load, Temperature 1.75 1.80 1.85 V
Line Regulation VCORE 2 mV
Load Regulation VCORE 50 µA ≤ I

Output Capacitor Required for C

O

Stability

RTC LDO
REAL-TIME CLOCK LDO/
COIN CELL CHARGER (VRTC)

Maximum Output Voltage VRTC 1 µA ≤ I
Maximum Output Current VRTC = 0.5 V 4.0 mA
Off Reverse Input Current I

Output Capacitor Required for C

L

O

Stability

ANALOG LDO (VAN)

Output Voltage VAN Line, Load, Temperature 2.50 2.55 2.60 V
Line Regulation VAN 2 mV
Load Regulation VAN 50 µA ≤ I

Output Capacitor Required for C

O

Stability
Ripple Rejection VBAT/ f = 217 Hz (t = 4.6 ms) 65 dB

VAN

Output Noise Voltage V

NOISE

Dropout Voltage V

PWRONKEY = Low
I

= 200 µA 0.4 V

OL

PWRONKEY = High
V(ROWX) = 5 V 1 µA

SIMVSEL = Low

SIMVSEL = High

≤ 20 mA 2 mV

LOAD

VBAT = 3.6 V

2.2 µF

VO = V
I

= 20 mA, 35 100 mV

LOAD

INITIAL

– 100 mV,

VSIM = 2.85 V

≤ 100 mA 8 mV

LOAD

VBAT = 3.6 V

2.2 µF

≤ 10 µA1.861.95 2.0 V

LOAD

VRTC = 1.90 V,
VBAT = 1.70 V, T

= 25°C 0.5 µA

A

0.1 µF

≤ 180 mA, 11 mV

LOAD

VBAT = 3.6 V

2.2 µF

3

VBAT = 3.6 V
f = 10 Hz to 100 kHz 80 µV rms

= 180 mA

I

LOAD

VBAT = 3.6 V

O

I

LOAD

= V

= 180 mA

– 100 mV, 160 400 mV

INITIAL

REV. 0

–3–

ADP3522

(–20C < TA < +85C, VBAT = VBAT2 = 3 V–5.5 V, CVSIM = CVCORE = CVAN = CVMEM =

2.2 F, VTCXO = 0.22 F, CVRTC = 0.1 F, CVBAT = 10 F, minimum loads applied on

ELECTRICAL CHARACTERISTICS

Parameter Symbol Conditions Min Typ Max Unit

TCXO LDO (VTCXO)

Output Voltage VTCXO Line, Load, Temperature 2.711 2.75 2.789 V

Line Regulation VTCXO 2 mV

Load Regulation VTCXO 50 µA ≤ I

Output Capacitor Required for C

Stability

Dropout Voltage V

Ripple Rejection VBAT/ f = 217 Hz (t = 4.6 ms) 65 dB

Output Noise Voltage V

MEMORY LDO (VMEM)

Output Voltage-3 VMEM Line, Load, Temperature 2.740 2.80 2.850 V

Output Voltage-1.8 VMEM Line, Load, Temperature 1.80 1.85 1.90 V

Line Regulation VMEM 2 mV

Load Regulation VMEM 50 µA < I

Output Capacitor Required for C

Stability

Dropout Voltage-3 V

REFOUT

Output Voltage VREFOUT Line, Load, Temperature 1.19 1.21 1.23 V

Line Regulation VREFOUT Min Load 0.2 mV

Load Regulation VREFOUT 0 µA < I

Ripple Rejection VBAT/ f = 217 Hz (t = 4.6 ms) 65 75 dB

Maximum Capacitive Load C

Output Noise Voltage V
RESET GENERATOR (RESET)

Output High Voltage V

Output Low Voltage V

Output Current I

Delay Time per Unit Capacitance t

Applied to RESCAP Pin

BATTERY VOLTAGE DIVIDER

Divider Ratio

Divider Impedance at MVBAT Z

Divider Leakage Current TCXOEN = Low 1 µA

Divider Resistance TCXOEN = High 215 300 385 k

1

all outputs, unless otherwise noted.)

LOAD

VBAT = 3.6 V

O

DO

VO = V

= 20 mA

I

LOAD

– 100 mV 160 300 mV

INITIAL

VTCXO VBAT = 3.6 V

NOISE

f = 10 Hz to 100 kHz 80 µV rms
I

= 20 mA, VBAT = 3.6 V

LOAD

LOAD

VBAT = 3.6 V

O

O

I

LOAD

= V

= 150 mA

– 100 mV 160 360 mV

INITIAL

< 50 µA 0.5 mV

LOAD

VBAT = 3.6 V

VREFOUT

O

NOISE

OH

OL

OL/IOH

D

BATSNS/

f = 10 Hz to 100 kHz 40 µV rms

IOH = +500 µAV
IOL = –500 µA0.25V
VOL= 0.25 V, 1 mA
V

OH

= V

MEM

– 0.25 V

TCXOEN = High 2.32 2.35 2.37

MVBAT

O

≤ 20 mA, 2 mV

0.22 µF

< 150 mA 12 mV

2.2 µF

100 pF

– 0.25 V

MEM

0.6 1.2 2.4 ms/nF

59.5 85 110 k

REV. 0–4–

ADP3522

Parameter Symbol Conditions Min Typ Max Unit

BATTERY CHARGER

Charger Output Voltage BATSNS

4.35 V ≤ CHRIN ≤ 10 V

CHGEN = Low, No Load
CHRIN = 10 V 4.155 4.250 V
CHGEN = Low, No Load
0°C < T

< 50°C

A

Load Regulation BATSNS CHRIN = 5 V 15 mV

0 ≤ CHRIN – ISENSE
< Current Limit Threshold

CHGEN = Low

CHRDET On Threshold CHRIN –

VBAT 30 90 150 mV
CHRDET Hysteresis 40 mV
CHRDET Off Delay

4

CHRIN < VBAT 6 ms/nF
CHRIN Supply Current CHRIN = 5 V 0.6 mA
Current Limit Threshold CHRIN –

ISENSE
High Current Limit CHRIN = 5 V DC 142 160 190 mV
(UVLO Not Active) VBAT = 3.6 V

CHGEN = Low
CHRIN = 5 V DC 149 160 180 mV
VBAT = 3.6 V
CHGEN = Low
0°C < T

< 50°C

A

Low Current Limit VBAT = 2 V 20 35 mV
(UVLO Active) CHGEN = Low

CHRIN = 5 V – 10 V
ISENSE Bias Current 200 µA
EOC Signal Threshold

CHRIN –
ISENSE

CHRIN = 5 V DC 14 35 mV

VBAT > 4.0 V

CHGEN = Low
EOC Reset Threshold VBAT CHGEN = Low 3.82 3.96 4.10 V
GATEDR Transition Time t

, t

R

F

CHRIN = 5 V 0.1 1 µs

VBAT > 3.6 V

CHGEN = High, C
GATEDR High Voltage V

OH

CHRIN = 5 V 4.5 V

VBAT = 3.6 V

CHGEN = High

GATEIN = High

= –1 mA

I

OH

GATEDR Low Voltage V

OL

CHRIN = 5 V 0.5 V

VBAT = 3.6 V

CHGEN = High

GATEIN = Low

= 1 mA

I

OL

Output High Voltage V

OH

IOH = –250 µAV

(EOC, CHRDET)

Output Low Voltage V

OL

IOL = 250 µA0.25V

(EOC, CHRDET)

NOTES

1

All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.

2

This feature is intended to protect against catastrophic failure of the device. Maximum allowed operating junction temperature is 125ºC. Operation beyond 125ºC
could cause permanent damage to the device.

3

No isolation diode is present between the charger input and the battery.

4

Delay set by external capacitor on the RESCAP pin.

Specifications subject to change without notice.

3

= 2 nF

L

4.150 4.200 4.250 V

– 0.25 V

MEM

REV. 0

–5–

ADP3522

Y

ABSOLUTE MAXIMUM RATINGS*

Voltage on Any Pin with Respect to

Any GND Pin . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +10 V

Voltage on Any Pin May Not Exceed VBAT, with the Following

Exceptions: CHRIN, BASE, ISENSE

Storage Temperature Range . . . . . . . . . . . . . –65∞C to +150∞C

Operating Ambient Temperature Range . . . . . –20∞C to +85∞C

Maximum Junction Temperature . . . . . . . . . . . . . . . . . 125∞C

, Thermal Impedance (LFCSP 5 mm ⫻ 5 mm)

␪

JA

4-Layer JEDEC PCB . . . . . . . . . . . . . . . . . . . . . . . . . . 32∞C/W

2-Layer SEMI PCB . . . . . . . . . . . . . . . . . . . . . . . . . . 108∞C/W

Lead Temperature Range (Soldering, 60 sec.) . . . . . . . . 300∞C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Absolute maximum
ratings apply individually only, not in combination. Unless otherwise specified all
other voltages are referenced to GND.

ORDERING GUIDE

Memory
LDO Temperature

Package

Model Output Range Option

ADP3522ACP-3 2.80 V –20∞C to +85∞C CP-32
ADP3522ACP-1.8 1.80 V –20∞C to +85∞C CP-32

PIN CONFIGURATION

NC

ROWX

PWRONKE

PWRONIN

TCXOEN

AGND

REFOUT

282726

EOC

CHGEN

VTCXO
25

16

15

RESET

RESCAP

24
23
22

21

20

19
18
17

NC

VAN
VBAT

VCORE

VMEM

VBAT2
VSIM

NC

SIMEN

VRTCIN

VRTC

BATSNS

MVBAT

CHRDET

CHRIN

SIMVSEL

32

313029

1

2
3

4

5

6
7
8

PIN 1
INDICATOR

ADP3522

TOP VIEW

(Not to Scale)

TOP VIEW

9

10

GATEIN

GATEDR

11

121314

DGND

ISENSE

PIN FUNCTION DESCRIPTIONS

Pin Mnemonic Description

1 SIMEN SIM LDO Enable

2 VRTCIN RTC LDO Input Voltage

3 VRTC Real-Time Clock Supply/

Coin Cell Battery Charger

4 BATSNS Battery Voltage Sense Input

5 MVBAT Divided Battery Voltage Output

6 CHRDET Charge Detect Output

7 CHRIN Charger Input Voltage

8 SIMVSEL Programs VSIM Output;

Low: 1.8 V

9 GATEDR Charger Drive Output

10 GATEIN Microprocessor Charger Gate

Control Input

11 DGND Digital Ground

12 ISENSE Charge Current Sense Input

13 EOC End of Charge Output
14 CHGEN Charge Enable Control Input

15 RESCAP Reset Delay Time
16 RESET Main Reset, Open Drain

17, 24, 32 NC No Connection

18 VSIM SIM LDO Output

19 VBAT2 Battery Input Voltage 2

20 VMEM Memory LDO Output

21 VCORE Digital Core LDO Output

22 VBAT Battery Input Voltage

23 VAN Analog LDO Output

25 VTCXO TCXO LDO Output

26 REFOUT Output Reference

27 AGND Analog Ground

28 TCXOEN TCXO LDO Enable and

MVBAT Enable

29 PWRONIN Power On/Off Signal from

Microprocessor

30 PWRONKEY Power On/Off Key
31 ROWX Power Key Interface Output

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADP3522 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

REV. 0–6–