Analog Devices ADP3421 Datasheet

Geyserville-Enabled DC-DC

a

Converter Controller for Mobile CPUs

FEATURES
Meets Intel Mobile Voltage Positioning Requirements
Lowest Processor Dissipation for Longest Battery Life
Best Transient Containment
Minimum Number of Output Capacitors
System Power Management Compliant
Fast, Smooth, Output Transition During VID Code

Change
Programmable Current Limit
Power-Good
Integrated LDO Controllers for Clock and I/O Supplies
Programmable UVLO
Soft Start with Restart Lock-In

APPLICATIONS
Geyserville-Enabled Core DC-DC Converters
Fixed Voltage Mobile CPU Core DC-DC Converters
Notebook/Laptop Power Supplies
Programmable Output Power Supplies

GENERAL DESCRIPTION

The ADP3421 is a hysteretic dc-dc buck converter controller
with two auxiliary linear regulator controllers. The ADP3421
provides a total power conversion control solution for a micro­processor by delivering the core, I/O, and clock voltages. The
optimized low-voltage design is powered from the 3.3 V system

supply and draws only 10 µA maximum in shutdown. The main

output voltage is set by a 5-bit VID code. To accommodate the
transition time required by the newest processors for on-the­fly VID changes, the ADP3421 features high-speed operation
to allow a minimized inductor size that results in the fastest change
of current to the output. To further allow for the minimum
number of output capacitors to be used, the ADP3421 features
active voltage positioning that can be optimally compensated
to ensure a superior load transient response. The main output
signal interfaces with the ADP3410 dual MOSFET driver,
which is optimized for high speed and high efficiency for driving
both the upper and lower (synchronous) MOSFETs of the
buck converter.

DACOUT

VID4
VID3
VID2

VID1
VID0

LTO
LTB

LTI

CLKDRV

CLKFB

IODRV

IOFB

UVLO

VCC

GND

SD

ADP3421

FUNCTIONAL BLOCK DIAGRAM

ADP3421

VID DAC

CURRENT

LIMIT

COMPARATOR

EN

LEVEL

TRANSLATOR

CLOCK LDO

CONTROLLER

I/O LDO

CONTROLLER

VIN/VCC

MONITOR AND

UVLO BIAS

REFERENCE

CONTROLLER

BIAS AND

REFERENCE

BIAS EN

CORE

COMPARATOR

CORE CONTROLLER

SOFT START

TIMER

AND

POWER GOOD

GENERATOR

CLSET

CS+
CS–

VHYS

REG
RAMP

OUT

SSC

SSL

CORE

PWRGD

REV. 0

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reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1999

ADP3421–SPECIFICATIONS

(0ⴗC ≤ TA ≤ 100ⴗC, VCC = 3.3 V, V

1

C

= 10 pF, C

OUT

= 1.8 nF, C

SSC

= VCC, V

SD

= 1.3 nF, C

SSL

= 2.0 V, V

ULVO

= 1.5 nF, unless otherwise noted)

LTB

CORE

= V

DAC

, R

OUT

= 100 k⍀,

Parameter Symbol Conditions Min Typ Max Unit

SUPPLY-UVLO-POWER-GOOD

Supply Current I

VCC UVLO Threshold I

VCC UVLO Hysteresis V
Battery UVLO Threshold V
Battery UVLO Hysteresis I

Shutdown Input Threshold V
Core Power Good Threshold V

PWRGD Output Voltage V

CC(ON)

I

CC(UVLO)

V

CCH

CCH

V

CCL

CCHYS

UVLOTH

UVLO

SDTH

COREH(UP)

V

COREH(DN)

V

COREL(UP)

V

COREL(DN)

PWRGD

V

= 0.2 V 350 µA

UVLO

V

= 0 V, 3.0 V ≤ VCC ≤ 3.6 V 10 µA

SD

2.7 V
20 mV

1.175 1.225 1.275 V

V

= 1.275 V –0.3 +0.3 µA

UVLO

= 1.175 V 0.6 1.0 1.4 µA

V

UVLO

3.0 V < VCC < 5.0 V 0.8 0.7 × VCC V

1

2

1

2

3

0.925 V < V

V

= V

CORE

= 0.8 V

V

CORE

V

= 0.2 V 0 0.4 V

UVLO

< 2.000 V 1.10 × V

DAC

DAC

DAC

1.08 × V

0.90 × V

0.88 × V

0.95 × VCC VCC V

0 0.8 V

715 mA

2.9 V

DAC

DAC

DAC

DAC

1.12 × V

1.10 × V

0.92 × V

0.90 × V

DAC

DAC

DAC

DAC

V
V
V
V

CORE CONVERTER SOFT-START TIMER

Timing Charge Current I
Discharge Current I
Enable Threshold V
Termination Threshold V

SSC(UP)

SSC(DN)

SSCEN

SSCTH

4

V

= 0 V –0.6 –1.0 –1.4 µA

SSC

V

= 1.7 V, V

SSC

= 1.1 V 0.3 1.0 mA

UVLO

150 400 mV

1.53 1.70 1.87 V

VID DAC

VID Input Threshold V
VID Input Pull-up Current I

VID0..4

Nominal Output Voltage V

Output Voltage Accuracy ∆V

Output Voltage Settling Time t

DACS

VID0..4

DAC

DAC/VDAC

5

See VID Code Table I 0.925 2.000 V

0.8 0.7 × VCC V
10 40 µA

–0.85 0.85 %

35 µs

CORE COMPARATOR

Input Offset Voltage V
Input Bias Current I
Hysteresis Current I

Hysteresis Setting Reference Voltage V
Output Voltage V

Propagation Delay Time

Rise and Fall Time

6

6

COREOS

REG

RAMP

VHYS

OUTH

V

OUTL

t

COREPD

8

t

,710ns

CORER

8

t

COREF

V

= 1.3 V –3 +3 mV

REG

V

= V

REG

V

CORE

= 1.30 V, V

V

CS–

= 1.28 V

V

REG

R

VHYS

R

VHYS

R

VHYS

= 1.32 V

V

REG

R

VHYS

R

VHYS

R

VHYS

= V

= 1.3 V –2 +2 µA

RAMP

= 1.3 V

RAMP

= 1.28 V

CS+

Open –2 +2 µA
= 170 kΩ –7 –10 –13 µA
= 17 kΩ –82 –97 –113 µA

Open –2 +2 µA
= 170 kΩ 71013µA
= 17 kΩ 82 97 113 µA

1.53 1.70 1.87 V
VCC = 3.0 V 2.5 3.0 V
VCC = 3.6 V 0 0.4 V

7

T

= 25°C20ns

A

0°C ≤ T

≤ 100°C30ns

A

REV. 0–2–

ADP3421

Parameter Symbol Conditions Min Typ Max Unit

CURRENT LIMIT COMPARATOR

Input Offset Voltage V
Input Bias Current I
Hysteresis Current I

Hysteresis Setting Reference Voltage V
Propagation Delay Time

6

CLOS

CL+

CL–

VHYS

t

CLPD

7

LINEAR REGULATOR SOFT-START TIMER

Charge Current I
Discharge Current I
Enable Threshold V
Termination Threshold V

SSC(UP)

SSC(DN)

SSCEN

SSCTH

4

2.5 V CLK LDO CONTROLLER
Feedback Bias Current I
Output Drive Current I

DC Transconductance G

CLKFB

CLKDRV

CLK

1.5 V I/O LDO CONTROLLER
Feedback Bias Current I
Output Drive Current I

DC Transconductance G

IOFB

IODRV

IO

LEVEL TRANSLATOR

Input Clamping Threshold V
Output Voltage V

Propagation Delay Time

NOTES

1

V

ramps up monotonically.

CORE

2

V

ramps down monotonically.

CORE

3

During latency time of VID code change, the Power-Good output signal should not be considered valid.

4

Internal bias and soft start are not enabled unless the soft-start pin voltage first drops below the enable threshold.

5

Measured from 50% of VID code transient amplitude to the point where V

6

Guaranteed by characterization.

7

40 mV p-p amplitude impulse with 20 mV overdrive. Measure from the input threshold intercept point to 50% of the output voltage swing.

8

Measured between the 30% and 70% points of the output voltage swing.

9

The LTO output tied to V

Specifications subject to change without notice.

6

= 2.5 V rail through an R

CCLT

LTIH

LTOH

V

LTOL

t

LTPD

LTO

V

= 1.3 V –6 +6 mV

CS–

V

= 1.3 V –5 +5 µA

CS+

V

CORE

= 1.28 V, V

V

REG

= 1.28 V

V

CS+

R

IHYS

R

IHYS

R

IHYS

= 1.32 V

V

CS+

R

IHYS

R

IHYS

R

IHYS

= V

= 1.3 V

RAMP

= 1.3 V

CS–

Open –5 µA
= 170 kΩ –22 –30 –38 µA
= 17 kΩ –265 –300 –335 µA

Open –5 µA
= 170 kΩ –13 –20 –27 µA
= 17 kΩ –175 –200 –225 µA

1.53 1.70 1.87 V

T

= 25°C3060ns

A

0°C ≤ TA ≤ 100°C 50 100 ns

V

= 0 V –0.6 –1.0 –1.4 µA

SSC

V

= 1.7 V, V

SSC

= 1.1 V 0.3 1.0 mA

UVLO

150 400 mV

1.53 1.70 1.87 V

V

= 2.5 V 12.5 25 µA

CLKFB

V
V

∆I

V
V
V

∆I

I
I
V

= 2.55 V 1 µA

CLKDRV

= 2.45 V 3 20 mA

CLKDRV

= 1 mA 500 mA/V

CLKDRV

= 1.5 V 7.5 15 µA

IOFB

= 1.53 V 1 µA

IODRV

= 1.47 V 10 60 mA

IODRV

= 1 mA 650 mA/V

CLKDRV

= –10 µA 0.95 1.5 V

LTI

= –10 µA

LTI

= 0.175 V

LTI

9

9

0.9 × V

CCLT

V
375 mV
10 ns

settles within ±1% of its steady state value.

DAC

= 150 Ω pull-up resistor.

CCLT

V

REV. 0 –3–

ADP3421

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

PIN CONFIGURATION

Input Supply Voltage (VCC) . . . . . . . . . . . . . . –0.3 V to +7 V

UVLO Input Voltage . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

All Other Inputs/Outputs . . . . . . . . . . . . . . . . . . VCC + 0.3 V

Operating Ambient Temperature Range . . . . . . 0°C to 100°C

Junction Temperature Range . . . . . . . . . . . . . . . 0°C to 150°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98°C/W

θ

JA

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . 300°C

*This is a stress rating only; operation beyond these limits can cause the device to

be permanently damaged.

ORDERING GUIDE

Temperature Package Package

Model Range Description Option

ADP3421JRU 0°C to 100°C Thin Shrink Small RU-28

CLKDRV

VHYS

CLSET

LTO

LTI

LTB
VID4
VID3
VID2
VID1
VID0

CLKFB

IODRV

IOFB

1
2
3
4
5
6

ADP3421

7

TOP VIEW

(Not to Scale)

8

9
10
11
12
13
14

Outline (TSSOP)

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADP3421 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

28
27
26
25
24
23
22
21
20
19
18
17
16
15

CS–
CS+
REG
RAMP
VCC
OUT
GND

DACOUT
CORE
SSC

SSL
UVLO
PWRGD

SD

PIN FUNCTION DESCRIPTIONS

Pin Mnemonic Function

1 VHYS Core Comparator Hysteresis Setting. The voltage at this pin is held at a 1.7 V reference level. A resistor to

ground programs at a 1:1 ratio the current that is alternately switched into and out of the RAMP pin.

2 CLSET Current Limit Setting. The voltage at this pin is held at a 1.7 V reference level. A resistor to ground programs

a current that is gained up by 3:1 flowing out of the CS– pin, assuming the current limit comparator is not
triggered.

3 LTO Level Translator Output. This pin must be tied through a pull-up resistor to the voltage level desired for the

output high level. That voltage cannot be less than 1.5 V.

4 LTI Level Translator Input. This pin should be driven from an open drain/collector signal. The pull-up current is

provided by the pull-up resistor on the LTO pin. However, the pull-up current will be terminated when the
LTI pin reaches 1.5 V.

5 LTB Level Translator Bypass. For operation of the level translator with high-speed signals, this pin should be by-

passed to ground with a large value capacitor.
6 VID4 VID Input. Most significant bit.
7 VID3 VID Input.
8 VID2 VID Input.
9 VID1 VID Input.
10 VID0 VID Input. Least significant bit.
11 CLKDRV 2.5 V Linear Regulator Driver Output. This pin sinks current from the base of a PNP transistor as needed to

keep the CLKFB node regulated at 2.5 V.
12 CLKFB 2.5 V Linear Regulator Output Feedback. This pin is connected to the collector of a PNP transistor whose

base is driven by the CLKDRV pin.
13 IODRV 1.5 V Linear Regulator Driver Output. This pin sinks current from the base of a PNP transistor as needed to

keep the IOFB node regulated at 1.5 V.
14 IOFB 1.5 V Linear Regulator Output Feedback. This pin is connected to the collector of a PNP transistor whose

base is driven by the IODRV pin.

–4–

REV. 0