Dual Bootstrapped 12 V MOSFET
FEATURES
All-in-one synchronous buck driver
Bootstrapped high-side drive
1 PWM signal generates both drives
Anticross-conduction protection circuitry
Output disable control turns off both MOSFETs to float the
output per Intel® VRM 10 and AMD Opteron specifications
APPLICATIONS
Multiphase desktop CPU supplies
Single-supply synchronous buck converters
FUNCTIONAL BLOCK DIAGRAM
Driver with Output Disable
ADP3418
GENERAL DESCRIPTION
The ADP3418 is a dual, high voltage MOSFET driver optimized
for driving two N-channel MOSFETs, the two switches in a
nonisolated, synchronous, buck power converter. Each of the
drivers is capable of driving a 3000 pF load with a 30 ns transition
time. One of the drivers can be bootstrapped, and is designed to
handle the high voltage slew rate associated with floating highside gate drivers. The ADP3418 includes overlapping drive
protection to prevent shoot-through current in the external
OD
MOSFETs. The
low-side MOSFETs to prevent rapid output capacitor discharge
during system shutdowns.
The ADP3418 is specified over the commercial temperature
range of 0°C to 85°C, and is available in an 8-lead SOIC
package.
pin shuts off both the high-side and the
12V
C
IN
ADP3418
2
SQ
R
Q
1V
CMP
DELAY
DELAY
CMP
VCC
6
OD
VCC
3
VCC
4
1
8
7
5
6
BST
DRVH
SW
DRVL
PGND
C
R
BST1
BST1
D1
C
BST2
R
Q1
G
TO
INDUCTOR
Q2
03229-B-001
Figure 1.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
www.analog.com
ADP3418
TABLE OF CONTENTS
Specifications..................................................................................... 3
Overlap Protection Circuit...........................................................9
Absolute Maximum Ratings............................................................ 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Timing Characteristics..................................................................... 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ........................................................................ 9
Low-Side Driver............................................................................ 9
High-Side Driver .......................................................................... 9
REVISION HISTORY
8/04—Data Sheet Changed from Rev. A to Rev. B
Updated Figure 1; Deleted Figure 2.....................................................1
Updated Specifications Table...............................................................3
Updated Pin Description......................................................................5
Updated Theory of Operation .............................................................9
Updated Applications Section............................................................10
Change to Ordering Guide.................................................................14
Application Information................................................................ 10
Supply Capacitor Selection ....................................................... 10
Bootstrap Circuit........................................................................ 10
MOSFET Selection..................................................................... 10
PC Board Layout Considerations................................................. 12
Outline Dimensions....................................................................... 14
Ordering Guide .......................................................................... 14
4/04—Data Sheet Changed from Rev. 0 to Rev. A
Updated Format...................................................................... Universal
Change to General Description...........................................................1
Change to Figure 13 ..............................................................................8
Change to Ordering Guide.................................................................12
3/03—Revision 0: Initial Version
Rev. B | Page 2 of 16
ADP3418
SPECIFICATIONS
VCC = 12 V, BST = 4 V to 26 V, TA = 0°C to 85°C, unless otherwise noted.
Table 1.
Parameter Symbol Conditions Min Typ Max Unit
SUPPLY
Supply Voltage Range V
Supply Current I
OD INPUT
Input Voltage High 2.6 V
Input Voltage Low 0.8 V
Input Current –1 +1 µA
Propagation Delay Time
t
PWM INPUT
Input Voltage High 3.0 V
Input Voltage Low 0.8 V
Input Current –1 +1 µA
HIGH-SIDE DRIVER
Output Resistance, Sourcing Current V
Output Resistance, Sinking Current V
Transition Times t
t
Propagation Delay
t
LOW-SIDE DRIVER
Output Resistance, Sourcing Current 1.8 3.0 Ω
Output Resistance, Sinking Current 1.0 2.5 Ω
Transition Times t
t
Propagation Delay2 t
t
Timeout Delay SW = 5 V 240 ns
SW = PGND 90 120 ns
1
All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC).
2
For propagation delays, t
1
CC
SYS
2
refers to the specified signal going high, and t
pdh
t
pdh
OD
pdl
OD
rDRVH
fDRVH
t
pdhDRVH
pdlDRVH
rDRVL
See Figure 4, C
fDRVL
pdhDRVL
pdlDRVL
4.15 13.2 V
BST = 12 V, IN = 0 V 3 6 mA
See Figure 3 25 40 ns
See Figure 3 20 40 ns
− VSW = 12 V 1.8 3.0 Ω
BST
− VSW = 12 V 1.0 2.5 Ω
BST
See Figure 4, V
= 3 nF
C
LOAD
See Figure 4, V
= 3 nF
C
LOAD
See Figure 4, V
V
− VSW = 12 V 20 35 ns
BST
See Figure 4, C
− VSW = 12 V,
BST
− VSW = 12 V,
BST
− VSW = 12 V 40 65 ns
BST
= 3 nF 25 35 ns
LOAD
= 3 nF 21 30 ns
LOAD
35 45 ns
20 30 ns
See Figure 4 30 60 ns
See Figure 4 10 20 ns
refers to it going low.
pdl
Rev. B | Page 3 of 16
ADP3418
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
VCC –0.3 V to +15 V
BST
DC –0.3 V to VCC + 15 V
<200 ns –0.3 V to 36 V
BST to SW –0.3 V to +15 V
SW
DC –5 V to +15 V
< 200 ns –10 V to +25 V
DRVH SW – 0.3 V to BST + 0.3 V
DRVL (< 200 ns) –2 V to VCC + 0.3 V
All Other Inputs and Outputs –0.3 V to VCC + 0.3 V
Operating Ambient Temperature
Range
Operating Junction Temperature
Range
Storage Temperature Range –65°C to +150°C
Junction-to-Air Thermal Resistance
)
(θ
JA
2-Layer Board 123°C/W
4-Layer Board 90°C/W
Lead Temperature (Soldering, 10 s) 300°C
Infrared (15 s) 260°C
0°C to 85°C
0°C to 150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. Absolute maximum ratings apply individually
only, not in combination. Unless otherwise specified, all voltages
are referenced to PGND.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. B | Page 4 of 16
ADP3418
V
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
DRVH
BST
1
AD3418
IN
2
TOP VIEW
3
OD
(Not to Scale)
CC
4
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1 BST
Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins holds this
bootstrapped voltage for the high-side MOSFET as it is switched. The capacitor should be between 100 nF and 1 µF.
2 IN Logic Level Input. This pin has primary control of the drive outputs.
3
OD
Output Disable. When low, this pin disables normal operation, forcing DRVH and DRVL low.
4 VCC Input Supply. This pin should be bypassed to PGND with ~1 µF ceramic capacitor.
5 DRVL Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET.
6 PGND Power Ground. Should be closely connected to the source of the lower MOSFET.
7 SW
This pin is connected to the buck switching node, close to the upper MOSFET’s source. It is the floating return for
the upper MOSFET drive signal.
8 DRVH Buck Drive. Output drive for the upper (buck) MOSFET.
8
SW
7
PGND
6
DRVL
5
03229-B-002
Rev. B | Page 5 of 16
ADP3418
O
TIMING CHARACTERISTICS
OD
DRVH
R DRVL
t
pdlOD
90%
t
pdhOD
10%
03229-B-003
Figure 3. Output Disable Timing Diagram
IN
t
rDRVL
03229-B-004
DRVL
DRVH-SW
SW
t
pdlDRVLtfDRVL
t
pdhDRVH
t
rDRVH
V
TH
t
pdlDRVH
V
t
fDRVH
TH
t
pdhDRVL
1V
Figure 4. Timing Diagram. Timing is referenced to the 90% and 10% points, unless otherwise noted.
Rev. B | Page 6 of 16
ADP3418
TYPICAL PERFORMANCE CHARACTERISTICS
26
= 12V
V
1
IN
CC
= 3nF
C
LOAD
24
DRVL
2
3
DRVH
DRVL
03229-B-005
Figure 5. DRVH Rise and DRVL Fall Times
22
20
FALL TIME (ns)
18
16
JUNCTION TEMPERATURE (°C)
Figure 8. DRVH and DRVL Fall Times vs. Temperature
DRVH
1250 25 50 75 100
03229-B-008
IN
1
DRVH
2
DRVL
3
60
TA=25°C
V
= 12V
CC
50
40
30
RISE TIME (ns)
20
DRVH
DRVL
Figure 6. DRVH Fall and DRVL Rise Times
40
VCC = 12V
= 3nF
C
LOAD
35
30
RISE TIME (ns)
25
20
JUNCTION TEMPERATURE (°C)
Figure 7. DRVH and DRVL Rise Times vs. Temperature
DRVH
DRVL
03229-B-006
1250 25 50 75 100
03229-B-007
Rev. B | Page 7 of 16
10
LOAD CAPACITANCE (nF)
Figure 9. DRVH and DRVL Rise Times vs. Load Capacitance
35
TA=25°C
= 12V
V
CC
30
25
20
FALL TIME (ns)
15
10
LOAD CAPACITANCE (nF)
Figure 10. DRVH and DRVL Fall Times vs. Load Capacitance
DRVL
DRVH
51234
03229-B-009
51234
03229-B-010
ADP3418
60
TA=25°C
= 12V
V
CC
= 3nF
C
LOAD
5
4
TA = 25°C
C
= 3nF
LOAD
40
20
SUPPLY CURRENT (mA)
0
16
15
14
13
SUPPLY CURRENT (mA)
IN FREQUENCY (kHz)
Figure 11. Supply Current vs. Frequency
VCC = 12V
= 3nF
C
LOAD
f
= 250kHz
IN
3
2
1
DRVL OUTPUT VOLTAGE (V)
12000 200 400 600 800 1000
03229-B-011
0
VCC VOLTAGE (V)
501234
03229-B-013
Figure 13. DRVL Output Voltage vs. Supply Voltage
12
JUNCTION TEMPERATURE (°C)
1250 25 50 75 100
03229-B-012
Figure 12. Supply Current vs. Temperature
Rev. B | Page 8 of 16
ADP3418
THEORY OF OPERATION
The ADP3418 is a dual MOSFET driver optimized for driving
two N-channel MOSFETs in a synchronous buck converter
topology. A single PWM input signal is all that is required to
properly drive the high-side and the low-side MOSFETs. Each
driver is capable of driving a 3 nF load at speeds up to 500 kHz.
A more detailed description of the ADP3418 and its features
follows. Refer to Figure 1.
LOW-SIDE DRIVER
The low-side driver is designed to drive a ground-referenced
N-channel MOSFET. The bias to the low-side driver is internally
connected to the VCC supply and PGND.
When the driver is enabled, the driver’s output is 180 degrees
out of phase with the PWM input. When the ADP3418 is disabled, the low-side gate is held low.
HIGH-SIDE DRIVER
The high-side driver is designed to drive a floating N-channel
MOSFET. The bias voltage for the high-side driver is developed
by an external bootstrap supply circuit, which is connected
between the BST and SW pins.
The bootstrap circuit comprises a diode, D1, and bootstrap
. C
capacitor, C
BST1
BST2
and R
side gate drive voltage and limit the switch node slew-rate
(referred to as a Boot-Snap™ circuit, see the Application
Information section for more details). When the ADP3418 is
starting up, the SW pin is at ground, so the bootstrap capacitor
will charge up to VCC through D1. When the PWM input goes
high, the high-side driver will begin to turn on the high-side
MOSFET, Q1, by pulling charge out of C
turns on, the SW pin will rise up to V
+ V
V
IN
, which is enough gate-to-source voltage to hold Q1
C(BST)
on. To complete the cycle, Q1 is switched off by pulling the gate
down to the voltage at the SW pin. When the low-side MOSFET,
Q2, turns on, the SW pin is pulled to ground. This allows the
bootstrap capacitor to charge up to VCC again.
are included to reduce the high-
BST
and C
BST1
, forcing the BST pin to
IN
BST2
. As Q1
OVERLAP PROTECTION CIRCUIT
The overlap protection circuit prevents both of the main power
switches, Q1 and Q2, from being on at the same time. This is
done to prevent shoot-through currents from flowing through
both power switches and the associated losses that can occur
during their on/off transitions. The overlap protection circuit
accomplishes this by adaptively controlling the delay from the
Q1 turn off to the Q2 turn on, and by internally setting the
delay from the Q2 turn off to the Q1 turn on.
To prevent the overlap of the gate drives during the Q1 turn off
and the Q2 turn on, the overlap circuit monitors the voltage at
the SW pin. When the PWM input signal goes low, Q1 will
begin to turn off (after propagation delay). Before Q2 can turn
on, the overlap protection circuit makes sure that SW has first
gone high and then waits for the voltage at the SW pin to fall
from V
1 V, Q2 begins turn on. If the SW pin had not gone high first,
then the Q2 turn on is delayed by a fixed 120 ns. By waiting for
the voltage on the SW pin to reach 1 V or for the fixed delay
time, the overlap protection circuit ensures that Q1 is off before
Q2 turns on, regardless of variations in temperature, supply
voltage, input pulse width, gate charge, and drive current. If SW
does not go below 1 V after 240 ns, DRVL will turn on. This can
occur if the current flowing in the output inductor is negative
and is flowing through the high-side MOSFET body diode.
To prevent the overlap of the gate drives during the Q2 turn off
and the Q1 turn on, the overlap circuit provides an internal
delay that is set to 40 ns. When the PWM input signal goes high,
Q2 will begin to turn off (after a propagation delay), but before
Q1 can turn on, the overlap protection circuit waits for the
voltage at DRVL to drop to approximately one sixth of V
Once the voltage at DRVL has reached this point, the overlap
protection circuit will wait for the 40 ns internal delay time.
Once the delay period has expired, Q1 will begin turn on.
to 1 V. Once the voltage on the SW pin has fallen to
IN
.
CC
The high-side driver’s output is in phase with the PWM input.
When the driver is disabled, the high-side gate is held low.
Rev. B | Page 9 of 16
ADP3418
×
=
−
APPLICATION INFORMATION
SUPPLY CAPACITOR SELECTION
For the supply input (VCC) of the ADP3418, a local bypass
capacitor is recommended to reduce the noise and to supply
some of the peak currents drawn. Use a 4.7 µF, low ESR
capacitor. Multilayer ceramic chip (MLCC) capacitors provide
the best combination of low ESR and small size. Keep the
ceramic capacitor as close as possible to the ADP3418.
BOOTSTRAP CIRCUIT
The bootstrap circuit uses a charge storage capacitor (C
a diode, as shown in Figure 1. These components can be
selected after the high-side MOSFET has been chosen. The
bootstrap capacitor must have a voltage rating that is able to
handle twice the maximum supply voltage. A minimum 50 V
rating is recommended. The capacitor values are determined
using the following equations:
Q
where Q
V
GATE
CC ×=+ 10
BST2BST1
C
BST1
CC
+
BST2BST1
is the total gate charge of the high-side MOSFET at
GATE
, V
is the desired gate drive voltage (usually in the
GATE
range of 5-10 V, 7 V being typical), and V
GATE
(1)
V
GATE
V
GATE
=
(2)
VVCC
−
D
is the voltage drop
D
across D1. Rearranging Equations 1 and 2 to solve for C
yields
Q
C
BST1
can then be found by rearranging Equation 1:
C
BST2
C −×=
BST2
GATE
×=10
Q
GATE
V
GATE
−
VVCC
D
C
110BST
For example, an NTD60N02 has a total gate charge of about
12 nC at V
C
= 12 nF and C
BST1
= 7 V. Using VCC = 12 V and VD = 1 V, we find
GATE
= 6.8 nF. Good quality ceramic
BST2
capacitors should be used.
is used for slew-rate limiting to minimize the ringing at the
R
BST
switch node. It also provides peak current limiting through D1.
value of 1.5 Ω to 2.2 Ω is a good choice. The resistor
An R
BST
needs to be able to handle at least 250 mW due to the peak
currents that flow through it.
BST
BST1
) and
A small-signal diode can be used for the bootstrap diode due to
the ample gate drive voltage supplied by V
. The bo otstrap
CC
diode must have a minimum 15 V rating to withstand the
maximum supply voltage. The average forward current can be
estimated by
fQI
where f
GATE
)(
AVGF
is the maximum switching frequency of the
MAX
(3)
MAX
controller. The peak surge current rating should be calculated
using:
VVCC
D
I
=
PEAKF
)(
R
(4)
BST
MOSFET SELECTION
When interfacing the ADP3418 to external MOSFETs, there are
a few considerations that the designer should be aware of. These
will help to make a more robust design that will minimize
stresses on both the driver and MOSFETs. These stresses
include exceeding the short-time duration voltage ratings on
the driver pins as well as the external MOSFET.
It is also highly recommended to use the Boot-Snap circuit to
improve the interaction of the driver with the characteristics of
the MOSFETs. If a simple bootstrap arrangement is used, make
sure to then include a proper snubber network on the SW node.
High-Side (Control) MOSFETs
The high-side MOSFET is usually selected to be high speed to
minimize switching losses (see any ADI Flex-mode™ controller
datasheet for more details on MOSFET losses). This usually
implies a low gate resistance and low input capacitance/charge
device. Yet, there is also a significant source lead inductance that
can exist (this depends mainly on the MOSFET package; it is
best to contact the MOSFET vendor for this information).
The ADP3418 DRVH output impedance and the input
resistance of the MOSFETs determine the rate of charge
delivery to the gate’s internal capacitance, which determines the
speed at which the MOSFETs turn on and off. However, due to
potentially large currents flowing in the MOSFETs at the on and
off times (this current is usually larger at turn off due to
ramping up of the output current in the output inductor), the
source lead inductance will generate a significant voltage across
it when the high-side MOSFETs switch off. This will create a
significant drain-source voltage spike across the internal die of
the MOSFETs and can lead to catastrophic avalanche. The
mechanisms involved in this avalanche condition can be
referenced in literature from the MOSFET suppliers.
Rev. B | Page 10 of 16
ADP3418
The MOSFET vendor should provide a maximum voltage slew
rate at drain current rating such that this can be designed
around. Once you have this specification, the next step is to
determine the maximum current you expect to see in the
MOSFET. This can be done with the following equation:
Here, D
()
DCMAX
is determined for the VR controller being used with
MAX
)(
VVCCphaseperII
OUT
MAX
×−+=
MAX
(5)
Lf
×
OUT
D
the driver. Please note this current gets divided roughly equally
between MOSFETs if more than one is used (assume a worstcase mismatch of 30% for design margin). L
is the output
OUT
inductor value.
When producing your design, there is no exact method for
calculating the dV/dt due to the parasitic effects in the external
MOSFETs as well as the PCB. However, it can be measured to
determine if it is safe. If it appears the dV/dt is too fast, an
optional gate resistor can be added between DRVH and the
high-side MOSFETs. This resistor will slow down the dV/dt, but
it will also increase the switching losses in the high-side
MOSFETs. The ADP3418 has been optimally designed with an
internal drive impedance that will work with most MOSFETs to
switch them efficiently yet minimize dV/dt. However, some
high-speed MOSFETs may require this external gate resistor
depending on the currents being switched in the MOSFET.
Low-Side (Synchronous) MOSFETs
The low-side MOSFETs are usually selected to have a low onresistance to minimize conduction losses. This usually implies a
large input gate capacitance and gate charge. The first concern is
to make sure the power delivery from the ADP3418’s DRVL
does not exceed the thermal rating of the driver (see the Flexmode controller data sheet for details).
The next concern for the low-side MOSFETs is based on
preventing them from inadvertently being switched on when
the high-side MOSFET turns on. This occurs due to the draingate (Miller, also specified as C
) capacitance of the MOSFET.
rss
When the drain of the low-side MOSFET is switched to VCC by
the high-side turning on (at a rate dV/dt), the internal gate of
the low-side MOSFET will be pulled up by an amount roughly
equal to VCC × (C
). It is important to make sure this does
rss/Ciss
not put the MOSFET into conduction.
Another consideration is the non-overlap circuitry of the
ADP3418 which attempts to minimize the non-overlap period.
During the state of the high-side turning off to low-side turning
on, the SW pin is monitored (as well as the conditions of SW
prior to switching) to adequately prevent overlap.
However, during the low-side turn off to high-side turn on, the
SW pin does not contain information for determining the
proper switching time, so the state of the DRVL pin is
monitored to go below one sixth of VCC and then a delay is
added. But due to the Miller capacitance and internal delays of
the low-side MOSFET gate, one must ensure the Miller to input
capacitance ratio is low enough and the low-side MOSFET
internal delays are not large enough to allow accidental turn on
of the low-side when the high-side turns on.
A spreadsheet is available from ADI that will assist the designer
in the proper selection of low-side MOSFETs.
Rev. B | Page 11 of 16
ADP3418
PC BOARD LAYOUT CONSIDERATIONS
Use the following general guidelines when designing printed
circuit boards.
• Trace out the high current paths and use short, wide
(>20 mil) traces to make these connections.
• Connect the PGND pin of the ADP3418 as closely as
possible to the source of the lower MOSFET.
• The V
possible to the VCC and PGND pins.
• Use vias to other layers when possible to maximize thermal
conduction away from the IC.
The circuit in Figure 15 shows how four drivers can be
combined with the ADP3188 to form a total power conversion
solution for generating V
10.x compliant.
Figure 14 shows an example of the typical land patterns based
on the guidelines given previously. For more detailed layout
guidelines for a complete CPU voltage regulator subsystem,
refer to the ADP3188 data sheet.
bypass capacitor should be located as close as
CC
for an Intel CPU that is VRD
CC(CORE)
C
BST1
BST2
R
BST
03229-B-014
C
D1
C
VCC
Figure 14. External Component Placement Example for the ADP3418 Driver
Rev. B | Page 12 of 16
ADP3418
CC (CORE)
CC (CORE) RTN
V
0.8375 V – 1.6V
95A TDC, 119A PK
V
LI
C8
R3
12nF
2.2Ω
2700MF/16V/3.3A × 2
18A
370nH
+
5mΩ EACH
560µF/4V × 8
C24 C31
+
SANYO SEPC SERIES
L4
320nH/1.4mΩ
F
µ
C7
4.7
Q1
NTD60N02
C6
876
6.8nF
DRVH
U2
ADP3418
BST1IN
D2
1N4148
++
C1 C2
SANYO MV-WX SERIES
IN
V
12V
RTN
IN
V
Q4
NTD110N02
5
SW
DRVL
PGND
VCC
OD
2
3
4
C5
4.7µF
MLCC IN
SOCKET
10µF× 18
RTH1
100kΩ, 5%
NTC
F
µ
C15
4.7
C14
6.8nF
U4
ADP3418
D4
1N4148
2827262524
VCC
PWM1
VID4
VID3
12345
1%
L4
Q9
NTD60N02
876
DRVH
BST1IN
PWM2
VID2
FROM
320nH/1.4mΩ
SW
2
PWM3
VID1
CPU
PGND
OD
3
PWM4
VID0
Q12
NTD110N02
Q11
NTD110N02
5
C20
DRVL
R6
VCC
4
F
µ
C13
4.7
R
2322212019
SW1
SW2
SW3
SW4
VID5
FBRTNFBCOMP
678
9
CFB22pF
B
C
470pF
1nF
C21
POWER
12nF
2.2Ω
PH1
R
158kΩ,
1%
PH2
158kΩ,
PH3
R
158kΩ,
PH4
R
158kΩ, 1%
181716
GND
CSCOMP
PWRGDENDELAYRTRAMPADJ
10
111213
A
R
12.1kΩ
A
C
470pF
B
R
1.21kΩ
GOOD
ENABLE
L3
320nH/1.4mΩ
F
µ
C11
4.7
Q5
NTD60N02
Q3
NTD110N02
C10
876
12nF
2.2Ω
U3
6.8nF
ADP3418
D3
DRVH
BST1IN
1N4148
C12
R4
Q8
NTD110N02
Q7
NTD110N02
5
C16
DRVL
VCC
4
C9
12nF
R5
2.2Ω
F
µ
4.7
SW
PGND
OD
2
3
U1
ADP3188
R2
137kΩ
D1
1N4148
C4
1µF
+
C3
100µF
C19
1%
1%
CS2
R
CS1
R
CS2
C
CS1
C
CSSUM
F
µ
4.7
C16
U5
84.5kΩ
35.7kΩ
1.5nF
560pF
6.8nF
ADP3418
D5
1N4148
C22
CSREF
T
R
LDY
R
LDY
C
L5
Q13
NTD60N02
876
DRVH
BST1IN
1nF
15
ILIMIT
14
137kΩ
470kΩ
39nF
320nH/1.4mΩ
Q16
NTD110N02
Q15
NTD110N02
5
SW
DRVL
PGND
VCC
OD
2
3
4
F
µ
C17
4.7
LIM
150kΩ
1%
R
1nF
C23
1%
3229-B-015
Figure 15. VRD 10.x Compliant Intel CPU Supply Circuit
Rev. B | Page 13 of 16
ADP3418
Y
OUTLINE DIMENSIONS
4.00 (0.1574)
3.80 (0.1497)
5.00 (0.1968)
4.80 (0.1890)
85
6.20 (0.2440)
5.80 (0.2284)
41
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
COPLANARIT
0.10
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012AA
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
0.25 (0.0098)
0.17 (0.0067)
0.50 (0.0196)
0.25 (0.0099)
8°
1.27 (0.0500)
0°
0.40 (0.0157)
× 45°
Figure 16. 8-Lead Standard Small Outline Package [SOIC]
Narrow Body (R-8)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model Temperature Range Package Description Package Option
ADP3418KRZ
ADP3418KRZ–REEL
1
Z = Pb-free part.
1
1
0°C to 85°C SOIC RN-8
0°C to 85°C SOIC RN-8
Rev. B | Page 14 of 16
ADP3418
NOTES
Rev. B | Page 15 of 16
ADP3418
NOTES
© 2004 Analog Devices, Inc. All rights reserved. Trademarks
and
registered trademarks are the property of their respective owners.
C03229–0–8/04(B)
Rev. B | Page 16 of 16
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