Analog Devices ADP3418 b Datasheet
Dual Bootstrapped 12 V MOSFET
FEATURES
All-in-one synchronous buck driver
Bootstrapped high-side drive
1 PWM signal generates both drives
Anticross-conduction protection circuitry
Output disable control turns off both MOSFETs to float the
output per Intel® VRM 10 and AMD Opteron specifications
APPLICATIONS
Multiphase desktop CPU supplies
Single-supply synchronous buck converters
FUNCTIONAL BLOCK DIAGRAM
Driver with Output Disable
ADP3418
GENERAL DESCRIPTION
The ADP3418 is a dual, high voltage MOSFET driver optimized
for driving two N-channel MOSFETs, the two switches in a
nonisolated, synchronous, buck power converter. Each of the
drivers is capable of driving a 3000 pF load with a 30 ns transition
time. One of the drivers can be bootstrapped, and is designed to
handle the high voltage slew rate associated with floating highside gate drivers. The ADP3418 includes overlapping drive
protection to prevent shoot-through current in the external
OD
MOSFETs. The
low-side MOSFETs to prevent rapid output capacitor discharge
during system shutdowns.
The ADP3418 is specified over the commercial temperature
range of 0°C to 85°C, and is available in an 8-lead SOIC
package.
pin shuts off both the high-side and the
12V
C
IN
ADP3418
2
SQ
R
Q
1V
CMP
DELAY
DELAY
CMP
VCC
6
OD
VCC
3
VCC
4
1
8
7
5
6
BST
DRVH
SW
DRVL
PGND
C
R
BST1
BST1
D1
C
BST2
R
Q1
G
TO
INDUCTOR
Q2
03229-B-001
Figure 1.
Rev. B
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However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
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Tel: 781.329.4700
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
www.analog.com
ADP3418
TABLE OF CONTENTS
Specifications..................................................................................... 3
Overlap Protection Circuit...........................................................9
Absolute Maximum Ratings............................................................ 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Timing Characteristics..................................................................... 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ........................................................................ 9
Low-Side Driver............................................................................ 9
High-Side Driver .......................................................................... 9
REVISION HISTORY
8/04—Data Sheet Changed from Rev. A to Rev. B
Updated Figure 1; Deleted Figure 2.....................................................1
Updated Specifications Table...............................................................3
Updated Pin Description......................................................................5
Updated Theory of Operation .............................................................9
Updated Applications Section............................................................10
Change to Ordering Guide.................................................................14
Application Information................................................................ 10
Supply Capacitor Selection ....................................................... 10
Bootstrap Circuit........................................................................ 10
MOSFET Selection..................................................................... 10
PC Board Layout Considerations................................................. 12
Outline Dimensions....................................................................... 14
Ordering Guide .......................................................................... 14
4/04—Data Sheet Changed from Rev. 0 to Rev. A
Updated Format...................................................................... Universal
Change to General Description...........................................................1
Change to Figure 13 ..............................................................................8
Change to Ordering Guide.................................................................12
3/03—Revision 0: Initial Version
Rev. B | Page 2 of 16
ADP3418
SPECIFICATIONS
VCC = 12 V, BST = 4 V to 26 V, TA = 0°C to 85°C, unless otherwise noted.
Table 1.
Parameter Symbol Conditions Min Typ Max Unit
SUPPLY
Supply Voltage Range V
Supply Current I
OD INPUT
Input Voltage High 2.6 V
Input Voltage Low 0.8 V
Input Current –1 +1 µA
Propagation Delay Time
t
PWM INPUT
Input Voltage High 3.0 V
Input Voltage Low 0.8 V
Input Current –1 +1 µA
HIGH-SIDE DRIVER
Output Resistance, Sourcing Current V
Output Resistance, Sinking Current V
Transition Times t
t
Propagation Delay
t
LOW-SIDE DRIVER
Output Resistance, Sourcing Current 1.8 3.0 Ω
Output Resistance, Sinking Current 1.0 2.5 Ω
Transition Times t
t
Propagation Delay2 t
t
Timeout Delay SW = 5 V 240 ns
SW = PGND 90 120 ns
1
All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC).
2
For propagation delays, t
1
CC
SYS
2
refers to the specified signal going high, and t
pdh
t
pdh
OD
pdl
OD
rDRVH
fDRVH
t
pdhDRVH
pdlDRVH
rDRVL
See Figure 4, C
fDRVL
pdhDRVL
pdlDRVL
4.15 13.2 V
BST = 12 V, IN = 0 V 3 6 mA
See Figure 3 25 40 ns
See Figure 3 20 40 ns
− VSW = 12 V 1.8 3.0 Ω
BST
− VSW = 12 V 1.0 2.5 Ω
BST
See Figure 4, V
= 3 nF
C
LOAD
See Figure 4, V
= 3 nF
C
LOAD
See Figure 4, V
V
− VSW = 12 V 20 35 ns
BST
See Figure 4, C
− VSW = 12 V,
BST
− VSW = 12 V,
BST
− VSW = 12 V 40 65 ns
BST
= 3 nF 25 35 ns
LOAD
= 3 nF 21 30 ns
LOAD
35 45 ns
20 30 ns
See Figure 4 30 60 ns
See Figure 4 10 20 ns
refers to it going low.
pdl
Rev. B | Page 3 of 16
ADP3418
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
VCC –0.3 V to +15 V
BST
DC –0.3 V to VCC + 15 V
<200 ns –0.3 V to 36 V
BST to SW –0.3 V to +15 V
SW
DC –5 V to +15 V
< 200 ns –10 V to +25 V
DRVH SW – 0.3 V to BST + 0.3 V
DRVL (< 200 ns) –2 V to VCC + 0.3 V
All Other Inputs and Outputs –0.3 V to VCC + 0.3 V
Operating Ambient Temperature
Range
Operating Junction Temperature
Range
Storage Temperature Range –65°C to +150°C
Junction-to-Air Thermal Resistance
)
(θ
JA
2-Layer Board 123°C/W
4-Layer Board 90°C/W
Lead Temperature (Soldering, 10 s) 300°C
Infrared (15 s) 260°C
0°C to 85°C
0°C to 150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. Absolute maximum ratings apply individually
only, not in combination. Unless otherwise specified, all voltages
are referenced to PGND.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. B | Page 4 of 16
ADP3418
V
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
DRVH
BST
1
AD3418
IN
2
TOP VIEW
3
OD
(Not to Scale)
CC
4
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1 BST
Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins holds this
bootstrapped voltage for the high-side MOSFET as it is switched. The capacitor should be between 100 nF and 1 µF.
2 IN Logic Level Input. This pin has primary control of the drive outputs.
3
OD
Output Disable. When low, this pin disables normal operation, forcing DRVH and DRVL low.
4 VCC Input Supply. This pin should be bypassed to PGND with ~1 µF ceramic capacitor.
5 DRVL Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET.
6 PGND Power Ground. Should be closely connected to the source of the lower MOSFET.
7 SW
This pin is connected to the buck switching node, close to the upper MOSFET’s source. It is the floating return for
the upper MOSFET drive signal.
8 DRVH Buck Drive. Output drive for the upper (buck) MOSFET.
8
SW
7
PGND
6
DRVL
5
03229-B-002
Rev. B | Page 5 of 16
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