Analog Devices ADP3417 a Datasheet
Dual Bootstrapped
a
FEATURES
All-In-One Synchronous Buck Driver
Bootstrapped High Side Drive
One PWM Signal Generates Both Drives
Anticross-Conduction Protection Circuitry
APPLICATIONS
Multiphase Desktop CPU Supplies
Single-Supply Synchronous Buck Converters
Standard-to-Synchronous Converter Adaptations
GENERAL DESCRIPTION
The ADP3417 is a dual MOSFET driver optimized for driving
two N-channel MOSFETs which are the two switches in a
nonisolated synchronous buck power converter. Each of the
drivers is capable of driving a 3000 pF load with a 20 ns propagation delay and a 30 ns transition time. One of the drivers can
be bootstrapped and is designed to handle the high voltage
slew rate associated with “floating” high side gate drivers.
The ADP3417 includes overlapping drive protection (ODP)
to prevent shoot-through current in the external MOSFETs.
The ADP3417 is specified over the commercial temperature
range of 0°C to 70°C and is available in an 8-lead SOIC package.
MOSFET Driver
ADP3417
FUNCTIONAL BLOCK DIAGRAM
VCC
IN
OVERLAP
PROTECTION
CIRCUIT
ADP3417
VCC
ADP3417
IN
DELAY
BST
PGND
BST
C
BST
DRVH
SW
D1
DRVH
SW
DRVL
12V
Q1
TO
INDUCTOR
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
1V
1V
DRVL
PGND
Q2
Figure 1. General Application Circuit
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2002
1
ADP3417–SPECIFICATIONS
Parameter Symbol Conditions Min Typ Max Unit
SUPPLY
Supply Voltage Range VCC 4.15 13.2 V
Quiescent Current ISYS VCC = BST = 12 V, IN = 0 V 5 7 mA
PWM INPUT
Input Voltage High
Input Voltage Low
HIGH SIDE DRIVER
Output Resistance, Sourcing Current V
Output Resistance, Sinking Current V
Transition Times
Transition Times
Propagation Delay
LOW SIDE DRIVER
Output Resistance, Sourcing Current VCC = 12 V 1.75 3.0 Ω
Output Resistance, Sinking Current VCC = 12 V 1.0 2.5 Ω
Transition Times
Propagation Delay
NOTES
1
All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.
2
Logic inputs meet typical CMOS I/O conditions for source/sink current (~1 µA).
3
AC specifications are guaranteed by characterization but not production tested.
4
For propagation delays, “TPDH” refers to the specified signal going high; “TPDL” refers to it going low.
Specifications subject to change without notice.
2
2
3
3
3, 4
3
3, 4
(See Figure 2) tpdh
tr
DRVH
tf
DRVH
tpdh
tpdl
tr
DRVL
tf
DRVL
tpdl
DRVH
DRVH
DRVL
DRVL
(VCC = 12 V, BST = 4 V to 26 V, TA = 0C to 70C, unless otherwise noted.)
2.5 V
0.8 V
– VSW = 12 V 1.75 3.0 Ω
BST
– VSW = 12 V 1.0 2.5 Ω
BST
See Figure 2, V
= 3 nF
C
LOAD
See Figure 2, V
= 3 nF
C
LOAD
See Figure 2, V
V
– V
BST
SW
– VSW = 12 V, 45 55 ns
BST
– VSW = 12 V, 20 30 ns
BST
– V
BST
= 12 V, 45 65 ns
SW
= 12 V 15 35 ns
See Figure 2, VCC = 12 V, 25 35 ns
C
= 3 nF
LOAD
See Figure 2, VCC = 12 V, 21 30 ns
= 3 nF
C
LOAD
See Figure 2, VCC = 12 V 30 60 ns
See Figure 2, VCC = 12 V 10 20 ns
–2–
REV. A
ADP3417
ABSOLUTE MAXIMUM RATINGS
*
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +15 V
BST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +30 V
BST to SW . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +15 V
SW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –5.0 V to +25 V
IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V
Model Range Description Option
ADP3417JR 0°C to 70°C8-Lead Standard SOIC-8
ORDERING GUIDE
Temperature Package Package
Small Outline (SOIC)
Operating Ambient Temperature Range . . . . . . . 0°C to 70°C
Operating Junction Temperature Range . . . . . . 0°C to 125°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123°C/W
θ
JA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/W
θ
JC
PIN CONFIGURATION
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C
*This is a stress rating only; operation beyond these limits can cause the device to
be permanently damaged. Unless otherwise specified, all voltages are referenced
to PGND.
BST
NC
VCC
1
2
IN
3
4
ADP3417
TOP VIEW
(Not To Scale)
NC = NO CONNECT
8
DRVH
7
SW
6
PGND
5
DRVL
PIN FUNCTION DESCRIPTIONS
Pin Mnemonic Function
1 BST Floating Bootstrap Supply for the Upper MOSFET. A capacitor connected between BST and SW Pins
holds this bootstrapped voltage for the high side MOSFET as it is switched. The capacitor should be
chosen between 100 nF and 1 F.
2INLogic-level input signal that has primary control of the drive outputs.
3NC No Connection
4 VCC Input Supply. This pin should be bypassed to PGND with ~1 µF ceramic capacitor.
5 DRVL Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET.
6 PGND Power Ground. Should be closely connected to the source of the lower MOSFET.
7SW This pin is connected to the buck-switching node, close to the upper MOSFET’s source. It is the floating
return for the upper MOSFET drive signal. It is also used to monitor the switched voltage to prevent turn-
on of the lower MOSFET until the voltage is below ~1 V. Thus, according to operating conditions, the
high low transition delay is determined at this pin.
8 DRVH Buck Drive. Output drive for the upper (buck) MOSFET.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADP3417 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
REV. A
–3–
WARNING!
ESD SENSITIVE DEVICE
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