Analog Devices ADP3415KRM-REEL7, ADP3415KRM-REEL Datasheet

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Preliminary Technical Data

PRELIMINARY TECHNICAL DATA

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

a

ADP3415

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2002

Dual MOSFET Driver

with Bootstrapping

FUNCTIONAL BLOCK DIAGRAM

VCC

BST

DRVH

SW

DLY

GND

DRVL

ADP3415

SD

DRVLSD

IN

OVERLAP

PROTECTION

CIRCUIT

UVLO

VCC

FEATURES
All-In-One Synchronous Buck Driver
One PWM Signal Generates Both Drives
Anticross-Conduction Protection Circuitry
Programmable Transition Delay
Zero-Crossing Synchronous Drive Control
Synchronous Override Control
Undervoltage Lockout
Shutdown Quiescent Current < 10 mA

APPLICATIONS
Mobile Computing CPU Core Power Converters
Multiphase Desktop CPU Supplies
Single-Supply Synchronous Buck Converters
Standard-to-Synchronous Converter Adaptations

GENERAL DESCRIPTION

The ADP3415 is a dual MOSFET driver optimized for driving
two N-channel FETs that are the two switches in the noniso­lated synchronous buck power converter topology. The driver
sizes are each optimized for performance in notebook PC regula­tors for CPUs in the 20-amp range. The high-side driver can be
bootstrapped atop the switched node of the buck converter as
needed to drive the upper switch, and is designed to accommo­date the high voltage slew-rate associated with high-performance
high-frequency switching. The ADP3415 has several features: an
overlapping protection circuit (OPC) undervoltage lockout (UVLO)
that holds the switches off until the driver is assured of having
sufficient voltage for proper operation, a programmable transition
delay, and a synchronous drive disable pin. The quiescent
current, when the device is disabled, is less than 100 mA.

The ADP3415 is available in a 10-lead MSOP package.

BST

DRVH

SW

SD

IN

DRVLSD

DLY

GND

DRVL

ADP3415

V

DC-IN

V

OUT

5V

FROM SYSTEM

ENABLE CONTROL

FROM DUTY RATIO

MODULATOR

FROM SYSTEM

STATE LOGIC

VCC

Figure 1. Typical Application Circuit

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PRELIMINARY TECHNICAL DATA

–2–

ADP3415–SPECIFICATIONS

1

(TA = 0ⴗC to 100ⴗC, VCC = 5 V, V

BST

= 4 V to 26 V, SD = 5 V, unless otherwise noted.)

Parameter Symbol Conditions Min Typ Max Unit

SUPPLY (VCC)

Supply Voltage Range 4.15 5.0 6.0 V
Quiescent Current I

CCQ

Shutdown Mode V

SD

= 0.8 V 30 65 µA

Operating Mode V

SD

= 5 V, No Switching 1.2 2 mA

UNDERVOLTAGE LOCKOUT(

UVLO)

UVLO Threshold

V

CCUVLO

3.9 4.15 4.5 V

UVLO Hysteresis V

CCHUVLO

0.05 V

SYNCHRONOUS RECTIFIER
SHUTDOWN (DRVLSD)

Input Voltage High

2

V

IH

2.0 V

Input Voltage Low

2

V

IL

0.8 V

Propagation Delay

2, 3

tpdl

DRVLSD

VCC = 4.6 V, 23 50 ns

(See Figure 3) tpdh

DRVLSD

C

LOAD(DRVL)

= 3 nF 17 30 ns

SHUTDOWN (SD)

Input Voltage High

2

V

IH

2.0 V

Input Voltage Low

2

V

IL

0.8 V

INPUT (IN)

Input Voltage High

2

V

IH

2.0 V

Input Voltage Low

2

V

IL

0.8 V

THERMAL SHUTDOWN(THSD)

THSD Threshold T

SD

165 °C

THSD Hysteresis T

HSD

10 °C

HIGH-SIDE DRIVER (DRVH)

Output Resistance, DRVH–BST V

BST

– VSW = 4.6 V 1.5 3.5 Ω

Output Resistance, DRVH–SW V

BST

– VSW = 4.6 V .85 2 Ω

DRVH Transition Times

3

tr

DRVH

,V

BST

– VSW = 4.6 V, C

LOAD

= 3 nF 20 30 ns

(See Figure 4) tf

DRVH

25 35 ns

DRVH Propagation Delay

3, 4

tpdh

DRVH,

V

BST

– VSW = 4.6 V,

V

DLY

= 0 V 10 22 40 ns

(See Figure 4) tpdl

DRVH

40 50 ns

LOW-SIDE DRIVER (DRVL)

Output Resistance, DRVL–VCC VCC = 4.6 V 1.6 3

Ω

Output Resistance, DRVL–GND VCC = 4.6 V 1 3

Ω

DRVL Transition Times

3

tr

DRVL

,V

CC

= 4.6 V, C

LOAD

= 3 nF 27 40 ns

(See Figure 4) tf

DRVL

24 30 ns

DRVL Propagation Delay

3, 4, 6

tpdh

DRVL,

VCC = 4.6 V 5 33 38 ns

(See Figure 4) tpdl

DRVL

14 25 ns

SW Transition Timeout

6

t

SWTO

100 300 ns

Zero-Crossing Threshold V

ZC

1V

DRVH TURN-ON DELAY TIMER t

DLY

Programmable Delay

7

0 ≤ R

DLY

≤ 100 kΩ 0 100 µs

100 kΩ ≤ R

DLY

including open 100 200 µs

Delay Slope7 ⌬t

DLY/RDLY

0 ≤ R

DLY

≤ 100 kΩ 0 1 1.2 ks/kΩ

NOTES

1

All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.

2

Logic inputs meet typical CMOS I/O conditions for source current larger than 100 µA.

3

Guaranteed by characterization.

4

For propagation delays, “tpdh” refers to the specified signal going high, “tpdl” refers to it going low.

5

Propagation delay measured until DRVL begins its transition.

6

The turn-on of DRVL is initiated after IN goes low by either VSW crossing a ~1 V threshold or by expiration of t

SWTO

.

7

This delay represents a programmable extension to the propagation delay of DRVH assertion (t

PDH

DRVH). The additional delay is a linear function of the range

0 ≤ R

DLY

≤ 100 kΩ delay resistor tied from DLY to GND if its value is the specified resistance.

8

The DLY pin may be grounded for no additional delay.

Specifications subject to change without notice.

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PRELIMINARY TECHNICAL DATA

–3–

ADP3415

PIN FUNCTION DESCRIPTIONS

Pin Mnemonic Function

1 IN TTL-Level Input Signal. Has primary control of the drive outputs.
2 SD Shutdown. When high, this pin enables normal operation. When low, DRVH and DRVL are forced low

and the supply current (I

CCQ)

) is minimized as specified.

3 DRVLSD Drive-Low Shutdown. When DRVLSD is low, DRVL is kept low. When DRVLSD is high, DRVL is

enabled and controlled by IN and by the adaptive OPC function.

4 DLY High-Side Turn-On Delay. A resistor from this pin to ground programs an extended delay from turn-off

of the lower FET to turn-on of the upper FET.

5 VCC Input Supply. This pin should be bypassed to GND with ~10 µF ceramic capacitor.

6 DRVL Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) FET.

7 GND Ground. Should be directly connected to the ground plane, close to the source of the lower FET.

8 SW This pin should be connected to the buck switching node, close to the upper FET’s source. It is the

floating return for the upper FET drive signal. Also, it is used to monitor the switched voltage for the
OPC function.

9 DRVH Buck Drive. Output drive for the upper (buck) FET.

10 BST Floating Bootstrap Supply for the Upper FET. A capacitor connected between BST and SW pins holds

this bootstrapped supply voltage for the high-side FET driver as it is switched. The capacitor should be a
MLC type and should have substantially greater capacitance (e.g., ~20⫻) than the input capacitance of
the upper FET.

ORDERING GUIDE

Temperature Package Package
Model Range Description Option

ADP3415KRM-Reel 0°C to 100°C

Mini_SO Package

RM-10

MSOP-10)

ADP3415KRM-Reel7 0°C to 100°C

Mini_SO Package

RM-10

(MSOP-10)

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADP3415 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

BST to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +30 V

BST to SW . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

SW to GND . . . . . . . . . . . . . . . . . . . . . . . . . –2.0 V to +25 V

SD, IN, DRVLSD to GND . . . . . . . . . . . . . –0.3 V to +7.3 V

Operating Ambient Temperature Range . . . . . . 0°C to 100°C

Operating Junction Temperature Range . . . . . . 0°C to 125°C

θ

JA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155°C/W

θ

JC

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/W

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300°C

*This is a stress rating only; operation beyond these limits can cause the device to

be permanently damaged.

PIN CONFIGURATION

10-Lead Mini_SO Package (MSOP)

(RM-10)

TOP VIEW

(Not to Scale)

10

9

8

7

6

1

2

3

4

5

IN

SD

DRVLSD

DLY

BST

DRVH

SW

GND

ADP3415

VCC

DRVL