Analog Devices ADP3412JR Datasheet

Dual MOSFET Driver

VCC

BST

DRVH

SW

DRVL

PGND

IN

DLY

OVERLAP

PROTECTION

CIRCUIT

ADP3412

a

FEATURES
All-In-One Synchronous Buck Driver
Bootstrapped High-Side Drive
One PWM Signal Generates Both Drives
Programmable Transition Delay
Anticross-Conduction Protection Circuitry

APPLICATIONS
Multiphase Desktop CPU Supplies
Mobile Computing CPU Core Power Converters
Single-Supply Synchronous Buck Converters
Standard-to-Synchronous Converter Adaptations

GENERAL DESCRIPTION

The ADP3412 is a dual MOSFET driver optimized for driving
two N-channel MOSFETs which are the two switches in a
nonisolated synchronous buck power converter. Each of the
drivers is capable of driving a 3000 pF load with a 20 ns propa­gation delay and a 30 ns transition time. One of the drivers can
be bootstrapped, and is designed to handle the high-voltage
slew rate associated with “floating” high-side gate drivers. The
ADP3412 includes overlapping drive protection (ODP) to pre­vent shoot-through current in the external MOSFETs.

with Bootstrapping

ADP3412

FUNCTIONAL BLOCK DIAGRAM

5V

VCC

ADP3412

IN

DLY

C

DLY

1V

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

Figure 1. General Application Circuit

DELAY

1V

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

D1

BST

DRVH

SW

DRVL

PGND

12V

C

BST

Q1

Q2

1

ADP3412–SPECIFICATIONS

Parameter Symbol Conditions Min Typ Max Unit

SUPPLY

Supply Voltage Range VCC 4.15 5.0 7.5 V
Quiescent Current ICC

PWM INPUT

Input Voltage High
Input Voltage Low

2

2

HIGH-SIDE DRIVER

Output Resistance, Sourcing Current V
Output Resistance, Sinking Current V
Transition Times
Propagation Delay

3

(See Figure 2) tr

3, 4

(See Figure 2) tpdh

LOW-SIDE DRIVER

Output Resistance, Sourcing Current VCC = 4.6 V 2.5 5 Ω
Output Resistance, Sinking Current VCC = 4.6 V 2.5 5 Ω
Transition Times
Propagation Delay

NOTES

1

All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.

2

Logic inputs meet typical CMOS I/O conditions for source/sink current (~1 µA).

3

AC specifications are guaranteed by characterization, but not production tested.

4

For propagation delays, “tpdh” refers to the specified signal going high; “tpdl” refers to it going low.

5

Maximum propagation delay = 40 ns + (1 ns/pF  C

Specifications subject to change without notice.

3

(See Figure 2) tr

3, 4

(See Figure 2) tpdh

DRVH

tpdl

DRVL

tpdl

DLY

Q

, tf

DRVH

DRVH

, tf

DRVL

DRVL

).

(TA = 0ⴗC to 70ⴗC, VCC = 5 V, BST = 4 V to 26 V, unless otherwise noted.)

12 mA

2.0 V

– VSW = 4.6 V 2.5 5 Ω

BST

– VSW = 4.6 V 2.5 5 Ω

BST

V

– V

DRVH

DRVL

= 4.6 V, C

SW

– V

= 4.6 V 10 20 Note 5 ns

SW

– V

= 4.6 V 25 ns

SW

V
V

BST

BST

BST

VCC = 4.6 V, C

LOAD

= 3 nF 20 35 ns

LOAD

= 3 nF 20 35 ns
VCC = 4.6 V 30 ns
VCC = 4.6 V 25 ns

0.8 V

ABSOLUTE MAXIMUM RATINGS*

VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +8 V

BST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +30 V

BST to SW . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +8 V

SW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –5.0 V to +25 V

IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V

Operating Ambient Temperature Range . . . . . . . 0°C to 70°C

Operating Junction Temperature Range . . . . . . 0°C to 125°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155°C/W

θ

JA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/W

θ

JC

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C

*This is a stress rating only; operation beyond these limits can cause the device to

be permanently damaged. Unless otherwise specified, all voltages are referenced
to PGND.

–2–

REV. 0

ADP3412

PIN FUNCTION DESCRIPTIONS

Pin Mnemonic Function

1 BST Floating Bootstrap Supply for the Upper MOSFET. A capacitor connected between BST and SW pins

holds this bootstrapped voltage for the high-side MOSFET as it is switched. The capacitor should be

chosen between 100 nF and 1 F.
2 IN TTL-level Input Signal, which has primary control of the drive outputs.
3 DLY Low-High Transition Delay. A capacitor from this pin to ground programs the propagation delay from

turn-off of the lower FET to turn-on of the upper FET. The formula for the low-high transition delay

is DLY = C
4 VCC Input Supply. This pin should be bypassed to PGND with ~1 µF ceramic capacitor.
5 DRVL Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET.
6 PGND Power Ground. Should be closely connected to the source of the lower MOSFET.
7 SW This pin is connected to the buck-switching node, close to the upper MOSFET’s source. It is the floating

return for the upper MOSFET drive signal. It is also used to monitor the switched voltage to prevent turn-

on of the lower MOSFET until the voltage is below ~1 V. Thus, according to operating conditions, the

high-low transition delay is determined at this pin.
8 DRVH Buck Drive. Output drive for the upper (buck) MOSFET.

× (1 ns/pF) + 20 ns. The rise time for turn-on of the upper FET is not included in the formula.

DLY

PIN CONFIGURATION

BST

DLY

VCC

1

2

IN

3

4

ADP3412

TOP VIEW

(Not to Scale)

8

7

6

5

DRVH

SW

PGND

DRVL

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADP3412JR 0°C to 70°C 8-Lead Standard Small Outline Package (SOIC) R-8

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although

WARNING!

the ADP3412 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

ESD SENSITIVE DEVICE

REV. 0

–3–

ADP3412

DRVL

IN

DRVL

tf

DRVL

tpdl

DRVH

tr

DRVL

tpdl

DRVH-SW

SW

tpdh

DRVH

tr

DRVH

V

TH

tf

DRVH

V

TH

tpdh

DRVL

1V

Figure 2. Nonoverlap Timing Diagram

(Timing Is Referenced to the 90% and 10% Points Unless Otherwise Noted)

–4–

REV. 0

Typical Performance Characteristics–ADP3412

JUNCTION TEMPERATURE – ⴗC

11.0

10.5

9.0
0 12525

SUPPLY CURRENT – mA

50 75 100

10.0

9.5

VCC = 5V
f

IN

= 250kHz

C

LOAD

= 3nF

2V/DIV

DRVH

DRVL

VOLTAGE

IN

VCC = 5V

= 3nF

C

LOAD

= 0V

V

20ns/DIV

TIME – ns

SW

TPC 1. DRVH Fall and DRVL Rise
Times

35

VCC = 5V

= 3nF

C

LOAD

30

TIME – ns

25

20

15

10

5

0

0

RISE TIME

FALL TIME

50 75

AMBIENT TEMPERATURE – ⴗC

8525

TPC 4. DRVL Rise and Fall Times vs.
Temperature

2V/DIV

DRVL

DRVH

VOLTAGE

IN

VCC = 5V

= 3nF

C

LOAD

= 20pF

C

20ns/DIV

TIME – ns

DLY

TPC 2. DRVL Fall and DRVH Rise
Times

40

VCC = 5V
T

= 25ⴗC

A

30

20

TIME – ns

10

DRVH

DRVL

0

0

2345

CAPACITANCE – nF

61

TPC 5. DRVH and DRVL Rise Times
vs. Load Capacitance

30

VCC = 5V

= 3nF

C

LOAD

25

RISE TIME

FALL TIME

50 75

JUNCTION TEMPERATURE – ⴗC

8525

TIME – ns

20

15

10

5

0

0

TPC 3. DRVH Rise and Fall Times vs.
Temperature

35

VCC = 5V
T

= 25ⴗC

A

30

25

DRVH

DRVL

123456

CAPACITANCE – nF

TIME – ns

20

15

10

5

0

0

TPC 6. DRVH and DRVL Fall Times
vs. Load Capacitance

30

VCC = 5V
C

25

20

15

TIME – ns

10

5

0

0

TPC 7. Propagation Delay vs.
Temperature

REV. 0

= 3nF

LOAD

tpdl

DRVH

tpdl

DRVL

25

50 75

JUNCTION TEMPERATURE – ⴗC

100 125

40

VCC = 5V
T

= 25ⴗC

A

SUPPLY CURRENT – mA

35

30

25

20

15

10

= 3nF

C

LOAD

5

0

0

IN FREQUENCY – kHz

TPC 8. Supply Current vs.
Frequency

–5–

1200200 400 600 800 1000

TPC 9. Supply Current vs.
Temperature

ADP3412

THEORY OF OPERATION

The ADP3412 is a dual MOSFET driver optimized for driving
two N-channel MOSFETs in a synchronous buck converter
topology. A single PWM input signal is all that is required to
properly drive the high-side and the low-side FETs. Each driver
is capable of driving a 3 nF load with only a 20 ns transition time.

A more detailed description of the ADP3412 and its features
follows. Refer to the general application circuit in Figure 1.

Low-Side Driver

The low-side driver is designed to drive low-R

DS(ON)

N-channel
MOSFETs. The maximum output resistance for the driver is
5 Ω for both sourcing and sinking gate current. The low output
resistance allows the driver to have 20 ns rise and fall times into
a 3 nF load. The bias to the low-side driver is internally con­nected to the VCC supply and PGND.

The driver’s output is 180 degrees out of phase with the PWM
input.

High-Side Driver

The high-side driver is designed to drive a floating low R

DS(ON)

N-channel MOSFET. The maximum output resistance for the
driver is 5 Ω for both sourcing and sinking gate current. The
low output resistance allows the driver to have 20 ns rise and fall
times into a 3 nF load. The bias voltage for the high-side driver
is developed by an external bootstrap supply circuit, which is
connected between the BST and SW pins.

The bootstrap circuit comprises a diode, D1, and bootstrap
capacitor, C

. When the ADP3412 is starting up, the SW pin

BST

is at ground, so the bootstrap capacitor will charge up to VCC
through D1. When the PWM input goes high, the high-side
driver will begin to turn ON the high-side MOSFET, Q1, by
pulling charge out of C
rise up to V

, forcing the BST pin to VIN + V

IN

. As Q1 turns ON, the SW pin will

BST

C(BST)

, which is
enough gate-to-source voltage to hold Q1 ON. To complete the
cycle, Q1 is switched OFF by pulling the gate down to the volt­age at the SW pin. When the low-side MOSFET, Q2, turns
ON, the SW pin is pulled to ground. This allows the bootstrap
capacitor to charge up to VCC again. The high-side driver’s
output is in phase with the PWM input.

Overlap Protection Circuit

The Overlap Protection Circuit (OPC) prevents both of the
main power switches, Q1 and Q2, from being ON at the same
time. This is done to prevent shoot-through currents from flow­ing through both power switches and the associated losses that
can occur during their ON-OFF transitions. The Overlap Pro­tection Circuit accomplishes this by adaptively controlling the
delay from Q1’s turn OFF to Q2’s turn ON, and by externally
setting the delay from Q2’s turn OFF to Q1’s turn ON.

To prevent the overlap of the gate drives during Q1’s turn OFF
and Q2’s turn ON, the overlap circuit monitors the voltage at
the SW pin. When the PWM input signal goes low, Q1 will begin
to turn OFF (after a propagation delay), but before Q2 can turn
ON, the overlap protection circuit waits for the voltage at the SW
pin to fall from V

to 1 V. Once the voltage on the SW pin has

IN

fallen to 1 V, Q2 will begin turn ON. By waiting for the voltage
on the SW pin to reach 1 V, the overlap protection circuit ensures
that Q1 is OFF before Q2 turns on, regardless of variations in
temperature, supply voltage, gate charge, and drive current.

To prevent the overlap of the gate drives during Q2’s turn OFF
and Q1’s turn ON, the overlap circuit provides a programmable
delay that is set by a capacitor on the DLY pin. When the PWM
input signal goes high, Q2 will begin to turn OFF (after a propa­gation delay), but before Q1 can turn ON the overlap protection
circuit waits for the voltage at DRVL to drop to around 10% of
VCC. Once the voltage at DRVL has reached the 10% point,
the overlap protection circuit will wait for a 20 ns typical propa­gation delay plus an additional delay based on the external
capacitor, C

. The delay capacitor adds an additional 1 ns/pF

DLY

of delay. Once the programmable delay period has expired, Q1
will begin turn ON. The delay allows time for current to com­mutate from the body diode of Q2 to an external Schottky diode,
which allows turnoff losses to be reduced. Although not as fool­proof as the adaptive delay, the programmable delay adds a
safety margin to account for variations in size, gate charge, and
internal delay of the external power MOSFETs.

APPLICATION INFORMATION
Supply Capacitor Selection

For the supply input (VCC) of the ADP3412, a local bypass
capacitor is recommended to reduce the noise and to supply some
of the peak currents drawn. Use a 1 µF, low ESR capacitor.
Multilayer ceramic chip (MLCC) capacitors provide the best
combination of low ESR and small size and can be obtained from
the following vendors:

Murata GRM235Y5V106Z16 www.murata.com

Taiyo­Yuden EMK325F106ZF www.t-yuden.com

Tokin C23Y5V1C106ZP www.tokin.com

Keep the ceramic capacitor as close as possible to the ADP3412.

Bootstrap Circuit

The bootstrap circuit uses a charge storage capacitor (C

BST

) and
a Schottky diode, as shown in Figure 1. Selection of these com­ponents can be done after the high-side MOSFET has been
chosen.

The bootstrap capacitor must have a voltage rating that is able
to handle the maximum battery voltage plus 5 volts. A minimum
50 V rating is recommended. The capacitance is determined
using the following equation:

Q

GATE

=

V

∆

BST

where, Q
and ∆V

BST

C

BST

is the total gate charge of the high-side MOSFET,

GATE

is the voltage droop allowed on the high-side MOSFET
drive. For example, the IRF7811 has a total gate charge of about
20 nC. For an allowed droop of 200 mV, the required boot­strap capacitance is 100 nF. A good quality ceramic capacitor
should be used.

A Schottky diode is recommended for the bootstrap diode due
to its low forward drop, which maximizes the drive available for
the high-side MOSFET. The bootstrap diode must have a mini­mum 40 V rating to withstand the maximum battery voltage
plus 5 V. The average forward current can be estimated by:

fQI ×≈

MAXGATEF(AVG)

–6–

REV. 0

ADP3412

where f

is the maximum switching frequency of the control-

MAX

ler. The peak surge current rating should be checked in-circuit,
since this is dependent on the source impedance of the 5 V sup­ply, and the ESR of C

BST

.

Delay Capacitor Selection

The delay capacitor, C

, is used to add an additional delay

DLY

when the low-side FET drive turns off and when the high-side
drive starts to turn on. The delay capacitor adds 1 ns/pF of
additional time to the 20 ns of fixed delay.

If a delay capacitor is required, look for a good quality ceramic
capacitor with an NPO or COG dielectric, or for a good quality
mica capacitor. Both types of capacitors are available in the 1 pF
to 100 pF range and have excellent temperature and leakage
characteristics.

60.4k⍀

C

OC

1.4nF

1.1k⍀

270␮F ⴛ 4

V

12V

RTN

V

IN

FROM

CPU

R

A

R

B

R

Z

10k⍀

C2

100pF

OS-CON 16V

IN

R1

1k⍀

C12

1

2

3

4

5

6

7

8

C1
150pF

ADP3160

VID4

VID3

VID2

VID1

VID0

COMP

FB

CT

C14C13

4.7␮F

U1

VCC

REF

CS–

PWM1

PWM2

CS+

PWRGND

GND

C15

R6

10⍀

C4

16

15

14

13

12

11

10

C21

15nF

R8

ZMM5236BCT

330⍀

C23

330pF

C22
1nF

9

C26

4.7␮F

2.4k⍀

R7

20⍀

R4

4m⍀

Q5
2N3904

C5
1␮F

MBR052LTI

MBR052LTI

D2

R5

Z1

C6

1␮F

Printed Circuit Board Layout Considerations

Use the following general guidelines when designing printed
circuit boards:

1. Trace out the high-current paths and use short, wide traces
to make these connections.

2. Connect the PGND pin of the ADP3412 as close as pos­sible to the source of the lower MOSFET.

3. The VCC bypass capacitor should be located as close as
possible to VCC and PGND pins.

Typical Application Circuits

The circuit in Figure 3 shows how two drivers can be com­bined with the ADP3160 to form a total power conversion
solution for V

CC(CORE)

generation in a high-current GOA com­puter. Figure 4 gives CPU a similar application circuit for a
35 A processor.

D1

C8
15pF

1

2

3

4

C7
15pF

ADP3412

BST

1

2

IN

3

DLY

4

VCC

ADP3412

BST

IN

DLY

VCC

U3

U2

DRVH

PGND

DRVL

DRVH

SW

PGND

DRVL

SW

C10
1␮F

8

7

6

5

C9

1␮F

8

7

6

5

Q1
FDB7030L

Q2
FDB8030L

+++ + + + + +

C11 C16 C17 C18 C19 C20 C21 C22

Q3

FDB7030L

Q4

FDB8030L

L1

600nH

1200␮F ⴛ 8

OS-CON 2.5V

11m⍀ ESR (EACH)

L2

600nH

V

CC(CORE)

1.1V – 1.85V

53.4A

V

CC(CORE)

RTN

REV. 0

Figure 3. 53.4 A Intel CPU Supply Circuit

–7–

ADP3412

V

IN

5V

V

RTN

IN

12V V

CC

12V V

RTN

CC

R

A

14.7k⍀

C

OC

1nF

R

R

Z

10k⍀

22.1k⍀

100pF

RUBYCON ZA SERIES

C12

FROM

CPU

B

C1
150pF

R1

1k⍀

C2

1000␮F ⴛ 6

ADP3160

VID4

1

2

VID3

3

VID2

4

VID1

VID0

5

COMP

6

FB

7

CT

8

C15C14C13

4.7␮F

U1

VCC

REF

CS–

PWM1

PWM2

CS+

PWRGND

GND

C25C24

R6

10⍀

C4

16

15

14

13

12

11

10

C21

15nF

R8
330⍀

C23

330pF

C22
1nF

9

R7

20⍀

C26

4.7␮F

R5

2.4k⍀

Z1

ZMM5236BCT

C6

1␮F

MBR052LTI

Q5
2N3904

C5
1␮F

D2

MBR052LTI

D1

C8
15pF

R4

5m⍀

1

2

3

4

C7
15pF

ADP3412

BST

1

2

IN

3

DLY

4

VCC

U3

ADP3412

BST

DRVH

IN

DLY

PGND

VCC

DRVL

U2

DRVH

PGND

DRVL

SW

SW

1␮F

C10
1␮F

8

7

6

5

C9

8

7

6

5

Q1
FDB6035AL

Q2
FDB7030L

RUBYCON ZA SERIES

+ ++ + + + + +

C11 C16 C17 C18 C19 C20 C27 C28

Q3
FDB6035AL

Q4
FDB7030L

L1

600nH

1000␮F ⴛ 8

24m⍀ ESR (EACH)

L2

600nH

V

CC(CORE)

1.1V – 1.85V
35A

V

CC(CORE)

RTN

C01023–2.5–9/00 (rev. 0)

Figure 4. 35 A Athlon CPU Supply Circuit

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

8-Lead Small Outline Package

(R-8)

0.1968 (5.00)

0.1890 (4.80)

0.1574 (4.00)

0.1497 (3.80)

PIN 1

0.0098 (0.25)

0.0040 (0.10)

SEATING

85

0.0500 (1.27)

PLANE

0.2440 (6.20)

0.2284 (5.80)

41

BSC

0.0192 (0.49)

0.0138 (0.35)

0.102 (2.59)

0.094 (2.39)

0.0098 (0.25)

0.0075 (0.19)

0.0196 (0.50)

0.0099 (0.25)

8ⴗ
0ⴗ

0.0500 (1.27)

0.0160 (0.41)

ⴛ 45ⴗ

PRINTED IN U.S.A.

–8–

REV. 0