Analog Devices ADP3412 a Datasheet
Dual MOSFET Driver
a
FEATURES
All-In-One Synchronous Buck Driver
Bootstrapped High Side Drive
One PWM Signal Generates Both Drives
Programmable Transition Delay
Anticross-Conduction Protection Circuitry
APPLICATIONS
Multiphase Desktop CPU Supplies
Mobile Computing CPU Core Power Converters
Single-Supply Synchronous Buck Converters
Standard-to-Synchronous Converter Adaptations
GENERAL DESCRIPTION
The ADP3412 is a dual MOSFET driver optimized for driving
two N-channel MOSFETs which are the two switches in a
nonisolated synchronous buck power converter. Each of the
drivers is capable of driving a 3000 pF load with a 20 ns propagation delay and a 30 ns transition time. One of the drivers can
be bootstrapped and is designed to handle the high voltage
slew rate associated with “floating” high side gate drivers. The
ADP3412 includes overlapping drive protection (ODP) to prevent shoot-through current in the external MOSFETs.
with Bootstrapping
FUNCTIONAL BLOCK DIAGRAM
VCC
ADP3412
IN
OVERLAP
DLY
PROTECTION
CIRCUIT
ADP3412
BST
DRVH
SW
DRVL
PGND
ADP3412
IN
DLY
C
DLY
1V
DELAY
Figure 1. General Application Circuit
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
5V
VCC
1V
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2002
D1
BST
DRVH
SW
DRVL
PGND
12V
C
BST
Q1
Q2
1
ADP3412–SPECIFICATIONS
Parameter Symbol Conditions Min Typ Max Unit
SUPPLY
Supply Voltage Range VCC 4.15 5.0 7.5 V
Quiescent Current ICC
PWM INPUT
Input Voltage High
Input Voltage Low
2
2
HIGH SIDE DRIVER
Output Resistance, Sourcing Current V
Output Resistance, Sinking Current V
Transition Times
Propagation Delay
3
(See Figure 2) tr
3, 4
(See Figure 2) tpdh
LOW SIDE DRIVER
Output Resistance, Sourcing Current VCC = 4.6 V 2.5 5 Ω
Output Resistance, Sinking Current VCC = 4.6 V 2.5 5 Ω
Transition Times
Propagation Delay
NOTES
1
All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.
2
Logic inputs meet typical CMOS I/O conditions for source/sink current (~1 µA).
3
AC specifications are guaranteed by characterization but not production tested.
4
For propagation delays, “tpdh” refers to the specified signal going high; “tpdl” refers to it going low.
5
Maximum propagation delay = 40 ns + (1 ns/pF C
Specifications subject to change without notice.
3
(See Figure 2) tr
3, 4
(See Figure 2) tpdh
DRVH
tpdl
DRVL
tpdl
DLY
Q
, tf
DRVH
DRVH
, tf
DRVL
DRVL
).
(TA = 0ⴗC to 70ⴗC, VCC = 5 V, BST = 4 V to 26 V, unless otherwise noted.)
12 mA
2.0 V
– VSW = 4.6 V 2.5 5 Ω
BST
– VSW = 4.6 V 2.5 5 Ω
BST
V
– V
DRVH
DRVL
= 4.6 V, C
SW
– V
= 4.6 V 10 20 Note 5 ns
SW
– V
= 4.6 V 25 ns
SW
V
V
BST
BST
BST
VCC = 4.6 V, C
LOAD
= 3 nF 20 35 ns
LOAD
= 3 nF 20 35 ns
VCC = 4.6 V 30 ns
VCC = 4.6 V 25 ns
0.8 V
ABSOLUTE MAXIMUM RATINGS*
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +8 V
BST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +30 V
BST to SW . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +8 V
SW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –5.0 V to +25 V
IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V
Operating Ambient Temperature Range . . . . . . . 0°C to 70°C
Operating Junction Temperature Range . . . . . . 0°C to 125°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155°C/W
θ
JA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/W
θ
JC
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C
*This is a stress rating only; operation beyond these limits can cause the device to
be permanently damaged. Unless otherwise specified, all voltages are referenced
to PGND.
–2–
REV. A
ADP3412
PIN FUNCTION DESCRIPTIONS
Pin Mnemonic Function
1 BST Floating Bootstrap Supply for the Upper MOSFET. A capacitor connected between BST and SW Pins
holds this bootstrapped voltage for the high side MOSFET as it is switched. The capacitor should be
chosen between 100 nF and 1 F.
2IN TTL-level input signal that has primary control of the drive outputs.
3 DLY Low High Transition Delay. A capacitor from this pin to ground programs the propagation delay from
turn-off of the lower FET to turn-on of the upper FET. The formula for the low high transition delay
is DLY = C
4 VCC Input Supply. This pin should be bypassed to PGND with ~1 µF ceramic capacitor.
5 DRVL Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET.
6 PGND Power Ground. Should be closely connected to the source of the lower MOSFET.
7SW This pin is connected to the buck-switching node, close to the upper MOSFET’s source. It is the floating
return for the upper MOSFET drive signal. It is also used to monitor the switched voltage to prevent turn-
on of the lower MOSFET until the voltage is below ~1 V. Thus, according to operating conditions, the
high low transition delay is determined at this pin.
8 DRVH Buck Drive. Output drive for the upper (buck) MOSFET.
× (1 ns/pF) + 20 ns. The rise time for turn-on of the upper FET is not included in the formula.
DLY
PIN CONFIGURATION
BST
DLY
VCC
1
2
IN
3
4
ADP3412
TOP VIEW
(Not to Scale)
8
7
6
5
DRVH
SW
PGND
DRVL
ORDERING GUIDE
Model Temperature Range Package Description Package Option
ADP3412JR 0°C to 70°C 8-Lead Standard Small Outline Package (SOIC) SOIC-8
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
WARNING!
the ADP3412 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ESD SENSITIVE DEVICE
REV. A
–3–
ADP3412
DRVL
IN
DRVL
tf
DRVL
tpdl
DRVH
tr
DRVL
tpdl
DRVH-SW
SW
tpdh
DRVH
tr
DRVH
V
TH
tf
DRVH
V
TH
tpdh
DRVL
1V
Figure 2. Nonoverlap Timing Diagram
(Timing Is Referenced to the 90% and 10% Points Unless Otherwise Noted)
–4–
REV. A
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