Analog Devices ADP3408 a Datasheet

a

GSM Power Management System

ADP3408

FEATURES
Handles All GSM Baseband Power Management
6 LDOs Optimized for Specific GSM Subsystems
Li-Ion and NiMH Battery Charge Function
Optimized for the AD20msp430 Baseband Chipset

APPLICATIONS
GSM/DCS/PCS/CDMA Handsets

GENERAL DESCRIPTION

The ADP3408 is a multifunction power system chip optimized
for GSM handsets, especially those based on the Analog Devices
AD20msp430 system solution. It contains six LDOs, one to
power each of the critical GSM subblocks. Sophisticated con­trols are available for power-up during battery charging, keypad
interface, and RTC alarm. The charge circuit maintains low
current charging during the initial charge phase and provides an
end-of-charge signal when a Li-ion battery is being charged.

The ADP3408 is specified over the temperature range of –20°C to
+85°C and is available in a narrow body TSSOP 28-lead package
or 5 mm  5 mm LFCSP 32-lead package.

PWRONKEY

ROWX

PWRONIN

TCXOEN

SIMEN

RESCAP

CHRDET

EOC

CHGEN

GATEIN

BATSNS

ISENSE

GATEDR

CHRIN

FUNCTIONAL BLOCK DIAGRAM

VBAT VBAT2 VRTCIN

SIM

LDO

DIGITAL

CORE LDO

ANALOG

LDO

POWER-UP

SEQUENCING

AND

PROTECTION

LOGIC

BATTERY

CHARGE

CONTROLLER

ADP3408

TCXO

LDO

MEMORY

LDO

RTC
LDO

REF

BUFFER

BATTERY

CHARGE

DIVIDER

26

27

VSIM

VCORE

VAN

VTCXO

VMEM

VRTC

REFOUT

RESET

MVBAT

DGND

AGND

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

(Pin Assignment Is for TSSOP Option)

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2002

1

ADP3408–SPECIFICATIONS

CVMEM = 2.2 F, VTCXO = 0.22 F, CVRTC = 0.1 F, CVBAT = 10 F, minimum loads applied on all outputs, unless otherwise noted.)

Parameter Symbol Condition Min Typ Max Unit

SHUTDOWN SUPPLY CURRENT ICC

VBAT ≤ 2.5 V VBAT = VBAT2 = 2.3 V 7 20
(Deep Discharged Lockout Active)

2.5 V < VBAT ≤ 3.2 V VBAT = VBAT2 = 3.0 V 30 55
(UVLO Active)
VBAT > 3.2 V VBAT = VBAT2 = 4.0 V 45 80

OPERATING GROUND CURRENT IGND VBAT = 3.6 V

VSIM, VCORE, VMEM, VRTC On Minimum Loads 225 300
All LDOs On Minimum Loads 345 450

UVLO ON THRESHOLD VBAT 3.2 3.3 V

UVLO HYSTERESIS VBAT 200 mV

DEEP DISCHARGED LOCKOUT ON VBAT 2.4 2.75 V

THRESHOLD

DEEP DISCHARGED LOCKOUT VBAT 100 mV

HYSTERESIS

INPUT HIGH VOLTAGE V

(TCXOEN, SIMEN, 2.0 V
CHGEN, GATEIN)
PWRONIN (ADP3408-1.8) 1.1 V
PWRONIN (ADP3408-2.5) 2.0 V

INPUT LOW VOLTAGE V

(PWRONIN, TCXOEN, SIMEN,
CHGEN, GATEIN)

INPUT HIGH BIAS CURRENT I

(PWRONIN, TCXOEN, SIMEN,
CHGEN, GATEIN)

INPUT LOW BIAS CURRENT I

(PWRONIN, TCXOEN, SIMEN,
CHGEN, GATEIN)

PWRONKEY INPUT HIGH VOLTAGE V

PWRONKEY INPUT LOW VOLTAGE V

PWRONKEY INPUT PULL-UP 70 100 130 kΩ

RESISTANCE TO VBAT

THERMAL SHUTDOWN THRESHOLD

THERMAL SHUTDOWN HYSTERESIS 45 ºC

ROWX CHARACTERISTICS

ROWX Output Low Voltage V

ROWX Output High Leakage I
Current V(ROWX) = 5 V 1 µA

SIM CARD LDO (VSIM)

Output Voltage VSIM Line, Load, Temp 2.80 2.85 2.92 V
Line Regulation VSIM Min Load 2 mV
Load Regulation VSIM 50 µA ≤ I

Output Capacitor Required for Stability C
Dropout Voltage V

DIGITAL CORE LDO (VCORE)

Output Voltage

ADP3408ARU-2.5 VCORE Line, Load, Temp 2.40 2.45 2.50 V
ADP3408ARU-1.8 VCORE Line, Load, Temp 1.75 1.80 1.85 V

Line Regulation VCORE Min Load 2 mV
Load Regulation VCORE 50 µA ≤ I

Output Capacitor Required for Stability C

IH

IL

IH

IL

IH

IL

2

OL

IH

O

DO

O

(–20C ≤ TA ≤ +85C, VBAT = VBAT2 = 3 V–5.5 V, CVSIM = CVCORE = CVAN =

µ

A

µ

A

µ

A

µ

A

µ

A

Maximum Loads 1.0 3.0 % of max

load
current

0.3 V

1.0 µA

–1.0

µ

A

0.7  VBAT V

0.3  VBAT V

160 ºC

PWRONKEY = Low
IOL = 200 µA 0.4 V
PWRONKEY = High

≤ 20 mA, 1 mV

LOAD

VBAT = 3.6 V

2.2 µF
VO = V
I

LOAD

– 100 mV,

INITIAL

= 20 mA 35 100 mV

≤ 100 mA, 7 mV

LOAD

VBAT = 3.6 V

2.2 µF

–2–

REV. A

ADP3408

Parameter Symbol Condition Min Typ Max Unit

RTC LDO
REAL-TIME CLOCK LDO/
COIN CELL CHARGER (VRTC)

Maximum Output Voltage

ADP3408ARU-2.5 VRTC 1 µA ≤ I

ADP3408ARU-1.8 VRTC 1 µA ≤ I
Off Reverse Input Current I
Output Capacitor Required for Stability C

L

O

VBAT = 2.15 V, TA = 25°C 0.5 µA

ANALOG LDO (VAN)

Output Voltage VAN Line, Load, Temp 2.40 2.45 2.50 V
Line Regulation VAN Min Load 2 mV
Load Regulation VAN 50 µA ≤ I

VBAT = 3.6 V
Output Capacitor Required for Stability C
Ripple Rejection

Output Noise Voltage V

O



VBAT/ f = 217 Hz 65 dB



VAN VBAT = 3.6 V

NOISE

f = 10 Hz to 100 kHz 80 µV rms

I

LOAD

VBAT = 3.6 V

TCXO LDO (VTCXO)

Output Voltage

ADP3408-2.5 VTCXO Line, Load, Temp 2.66 2.715 2.77 V
ADP3408-1.8 VTCXO Line, Load, Temp 2.711 2.750 2.789 V

Line Regulation VTCXO Min Load 2 mV
Load Regulation VTCXO 50 µA ≤ I

VBAT = 3.6 V
Output Capacitor Required for Stability C
Dropout Voltage V

Ripple Rejection

Output Noise Voltage V

O

DO



VBAT/ f = 217 Hz 65 dB



VTCXO VBAT = 3.6 V

NOISE

VO = V

I

LOAD

f = 10 Hz to 100 kHz 80 µV rms

I

LOAD

VBAT = 3.6 V

MEMORY LDO (VMEM)

Output Voltage VMEM Line, Load, Temp 2.744 2.80 2.856 V
Line Regulation
Load Regulation



VMEM



VMEM 50 µA < I

Min Load

VBAT = 3.6 V
Output Capacitor Required for Stability C
Dropout Voltage I

O

LOAD

I

LOAD

REFOUT

Output Voltage VREFOUT Line, Load, Temp 1.19 1.210 1.23 V
Line Regulation VREFOUT Min Load 0.2 mV
Load Regulation VREFOUT 0 µA < I

VBAT = 3.6 V
Ripple Rejection VBAT/ f = 217 Hz 65 75 dB

VREFOUT VBAT = 3.6 V, I

Maximum Capacitive Load C
Output Noise Voltage V

O

NOISE

f = 10 Hz to 100 kHz, 40 µV rms

VBAT = 3.6 V

RESET GENERATOR (RESET)

Output High Voltage V
Output Low Voltage V
Output Current I

Delay Time per Unit Capacitance T
Applied to RESCAP Pin

OH

OL

OL

I

OH

D

IOH = 500 µAV

IOL = –500 µA 0.25 V

V

OL

VOH = V

BATTERY VOLTAGE DIVIDER

Divider Ratio BATSNS/MVBAT TCXOEN = High 2.32 2.35 2.37
Divider Impedance at MVBAT Z

O

Divider Leakage Current TCXOEN = Low 1
Divider Resistance TCXOEN = High 215 300 385 kΩ

≤ 10 µA 2.39 2.45 2.51 V

LOAD

≤ 10 µA 1.80 1.95 2.1 V

LOAD

0.1 µF

≤ 130 mA, 8 mV

LOAD

2.2 µF

= 130 mA

≤ 20 mA, 1 mV

LOAD

0.22 µF

– 100 mV 160 310 mV

INITIAL

= 20 mA

= 20 mA,

2mV

< 60 mA, 3 mV

LOAD

2.2 µF
= 60 mA 80 180 mV
= 80 mA 107 210 mV

< 50 µ

LOAD

LOAD

A

= 50 µA

0.5 mV

100 pF

– 0.25 V

MEM

= 0.25 V, 1 mA

– 0.25 V 1 mA

MEM

0.6 1.2 2.4 ms/nF

59.5 85 110 kΩ

µ

A

REV. A

–3–

ADP3408

Parameter Symbol Condition Min Typ Max Unit

BATTERY CHARGER

Charger Output Voltage BATSNS 4.35 V ≤ CHRIN ≤ 10 V

CHGEN = Low, No Load
CHRIN = 10 V 4.155 4.230 V
CHGEN = Low, No Load
0C < TA < 50C

Load Regulation ∆BATSNS CHRIN = 5 V 15 mV

0 ≤ CHRIN – ISENSE
< Current Limit Threshold

CHGEN = Low
CHRDET On Threshold CHRIN – BATSNS 30 90 150 mV
CHRDET Hysteresis 40 mV
CHRDET Off Delay

4

CHRIN < VBAT 6 ms/nF
CHRIN Supply Current CHRIN = 5 V 0.6 mA

BATTERY CHARGER

Current Limit Threshold CHRIN – ISENSE
High Current Limit CHRIN = 5 V DC 142 160 190 mV
(UVLO Not Active) VBAT = 3.6 V

CHGEN = Low

CHRIN = 5 V DC 149 160 180 mV

VBAT = 3.6 V

CHGEN = Low

0C < TA < 50C
Low Current Limit VBAT = 2 V 20 35 mV
(UVLO Active) CHGEN = Low

CHRIN = 5 V
ISENSE Bias Current 200 µA
End-of-Charge Signal Threshold CHRIN – ISENSE CHRIN = 5 V DC 14 35 mV

VBAT > 4.0 V

CHGEN = Low
EOC Reset Threshold VBAT CHGEN = Low 3.82 3.96 4.10 V
GATEDR Transition Time tR, t

F

CHRIN = 5 V 0.1 1 µs

VBAT > 3.6 V

CHGEN = High, CL = 2 nF
GATEDR High Voltage V

OH

CHRIN = 5 V 4.5 V

VBAT = 3.6 V

CHGEN = High,

GATEIN = High

IOH = –1 mA
GATEDR Low Voltage V

OL

CHRIN = 5 V 0.5 V

VBAT = 3.6 V

CHGEN = High

GATEIN = Low

I

= 1 mA

Output High Voltage V

(EOC, CHRDET)

Output Low Voltage V

(EOC, CHRDET)

OH

OL

OL

IOH = –250 µA 2.4 V

IOL = +250 µA 0.25 V

Battery Overvoltage BATSNS CHRIN = 7.5 V 5.30 5.50 5.70 V

Protection Threshold CHGEN = High

(GATEDR → High) GATEIN = Low
Battery Overvoltage BATSNS CHRIN = 7.5 V 200 mV
Protection Hysteresis CHGEN = High

GATEIN = Low

NOTES

1

All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.

2

This feature is intended to protect against catastrophic failure of the device. Maximum allowed operating junction temperature is 125ºC. Operation beyond
125ºC could cause permanent damage to the device.

3

No isolation diode present between charger input and battery.

4

Delay set by external capacitor on the RESCAP pin.

Specifications subject to change without notice.

3

4.150 4.200 4.250 V

–4–

REV. A

ABSOLUTE MAXIMUM RATINGS*

Voltage on any pin with respect to

any GND Pin . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +10 V

Voltage on any pin may not exceed VBAT, with the following

exceptions: CHRIN, GATEDR, ISENSE

Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C

Operating Ambient Temperature Range . . . . . –20°C to +85°C

Maximum Junction Temperature . . . . . . . . . . . . . . . . . 125°C

, Thermal Impedance (TSSOP-28)



JA

4-Layer JEDEC PCB . . . . . . . . . . . . . . . . . . . . . . . . 68°C/W

2-Layer SEMI PCB . . . . . . . . . . . . . . . . . . . . . . . . . 98°C/W

, Thermal Impedance (LFCSP)



JA

4-Layer JEDEC PCB . . . . . . . . . . . . . . . . . . . . . . . . 32°C/W

2-Layer SEMI PCB . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W

Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300°C

*This is a stress rating only; operation beyond these limits can cause the device

to be permanently damaged.

ORDERING GUIDE

Core LDO
Output Temperature Package

Model Voltage Range Option

ADP3408ARU-2.5 2.5 V –20°C to +85°C RU-28
ADP3408ACP-2.5 2.5 V –20°C to +85°C CP-32
ADP3408ARU-1.8 1.8 V –20°C to +85°C RU-28
ADP3408ACP-1.8 1.8 V –20°C to +85°C CP-32

ADP3408

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADP3408 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

REV. A

–5–

WARNING!

ESD SENSITIVE DEVICE

ADP3408

PIN CONFIGURATIONS

NC

32

1

2
3

4

5

6
7
8

9

GATEDR

LFCSP (CP)

ROWX

PWRONKEY

PWRONIN

TCXOEN
282726

ADP3408

TOP VIEW

ACP

11

121314

EOC

DGND

ISENSE

AGND

CHGEN

313029

PIN 1
INDICATOR

(Not to Scale)

TOP VIEW

10

NC

REFOUT

VTCXO
25

16

15

RESET

RESCAP

24
23
22

21

20

19
18
17

PWRONIN

PWRONKEY

ROWX

SIMEN

VRTCIN

VRTC

BATSNS

MVBAT

CHRDET

CHRIN

GATEIN

GATEDR

DGND

ISENSE

TSSOP (RU)

1

2

3

4

5

6

ADP3408

7

ARU

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

TCXOEN

AGND

REFOUT

VTCXO

VAN

VBAT

VCORE

VMEM

VBAT2

VSIM

RESET

RESCAP

CHGEN

EOC

SIMEN

VRTCIN

VRTC

BATSNS

MVBAT

CHRDET

CHRIN

GATEIN

PIN FUNCTION DESCRIPTIONS

TSSOP LFCSP
Pin Pin Mnemonic Function

129 PWRONIN Power On/Off Signal from Microprocessor
230 PWRONKEY Power On/Off Key
331 ROWX Power Key Interface Output
41 SIMEN SIM LDO Enable
52 VRTCIN RTC LDO Input Voltage
63 VRTC Real-Time Clock Supply/Coin Cell Battery Charger
74 BATSNS Battery Voltage Sense Input
85 MVBAT Divided Battery Voltage Output
96 CHRDET Charge Detect Output
10 7 CHRIN Charger Input Voltage
11 8 GATEIN Microprocessor Gate Input Signal
12 9 GATEDR Gate Drive Output
13 11 DGND Digital Ground
14 12 ISENSE Charge Current Sense Input
15 13 EOC End of Charge Signal
16 14 CHGEN Charger Enable for GATEIN, NiMH Pulse Charging
17 15 RESCAP Reset Delay Time
18 16 RESET Main Reset
19 18 VSIM SIM LDO Output
20 19 VBAT2 Battery Input Voltage 2
21 20 VMEM Memory LDO Output
22 21 VCORE Digital Core LDO Output
23 22 VBAT Battery Input Voltage
24 23 VAN Analog LDO Output
25 25 VTCXO TCXO LDO Output
26 26 REFOUT Output Reference
27 27 AGND Analog Ground
28 28 TCXOEN TCXO LDO Enable and MVBAT Enable

10, 17, 24, 32 NC No Connection

NC

VAN
VBAT

VCORE

VMEM

VBAT2
VSIM
NC

–6–

REV. A