+5 V Fixed, Adjustable
ADP3367
IN
SHDN
LBO
LBI
GND
50mV
SET
DD
OUT
1.255V
REF
A1
C1
C2
a
FEATURES
Low Dropout: 150 mV @ 200 mA
Low Dropout: 300 mV @ 300 mA
Low Power CMOS: 17 mA Quiescent Current
Shutdown Mode: 0.2 mA Quiescent Current
300 mA Output Current Guaranteed
Pin Compatible with MAX667
Stable with 10 mF Load Capacitor
+2.5 V to +16.5 V Operating Range
Low Battery Detector
Fixed +5 V or Adjustable Output
High Accuracy: 62%
Dropout Detector Output
Low Thermal Resistance Package*
ESD > 6000 V
APPLICATIONS
Handheld Instruments
Cellular Telephones
Battery Operated Devices
Portable Equipment
Solar Powered Instruments
High Efficiency Linear Power Supplies
Low-Dropout Linear Voltage Regulator
ADP3367*
FUNCTIONAL BLOCK DIAGRAM
TYPICAL OPERATING CIRCUIT
+6V
INPUT
IN
+
ADP3367
OUT
+
C1
10µF
+5V
OUTPUT
GENERAL DESCRIPTION
GNDSET SHDN
The ADP3367 is a low-dropout precision voltage regulator that
can supply up to 300 mA output current. It can be used to give
a fixed +5 V output with no additional external components or
can be adjusted from +1.3 V to +16 V using two external
resistors. Fixed or adjustable operation can be selected via the
SET input. The low quiescent current (17 µA) in conjunction
400
TA = +50°C
with the standby or shutdown mode (0.2 µA) makes this device
especially suitable for battery powered systems. The dropout
voltage when supplying 100 µA is only 15 mV allowing opera-
300
GUARANTEED 300mA
tion with minimal headroom thereby prolonging the useful battery life. At higher output current levels the dropout remains
low increasing to just 150 mV when supplying 200 mA. A wide
input voltage range from 2.5 V to 16.5 V is allowable. Additional features include a dropout detector and a low supply/battery monitoring comparator. The dropout detector can be used
to signal loss of regulation while the low battery detector can be
used to monitor the input supply voltage.
The ADP3367 is a much improved pin-compatible replacement
for the MAX667. Improvements include lower supply current,
tighter voltage accuracy and superior line and load regulation.
Improved ESD protection (>6000 V) is achieved by advanced
voltage clamping structures. The ADP3367 is specified over the
industrial temperature range –40°C to +85°C and is available in
narrow surface mount (SOIC) packages.
ADI’s proprietary Thermal Coastline leadframe used in ADP3367AR
packaging, has 30% lower thermal resistance than the standard
leadframes. This improvement in heat flow rate results in lower
200
LOAD CURRENT – mA
100
STANDARD
SO PACKAGE
DISSIPATION LIMIT
0
015
ADP3367
DISSIPATION LIMIT
510
VIN–V
– V
OUT
Load Current vs. Input-Output Differential Voltage
die temperature hence improves reliability.
*Patent pending.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703
© Analog Devices, Inc., 1995
ADP3367–SPECIFICA TIONS
(VIN = +9 V, GND = 0 V, V
= +5 V, TA = T
OUT
MIN
to T
unless otherwise noted)
MAX
Parameter Min Typ Max Units Test Conditions/Comments
Input Voltage, V
IN
Output Voltage, V
OUT
2.5 16.5 V
4.9 5.0 5.1 V V
= 0 V, VIN = 6 V, I
SET
Maximum Output Current 200 mA VIN = +9 V, + 4.5 V < V
Quiescent Current
: Shutdown Mode 0.2 0.75 µAV
I
GND
: Normal Mode V
I
GND
17 25 µAI
20 30 µAI
514 mAI
= 2 V
SHDN
= 0 V, V
SHDN
= 0 µA
OUT
= 100 µA
OUT
= 200 mA
OUT
SET
= 0 V
Dropout Voltage
= 5 V 15 40 mV I
V
OUT
60 125 mV I
100 175 mV I
150 250 mV I
175 300 mV I
300 500 mV I
= 3.3 V 94 140 mV I
V
OUT
210 312 mV I
430 625 mV I
Load Regulation 5 10 mV I
Line Regulation 0.1 5 mV VIN = 6 V to 10 V, I
Reference Voltage, V
SET
1.23 1.255 1.28 V
= 100 µA
OUT
= 50 mA
OUT
= 100 mA
OUT
= 200 mA, TA = +25°C
OUT
= 200 mA
OUT
= 300 mA
OUT
= 50 mA
OUT
= 100 mA
OUT
= 200 mA, TA = +25°C
OUT
= 10 mA–100 mA, VIN = 6 V
OUT
= 10 mA–200 mA, VIN = 6 V
I
OUT
OUT
= 10 mA
SET Input Threshold 50 mV
SET Input Current, I
Output Leakage Current, I
Short Circuit Current, I
Low Battery Detector Input Threshold, V
SET
OUT
OUT
LBI
1.215 1.255 1.295 V
±0.01 ±10 nA V
0.1 1 µAV
= 1.5 V
SET
SHDN
= 2 V
400 mA TA = +25°C
450 mA TA = T
MIN
to T
MAX
LBI Hysteresis 6 mV
LBI Input Leakage Current, I
Low Battery Detector Output Voltage, V
LBI
LBO
±0.01 ±10 nA V
0.25 V V
0.40 V V
Shutdown Input Voltage, V
SHDN
1.5 V V
0.4 V V
Shutdown Input Current, I
SHDN
±0.01 ±10 nA V
Dropout Detector Output Voltage 0.25 V (V
4.0 (V
Specifications subject to change without notice.
= 1.5 V
LBI
= 0 V, I
LBI
= 0 V, I
LBI
IH
IL
= 0 V to V
SHDN
= 0 V, V
SET
= 7 V, I
V
IN
SET
OUT
= 0 V, V
VIN = 4.5 V, I
= 10 mA, TA = +25°C
LBO
= 10 mA, TA = T
LBO
IN
= 0 V, RDD = 100 kΩ,
SHDN
= 10 mA)
= 0 V, RDD = 100 kΩ,
SHDN
= 10 mA)
OUT
= 10 mA
OUT
< +5.5 V
OUT
MIN
to T
MAX
ABSOLUTE MAXIMUM RATINGS*
(
TA= +25°C unless otherwise noted)
Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +18 V
Output Short Circuit to GND Duration . . . . . . . . . . . . . 1 sec
LBO Output Sink Current . . . . . . . . . . . . . . . . . . . . . . . 50 mA
LBO Output Voltage . . . . . . . . . . . . . . . . . . . . . GND to V
OUT
SHDN Input Voltage . . . . . . . . . . . . . . –0.3 V to (VIN + 0.3 V)
LBI, SET Input Voltage . . . . . . . . . . . –0.3 V to (V
+ 0.3 V)
IN
Power Dissipation, R-8 . . . . . . . . . . . . . . . . . . . . . . . 960 mW
(Derate 10 mW/°C above +50°C)
θ
, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 98°C/W
JA
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . > 6000 V
*This is a stress rating only and functional operation of the device at these or any
other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods of time may affect reliability.
ORDERING GUIDE
Model Temperature Range Package Option*
ADP3367AR –40°C to +85°C SO-8
*SO = Small Outline Package.
–2–
REV. 0
ADP3367
ADP3367
IN
SHDN
LBO
LBI
GND
50mV
SET
DD
OUT
1.255V
REF
A1
C1
C2
PIN FUNCTION DESCRIPTION
Mnemonic Function
DD Dropout Detector Output. PNP collector output
GENERAL INFORMATION
The ADP3367 contains a micropower bandgap reference voltage source, an error amplifier A1, two comparators (C1, C2)
and a series PNP output pass transistor.
which sources current as dropout is reached.
V
IN
Voltage Regulator Input.
GND Ground Pin. Must be connected to 0 V.
LBI Low Battery Detect Input. Compared with 1.255 V.
LBO Low Battery Detect Output. Open Drain Output
that goes low when LBI is below the threshold.
SHDN Digital Input. May be used to disable the device
so that the power consumption is minimized.
SET Voltage Setting Input. Connect to GND for +5 V
output or connect to resistive divider for adjust-
able output.
OUT Regulated Output Voltage. Connect to filter
capacitor.
CIRCUIT DESCRIPTION
The internal bandgap voltage reference is trimmed to 1.255V
and is used as a reference input to the error amplifier A1. The
feedback signal from the regulator output is supplied to the
other input by an on-chip voltage divider or by two external
resistors. When the SET input is at ground, the internal divider
provides the error amplifier’s feedback signal giving a +5V output. When SET is at more than 50 mV above ground, comparator C1 switches the error amplifier’s input directly to the SET
pin, and external resistors are used to set the output voltage.
The external resistors are selected so that the desired output
voltage gives 1.255 V at the SET input.
The output from the error amplifier supplies base current to the
PNP output pass transistor which provides output current. Up
to 300 mA output current is available provided that the device
power dissipation is not exceeded.
DIP & SOIC PIN CONFIGURATION
Comparator C2 compares the voltage on the Low Battery Input
(LBI) pin to the internal +1.255 V reference voltage. The out-
DD
OUT
LBI
GND
1
2
ADP3367
TOP VIEW
3
(Not to Scale)
4
8
IN
7
LBO
6
SET
5
SHDN
put from the comparator drives an open drain FET connected
to the Low Battery Output pin, LBO. The Low Battery Threshold may be set using a suitable voltage divider connected to
LBI. When the voltage on LBI falls below 1.255 V, the open
drain output, LBO, is pulled low.
A shutdown (SHDN) input that can be used to disable the
error amplifier and hence the voltage output is also available.
TERMINOLOGY
The supply current in shutdown is less than 0.75 µA.
Dropout Voltage: The input/output voltage differential at
which the regulator no longer maintains regulation against further reductions in input voltage. It is measured when the output
decreases 100 mV from its nominal value. The nominal value is
the measured value with V
IN
= V
OUT
+2 V.
Line Regulation: The change in output voltage as a result of a
change in the input voltage. It is specified for a change of input
voltage from 6 V to 10 V.
Load Regulation: The change in output voltage for a change
in output current. It is specified for an output current change
from 10 mA to 200 mA.
Quiescent Current (I
): The input bias current which
GND
flows into the regulator not including load current. It is measured on the GND line and is specified in shutdown and also for
different values of load current.
Figure 1. ADP3367 Functional Block Diagram
Shutdown: The regulator is disabled and power consumption
is minimized.
Dropout Detector: An output that indicates that the regulator
is dropping out of regulation.
Maximum Power Dissipation: The maximum total device
dissipation for which the regulator will continue to operate
within specifications.
REV. 0
–3–