Analog Devices ADP3335 a Datasheet

High Accuracy, Ultralow IQ, 500 mA,

FEATURES

High accuracy over line and load: ±0.9% @ 25°C,

±1.8% over temperature
Ultralow dropout voltage: 200 mV (typ) @ 500 mA
Requires only C
anyCAP = stable with any type of capacitor

(Including MLCC)
Current and thermal limiting
Low noise
Low shutdown current: < 10 nA (typ)

2.6 V to 12 V supply range
–40°C to +85°C ambient temperature range

APPLICATIONS

PCMCIA cards
Cellular phones
Camcorders, cameras
Networking systems, DSL/cable modems
Cable set-top box
MP3/CD players
DSP supplies

= 1.0 µF for stability

O

anyCAP® Low Dropout Regulator

ADP3335

FUNCTIONAL BLOCK DIAGRAM

SD

IN

THERMAL

PROTECTION

Q1

DRIVER

GND

CC

ADP3335

gm

BANDGAP

REF

+
–

Figure 1.

5

NR

ADP3335

3

OUT
OUT
OUT
GND

2
1

++

4

C
1µF

OUT

V

OUT

IN

7

V

IN

1µF

8

OFF

IN

SD

6

ON

C

IN

Figure 2. Typical Application Circuit

R1

R1

R2

00147-0-002

OUT

NR

00147-0-001

GENERAL DESCRIPTION

The ADP3335 is a member of the ADP333x family of precision,
low dropout, anyCAP voltage regulators. It operates with an
input voltage range of 2.6 V to 12 V, and delivers a continuous
load current up to 500 mA. The ADP3335 stands out from
conventional low dropout regulators (LDOs) by using an
enhanced process enabling it to offer performance advantages
beyond its competition. Its patented design requires only a

1.0 µF output capacitor for stability. This device is insensitive to
output capacitor equivalent series resistance (ESR), and is stable
with any good quality capacitor—including ceramic (MLCC)

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

types for space-restricted applications. The ADP3335 achieves
exceptional accuracy of ±0.9% at room temperature and ±1.8%
over temperature, line, and load.

The dropout voltage of the ADP3335 is only 200 mV (typical) at
500 mA. This device also includes a safety current limit, thermal
overload protection, and a shutdown feature. In shutdown
mode, the ground current is reduced to less than 1 µA. The
ADP3335 has a low quiescent current of 80 µA (typical) in light
load situations.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

ADP3335

TABLE OF CONTENTS

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 4

Pin Configuration and Function Descriptions............................. 5

Typical Performance Characteristics ............................................. 6

Theory of Operation ........................................................................ 9

Application Information................................................................ 10

Output Capacitor Selection....................................................... 10

Input Bypass Capacitor .............................................................. 10

REVISION HISTORY

1/04 changed from Rev. 0 to Rev. A

Format updated...............................................................Universal

Renumbered figures .......................................................Universal

Removed Figure 22....................................................................... 6

Change to Printed Circuit Board

Layout Considerations section.................................................. 11

Added LFCSP Layout Considerations section........................ 11

Added Package Drawing................................................Universal

Changes to Ordering Guide...................................................... 16

Noise Reduction ......................................................................... 10

Thermal Overload Protection .................................................. 10

Calculating Junction Temperature........................................... 10

Printed Circuit Board Layout Considerations........................ 11

LFCSP Layout Considerations.................................................. 11

Shutdown Mode ......................................................................... 11

Outline Dimensions....................................................................... 12

Ordering Guide .......................................................................... 13

Rev. A | Page 2 of 16

ADP3335

SPECIFICATIONS

All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods. Ambient
temperature of 85°C corresponds to a junction temperature of 125°C under pulsed full-load test conditions. Application stable with no
load. V

Table 1.

Parameter Symbol Conditions Min Typ Max Unit

OUTPUT

I
T
V
I
T
V
I
T

I
T

T

I
I
I
I

I
f = 10 Hz to 100 kHz, CL = 10 µF 95 µV rms
I
GROUND CURRENT

I
I
I

I

SHUTDOWN

OFF 0.4 V

1

VIN = 2.6 V to 12 V for models with V

= 6.0 V, C = C = 1.0 µF, T = –40°C to +85°C, unless otherwise noted.

IN IN OUT A

Voltage Accuracy

Line Regulation1 V

1

V

VIN = V

OUT

+ 0.4 V to 12 V –0.9 +0.9 %

OUT(NOM)

= 0.1 mA to 500 mA

L

= 25°C

A

= V

IN

= 0.1 mA to 500 mA

L

= 85°C

A

= V

IN

= 0.1 mA to 500 mA

L

= 150°C

J

= V

IN

= 0.1 mA

L

= 25°C

A

+ 0.4 V to 12 V –1.8 +1.8 %

OUT(NOM)

+ 0.4 V to 12 V –2.3 +2.3 %

OUT(NOM)

+ 0.4 V to 12 V 0.04 mV/V

OUT(NOM)

Load Regulation IL = 0.1 mA to 500 mA 0.04 mV/mA

= 25°C

A

Dropout Voltage V

Peak Load Current I

Output Noise V

In Regulation I

In Dropout I

In Shutdown

Threshold Voltage

SD

Input Current

Output Current in Shutdown

≤ 2.2 V.

OUT(NOM)

V

DROP

VIN = V

LDPK

f = 10 Hz to 100 kHz, CL = 10 µF 47 µV rms

NOISE

IL = 500 mA 4.5 10 mA

GND

VIN = V

GND

I

GNDSD

V

THSD

I

SD

I

OSD

= 98% of V

OUT

= 500 mA 200 370 mV

L

= 300 mA 140 230 mV

L

= 50 mA 30 110 mV

L

= 0.1 mA 10 40 mV

L

+ 1 V 800 mA

OUT(NOM)

= 500 mA, CNR = 10 nF

L

= 500 mA, CNR = 0 nF

L

= 300 mA 2.6 6 mA

L

= 50 mA 0.5 2.5 mA

L

= 0.1 mA 80 110 µA

L

– 100 mV 120 400 µA

OUT(NOM)

= 0.1 mA

L

SD

= 0 V, VIN = 12 V

OUT(NOM)

0.01 1 µA

ON 2.0 V

0 ≤ SD ≤ 5 V
VIN = 12 V, V

= 0 V 0.01 5 µA

OUT

1.2 3 µA

Rev. A | Page 3 of 16

ADP3335

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Input Supply Voltage –0.3 V to +16 V
Shutdown Input Voltage –0.3 V to +16 V
Power Dissipation Internally Limited
Operating Ambient Temperature Range –40°C to +85°C
Operating Junction Temperature Range –40°C to +150°C
θJA, 2-layer MSOP-8 220°C/W
θJA, 4-layer MSOP-8 158°C/W
θJA, 2-layer LFCSP-8 62°C/W
θJA, 4-layer LFCSP-8 48°C/W
Storage Temperature Range –65°C to +150°C
Lead Temperature Range (Soldering 10 sec) 300°C
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Rev. A | Page 4 of 16

ADP3335

PIN CONFIGURATIONS AND FUNCTIONAL DESCRIPTIONS

1

OUT

ADP3335

OUT

2

OUT

GND

TOP VIEW

3

(Not to Scale)

4

Figure 3. 8-Lead MSOP

8

IN
IN

7

SD

6

NR

5

00147-0-022

1

OUT

ADP3335

OUT

2

OUT

GND

TOP VIEW

3

(Not to Scale)

4

Figure 4. 8-Lead LFCSP

8

IN
IN

7

SD

6

NR

5

00147-0-025

Table 3. Pin Function Descriptions

Pin No. Mnemonic Function

1, 2, 3 OUT

Output of the Regulator. Bypass to ground with a 1.0 µF or larger capacitor. All pins must be connected together

for proper operation.
4 GND Ground Pin.
5 NR

Noise Reduction Pin. Used for further reduction of output noise (see the Noise Reduction section for further

details).
6

SD

Active Low Shutdown Pin. Connect to ground to disable the regulator output. When shutdown is not used, this

pin should be connected to the input pin.
7, 8 IN Regulator Input. All pins must be connected together for proper operation.

Rev. A | Page 5 of 16

ADP3335

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, unless otherwise noted

2.202

2.201

2.200

I

= 0

L

V

= 2.2V

OUT

5.0

4.0

2.199
150mA

2.198

2.197

OUTPUT VOLTAGE (V)

2.196

300mA

2.195

2.194

500mA

24681012

INPUT VOLTAGE (V)

Figure 5. Line Regulation Output Voltage vs. Supply Voltage

2.201

2.200

2.199

2.198

2.197

2.196

OUTPUT VOLTAGE (V)

2.195

2.194

2.193
0 100 200 300 400 500

LOAD CURRENT (mA)

V

= 2.2V

OUT

V

= 6V

IN

Figure 6. Output Voltage vs. Load Current

140

120

100

80

60

40

GROUND CURRENT (µA)

20

0

0

IL = 100µA

IL = 0

24681012

INPUT VOLTAGE (V)

V

= 2.2V

OUT

Figure 7. Ground Current vs. Supply Voltage

00147-0-003

00147-0-004

00147-0-005

3.0

2.0

GROUND CURRENT (µA)

1.0

0

0 100 200 300 400 500

LOAD CURRENT (mA)

Figure 8. Ground Current vs. Load Current

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

OUTPUT CHANGE (%)

0

–0.1

500mA

–0.2
–0.3

–0.4

–15 5 25

–40 45 65 85 105 125

JUNCTION TEMPERATURE (°

300mA

0

500mA

C)

Figure 9. Output Voltage Variation vs. Junction Temperature

8

IL = 500mA

7

6

5

300mA

4

3

GROUND CURRENT (mA)

2

100mA

50mA

1

0

0

–40 45 65 85 105 125

–15 5 25

JUNCTION TEMPERATURE (

°C)

Figure 10. Ground Current vs. Junction Temperature

00147-0-006

00147-0-007

00147-0-008

Rev. A | Page 6 of 16

ADP3335

250

200

150

100

DROPOUT VOLTAGE (mV)

50

0

0 400 500

Figure 11. Dropout Voltage vs. Output Current

3.0

2.5

2.0

1.5

1.0

0.5

INPUT/OUTPUT VOLTAGE (V)

0

100 200 300

OUTPUT (

mA)

123

TIME (

sec)

Figure 12. Power-Up/Power-Down

V

OUT

SD = V
RL= 4.4

4

= 2.2V

IN

Ω

00147-0-009

00147-0-010

2.210

2.200

(V)

2.190

OUT

V

(V)

IN

V

2.189

2.179

3.500

3.000

8040

TIME (µs)

V

= 2.2V

OUT

= 4.4

R

L

CL= 1µF

Ω

180140

00147-0-012

Figure 14. Line Transient Response

2.210

2.200

(V)

2.190

OUT

V

(V)

IN

V

2.189

2.179

3.500

3.000

8040

TIME (µs)

V

= 2.2V

OUT

= 4.4

R

L

CL= 10µF

180140

Ω

00147-0-013

Figure 15. Line Transient Response

(V)

OUT

V

(V)
V

3

C

= 1µF

OUT

2

1

0

4

2

IN

0

C

OUT

400200

= 10µF

TIME (µs)

V

= 2.2V

OUT

SD = V
RL= 4.4Ω

800600

IN

00147-0-011

Figure 13. Power-Up Response

2.3

2.2

(V)

OUT

2.1

V

400

200

(mA)

LOAD

I

VIN = 4V

= 2.2Ω

V

OUT

= 1µF

C

L

0

400200

TIME (µs)

800600

00147-0-014

Figure 16. Load Transient Response

Rev. A | Page 7 of 16

ADP3335

–20

V

= 2.2V

2.3

(V)

2.2

OUT

V

2.1

400

(mA)

200

LOAD

I

2.2

(V)

OUT

V

(A)

LOAD

I

VIN = 4V
R

= 4.4Ω

L

C

= 10µF

L

0

00147-0-015

200

400

TIME (µs)

800600

Figure 17. Load Transient Response

0

400200

TIME (µs)

FULL SHORT

VIN = 4V

00147-0-016

800600

3

2

1

0

800mΩ
SHORT

Figure 18. Short-Circuit Current

OUT

C

= 10µF

–30

–40

C

= 1µF

–50

–60

–70

RIPPLE REJECTION (dB)

–80

–90

10 1k 10k 100k 1M 10M

L

I

= 50µA

L

100

C

= 1µF

L

I

= 500mA

L

FREQUENCY (Hz)

I

C

= 10µF

L

I

= 50µA

L

L

= 500mA

L

Figure 20. Power Supply Ripple Rejection

160

140

120

100

80

60

RMS NOISE (µV)

40

20

0

0

IL = 500mA WITHOUT
NOISE REDUCTION

IL = 500mA WITH
NOISE REDUCTION

IL = 0mA WITH NOISE REDUCTION

10 20 30 40 50

= 0mA WITHOUT

I

L

NOISE REDUCTION

(µF)

C

L

CNR = 10nF

Figure 21. RMS Noise versus C

(10 Hz to 100 kHz)

L

00147-0-018

00147-0-019

100

10

1

0.1

DENSITY (µV/ Hz)

VOLTAGE NOISE SPECTRAL

0.01

0.001
10 1k 10k

100

C

L

C

NR

= 10µF

= 10nF

Figure 22. Output Noise Density

C

= 10µF

L

= 0nF

C

NR

= 1µF

C

L

CNR = 10nF

FREQUENCY (Hz)

C

= 1µF

L

= 0nF

C

NR

100k 1M

V

OUT

= 1mA

I

L

= 2.2V

00147-0-020

(V)

OUT

V

(V)

SD

V

VIN = 4V
V

= 2.2V

3

2

1

0

2

1

10µF

1µF

400200

TIME (µs)

R

800600

OUT
L

10µF

= 4.4Ω1µF

00147-0-017

Figure 19. Turn On/Turn Off Response

Rev. A | Page 8 of 16

ADP3335

THEORY OF OPERATION

The ADP3335 uses a single control loop for regulation and
reference functions. The output voltage is sensed by a resistive
voltage divider, R1 and R2, which is varied to provide the
available output voltage option. Feedback is taken from this
network by way of a series diode, D1, and a second resistor
divider, R3 and R4, to the input of an amplifier.

INPUT

Q1

NONINVERTING

WIDEBAND

DRIVER

ADP3335

COMPENSATION
CAPACITOR

g

m

Figure 23. Functional Block Diagram

PTAT

V

OS

R4

ATTENUATION

(V

GND

OUTPUT

BANDGAP/VOUT

D1

R3

PTAT

CURRENT

R1

)

C

LOAD

(a)

R

LOAD

R2

00147-0-023

A very high gain error amplifier is used to control this loop. The
amplifier is constructed in such a way that equilibrium
produces a large, temperature proportional input offset voltage
that is repeatable and very well controlled. The temperature
proportional offset voltage combines with the complementary
diode voltage to form a virtual band gap voltage implicit in the
network, although it never appears explicitly in the circuit.

This patented design makes it possible to control the loop with
only one amplifier. This technique also improves the noise
characteristics of the amplifier by providing more flexibility in
the trade-off of noise sources that leads to a low noise design.

The R1 and R2 divider is chosen in the same ratio as the band
gap voltage to the output voltage. Although the R1 and R2
resistor divider is loaded by the D1 diode and a second

divider—R3 and R4, the values can be chosen to produce a
temperature stable output. This unique arrangement specifically
corrects for the loading of the divider, thus avoiding the error
resulting from base current loading in conventional circuits.

The patented amplifier controls a new and unique noninverting
driver that drives the pass transistor, Q1. This special nonin­verting driver enables the frequency compensation to include
the load capacitor in a pole-splitting arrangement to achieve
reduced sensitivity to the value, type, and ESR of the load
capacitance.

Most LDOs place very strict requirements on the range of ESR
values for the output capacitor, because they are difficult to
stabilize due to the uncertainty of load capacitance and
resistance. The ESR value required to keep conventional LDOs
stable, moreover, changes depending on load and temperature.
These ESR limitations make designing with LDOs more
difficult because of their unclear specifications and extreme
variations over temperature.

With the ADP3335, ESR limitations are no longer a source of
design constraints. The ADP3335 can be used with virtually any
good quality capacitor and with no constraint on the minimum
ESR. This innovative design allows the circuit to be stable with
just a small 1 µF capacitor on the output. Additional advantages
of the pole-splitting scheme include superior line noise reject­tion and very high regulator gain, which lead to excellent line
and load regulation. Impressive ±1.8% accuracy is guaranteed
over line, load, and temperature.

Additional features of the circuit include current limit, thermal
shutdown, and noise reduction.

Rev. A | Page 9 of 16

ADP3335

(

)

(

)

T

+−=

APPLICATION INFORMATION

OUTPUT CAPACITOR SELECTION

As with any micropower device, output transient response is a
function of the output capacitance. The ADP3335 is stable over
a wide range of capacitor values, types, and ESR (anyCAP). A
capacitor as low as 1 µF is all that is needed for stability; larger
capacitors can be used if high output current surges are
anticipated. The ADP3335 is stable with extremely low ESR
capacitors (ESR ≈ 0), such as multilayer ceramic capacitors
(MLCC) or organic semiconductor electrolytic capacitors
(OSCON). Note that the effective capacitance of some capacitor
types may fall below the minimum at extreme temperatures.
Ensure that the capacitor provides more than 1 µF over the
entire temperature range.

INPUT BYPASS CAPACITOR

An input bypass capacitor is not strictly required, but is advi­sable in any application involving long input wires or high
source impedance. Connecting a 1 µF capacitor from IN to
ground reduces the circuit’s sensitivity to PC board layout. If a
larger value output capacitor is used, then a larger value input
capacitor is also recommended.

NOISE REDUCTION

A noise reduction capacitor (CNR) can be used, as shown in
Figure 24, to further reduce the noise by 6 dB to 10 dB
(Figure 22). Low leakage capacitors in the 100 pF to 1 nF range
provide the best performance. Since the noise reduction pin,
NR, is internally connected to a high impedance node, any con­nection to this node should be made carefully to avoid noise
pickup from external sources. The pad connected to this pin
should be as small as possible, and long PC board traces are not
recommended.

When adding a noise reduction capacitor, maintain a minimum
load current of 1 mA when not in shutdown.

THERMAL OVERLOAD PROTECTION

The ADP3335 is protected against damage from excessive
power dissipation by its thermal overload protection circuit,
which limits the die temperature to a maximum of 165°C.
Under extreme conditions (i.e., high ambient temperature and
power dissipation) where die temperature starts to rise above
165°C, the output current is reduced until the die temperature
has dropped to a safe level. The output current is restored when
the die temperature is reduced.

Current and thermal limit protections are intended to protect
the device against accidental overload conditions. For normal
operation, device power dissipation should be externally limited
so that junction temperatures will not exceed 150°C.

CALCULATING JUNCTION TEMPERATURE

Device power dissipation is calculated as follows:

IVIVVP

IN

GND

= 4 mA, VIN = 5.0 V, and V

is 48°C/W. In

JA

OUT

=

Where I

V

and V

IN

LOAD

Assuming I

IND

and I

are input and output voltages, respectively.

OUT

= 400 mA, I

LOAD

LOAD

OU

are load current and ground current, and

GND

GND

3.3 V, device power dissipation is

= (5 V – 3.3 V)400 mA + 5.0 V(4 mA) = 700 mW

P

D

The junction temperature can be calculated from the power
dissipation, ambient temperature, and package thermal
resistance. The thermal resistance is a function not only of the
package, but also of the circuit board layout. Standard test
conditions are used to determine the values published in this
data sheet, but actual performance will vary. For an LFCSP-8
package mounted on a standard 4-layer board, θ
the above example, where the power dissipation is 700 mW, the
temperature rise above ambient will be approximately equal to

= 0.700 W × 48°C/W = 33.6°C

∆T

It is important to note that as C
will be delayed. With NR values greater than 1 nF, this delay
may be on the order of several milliseconds.

ADP3335

7

IN

V

IN

1µF

8

IN

+

C

IN

Figure 24. Typical Application Circuit

OFF

SD

ON

increases, the turn-on time

NR

C

NR

5

NR

3

OUT

2

OUT

1

OUT
GND

4

6

+

C
1µF

V

OUT

OUT

00147-0-021

Rev. A | Page 10 of 16

To limit the maximum junction temperature to 150°C, the
maximum allowable ambient temperature will be

In this case, the resulting ambient temperature limitation is
above the maximum allowable ambient temperature of 85°C.

JA

= 150°C − 33.6°C = 116.4°C

T

AMAX

ADP3335

PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS

All surface-mount packages rely on the traces of the PC board
to conduct heat away from the package. Use the following
general guidelines when designing printed circuit boards to
improve both electrical and thermal performance.

1. Keep the output capacitor as close as possible to the output

and ground pins.

2. Keep the input capacitor as close as possible to the input

and ground pins.

3. PC board traces with larger cross sectional areas will

remove more heat from the ADP3335. For optimum heat
transfer, specify thick copper and use wide traces.

4. It is not recommended to use solder mask or silkscreen on

the PCB traces adjacent to the ADP3335’s pins, since doing
so will increase the junction-to-ambient thermal resistance
of the package.

5. Use additional copper layers or planes to reduce the

thermal resistance. When connecting to other layers, use
multiple vias, if possible.

LFCSP LAYOUT CONSIDERATIONS

The LFCSP package has an exposed die paddle on the bottom,
which efficiently conducts heat to the PCB. In order to achieve
the optimum performance from the LFCSP package, special
consideration must be given to the layout of the PCB. Use the
following layout guidelines for the LFCSP package.

2× VIAS, 0.250∅

35µm PLATING

0.73

0.30

1.80

0.90

2.36

0.50

1.40

1.90

3.36

Figure 25. 3 mm × 3 mm LFCSP Pad Pattern

(Dimensions shown in millimeters)

1. The pad pattern is given in Figure 25. The pad dimension

should be followed closely for reliable solder joints, while
maintaining reasonable clearances to prevent solder
bridging.

00147-0-024

2. The thermal pad of the LFCSP package provides a low

thermal impedance path (approximately 20°C/W) to the
PCB. Therefore, the PCB must be properly designed to
effectively conduct heat away from the package. This is
achieved by adding thermal vias to the PCB, which provide
a thermal path to the inner or bottom layers. See Figure 25
for the recommended via pattern. Note that the via
diameter is small to prevent the solder from flowing
through the via and leaving voids in the thermal pad solder
joint.

Also, note that the thermal pad is attached to the die
substrate, so the thermal planes to which the thermal vias
connect must be electrically isolated or tied to V

IN

. Do

NOT connect the thermal pad to ground.

3. The solder mask opening should be about 120 µ (4.7 mils)

larger than the pad size, resulting in a minimum 60 µm
(2.4 mils) clearance between the pad and the solder mask.

4. The paste mask opening is typically designed to match the

pad size used on the peripheral pads of the LFCSP package.
This should provide a reliable solder joint as long as the
stencil thickness is about 0.125 mm. The paste mask for the
thermal pad needs to be designed for the maximum
coverage to effectively remove the heat from the package.
However, due to the presence of thermal vias and the size
of the thermal pad, eliminating voids may not be possible.

5. The recommended paste mask stencil thickness is

0.125 mm. A laser cut stainless steel stencil with
trapezoidal walls should be used. A “No Clean” Type 3
solder paste should be used for mounting the LFCSP
package. Also, a nitrogen purge during the reflow process is
recommended.

6. The package manufacturer recommends that the reflow

temperature should not exceed 220°C and the time above
liquidus is less than 75 seconds. The preheat ramp should
be 3°C/second or lower. The actual temperature profile
depends on the board density and must be determined by
the assembly house as to what works best.

SHUTDOWN MODE

Applying a TTL high signal to the shutdown (SD) pin or tying it

SD

to the input pin, turns the output ON. Pulling
or below, or tying it to ground, turns the output OFF. In shut­down mode, quiescent current is reduced to a typical value of
10 nA.

down to 0.4 V

Rev. A | Page 11 of 16

ADP3335

OUTLINE DIMENSIONS

PIN 1

INDICATOR

0.90

0.85

0.80

SEATING

PLANE

12° MAX

3.00

BSC SQ

TOP

VIEW

0.30

0.23

0.18

0.80 MAX

0.65TYP

2.75

BSC SQ

0.20 REF

0.05 MAX

0.02 NOM

0.45

0.50
BSC

0.60 MAX

0.25
MIN

8

BOTTOM

5

VIEW

Figure 26. 8-Lead Frame Chip Scale Package [LFCSP]

(CP-8)

Dimensions shown in millimeters

3.00
BSC

0.50

0.40

0.30

4

1

1.60

1.45

1.30

1.50
REF

PIN 1
INDICATOR

1.90

1.75

1.60

85

3.00
BSC

PIN 1

0.65 BSC

0.15

0.00

0.38

0.22

COPLANARITY

0.10
COMPLIANT TO JEDEC STANDARDS MO-187AA

4.90
BSC

4

SEATING
PLANE

1.10 MAX

0.23

0.08

8°
0°

Figure 27. 8-Lead Mini Small Outline Package [MSOP]

(RM-8)

Dimensions shown in millimeters

0.80

0.60

0.40

Rev. A | Page 12 of 16

ADP3335

ORDERING GUIDE

Model Output Voltage

ADP3335ARM-1.8–RL 1.8 V RM-8 (MSOP-8) LFA
ADP3335ARM-1.8–RL7 1.8 V RM-8 (MSOP-8) LFA
ADP3335ARM-2.5–RL 2.5 V RM-8 (MSOP-8) LFC
ADP3335ARM-2.5–RL7 2.5 V RM-8 (MSOP-8) LFC
ADP3335ARMZ-2.5–RL7
ADP3335ARM-2.85–RL 2.85 V RM-8 (MSOP-8) LFD
ADP3335ARM-2.85–R7 2.85 V RM-8 (MSOP-8) LFD
ADP3335ARMZ-2.85–R72 2.85 V RM-8 (MSOP-8) LFD3
ADP3335ARM-3.3–RL 3.3 V RM-8 (MSOP-8) LFE
ADP3335ARMZ-3.3–RL2 3.3 V RM-8 (MSOP-8) LFE3
ADP3335ARM-3.3–RL7 3.3 V RM-8 (MSOP-8) LFE
ADP3335ARM-5–REEL 5 V RM-8 (MSOP-8) LFF
ADP3335ARM-5–REEL7 5 V RM-8 (MSOP-8) LFF
ADP3335ACP-1.8–RL 1.8 V CP-8 (LFCSP-8) LFA
ADP3335ACP-1.8–RL7 1.8 V CP-8 (LFCSP-8) LFA
ADP3335ACP-2.5–RL 2.5 V CP-8 (LFCSP-8) LFC
ADP3335ACP-2.5–RL7 2.5 V CP-8 (LFCSP-8) LFC
ADP3335ACP-2.85–R7 2.85 V CP-8 (LFCSP-8) LFD
ADP3335ACP-3.3–RL 3.3 V CP-8 (LFCSP-8) LFE
ADP3335ACP-3.3–RL7 3.3 V CP-8 (LFCSP-8) LFE
ADP3335ACP-5–REEL 5 V CP-8 (LFCSP-8) LFF
ADP3335ACP-5–REEL7 5 V CP-8 (LFCSP-8) LFF

1

Contact the factory for other output voltage options.

2

Z = Pb-free part.

3

Pb-free devices have a "#" marked on the device.

2

2.5 V RM-8 (MSOP-8) LFC

1

Package Option Branding Information

3

Rev. A | Page 13 of 16

ADP3335

NOTES

Rev. A | Page 14 of 16

ADP3335

NOTES

Rev. A | Page 15 of 16

ADP3335

NOTES

© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners

C00147-0-1/04(A)

Rev. A | Page 16 of 16