Analog Devices ADP3330ART-2.5, ADP3330ART-2.75, ADP3330ART-2.85, ADP3330ART-3, ADP3330ART-3.3 Schematic [ru]

High Accuracy Ultralow IQ,

a

FEATURES
High Accuracy Over Line and Load: 60.7% @ +258C,

61.4% Over Temperature
Ultralow Dropout Voltage: 140 mV (Typ) @ 200 mA
Requires Only C
anyCAP = Stable with Any Type of Capacitor

(Including MLCC)
Current and Thermal Limiting
Low Noise
Low Shutdown Current: <2 mA

2.9 V to 12 V Supply Range
–408C to +858C Ambient Temperature Range
Ultrasmall Thermally Enhanced Chip-on-Lead™

SOT-23-6 6-Lead Package

APPLICATIONS
Cellular Telephones
Notebook, Palmtop Computers
Battery Powered Systems
PCMCIA Regulator
Bar Code Scanners
Camcorders, Cameras

= 0.47 mF for Stability

O

ERR

SD

200 mA, SOT-23, anyCAP

™

Low Dropout Regulator

ADP3330

FUNCTIONAL BLOCK DIAGRAM

IN

THERMAL

PROTECTION

Q1

DRIVER

GND

CC

ADP3330

g

m

BANDGAP

REF

OUT

R1

R2

GENERAL DESCRIPTION

The ADP3330 is a member of the ADP330x family of precision
low dropout anyCAP voltage regulators. The ADP3330 operates
with an input voltage range of 2.9 V to 12 V and delivers a load
current up to 200 mA. The ADP3330 stands out from the con­ventional LDOs with a novel architecture and an enhanced
process that enables it to offer performance advantages and
higher output current than its competition. Its patented design

requires only a 0.47 µF output capacitor for stability. This

device is insensitive to output capacitor Equivalent Series
Resistance (ESR), and is stable with any good quality capaci­tor, including ceramic (MLCC) types for space-restricted
applications. The ADP3330 achieves exceptional accuracy of

±0.7% at room temperature and ±1.4% over temperature, line

and load variations. The dropout voltage of the ADP3330 is
only 140 mV (typical) at 200 mA. This device also includes a
safety current limit, thermal overload protection and a shutdown
feature. In shutdown mode, the ground current is reduced to

less than 2 µA. The ADP3330 has ultralow quiescent current
34 µA (typ) in light load situations.

anyCAP and Chip-on-Lead are trademarks of Analog Devices, Inc.

The SOT-23-6 package has been thermally enhanced using
Analog Devices’ proprietary Chip-on-Lead feature to maximize
power dissipation.

NR

ERR

ADP3330

V

IN

0.47mF

+

C

IN

–

OUT

IN

SD

GND

ON

OFF

V

OUT

+

C

OUT

–

0.47mF

Figure 1. Typical Application Circuit

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1999

ADP3330-xx–SPECIFICATIONS

unless otherwise noted).

1, 2

The following specifications apply to all voltage options except –2.5.

(@ TA = –408C to +858C, VIN = +7 V, CIN = 0.47 mF, C

= 0.47 mF,

OUT

Parameter Symbol Conditions Min Typ Max Units

OUTPUT VOLTAGE ACCURACY V

LINE REGULATION V

LOAD REGULATION I

GROUND CURRENT I

GROUND CURRENT IN DROPOUT I

DROPOUT VOLTAGE V

∆V

∆

OUT

∆V

V

∆

I

GND

GND

DROP

IN

O

L

O

VIN = V

= 0.1 mA to 200 mA

I

L

T

= +25°C –0.7 +0.7 %

A

= V

V

IN

= 0.1 mA to 150 mA

I

L

T

= –40°C to +85°C –1.4 +1.4 %

A

= V

V

IN

= 0.1 mA to 200 mA

I

L

T

= –20°C to +85°C –1.4 +1.4 %

A

= V

IN

T

= +25°C 0.04 mV/V

A

= 0.1 mA to 200 mA

L

T

= +25°C 0.04 mV/mA

A

IL = 200 mA, T

= 150 mA 1.2 3.1 mA

I

L

= 50 mA 0.4 1.1 mA

I

L

I

= 0.1 mA 34 50 µA

L

VIN = V
I

= 0.1 mA 37 55 µA

L

V

= 98% of V

OUT

IL = 200 mA, T

= 150 mA 0.11 0.17 V

I

L

= 10 mA 0.042 0.06 V

I

L

+0.25 V to +12 V

OUTNOM

OUTNOM

OUTNOM

OUTNOM

OUTNOM

+0.25 V to +12 V

+0.25 V to +12 V

+0.25 V to +12 V

= –20°C to +85°C 1.6 4.0 mA

A

– 100 mV

OUTNOM

= –20°C to +85°C 0.14 0.23 V

A

IL = 1 mA 0.025 0.052V

PEAK LOAD CURRENT I

OUTPUT NOISE

3

SHUTDOWN THRESHOLD V

LDPK

V

NOISE

THSD

VIN = V

f = 10 Hz–100 kHz, C
I

= 200 mA, CNR = 10 nF, V

L

f = 10 Hz–100 kHz, C
IL = 200 mA, CNR = 0 nF, V

+ 1 V 300 mA

OUTNOM

= 10 µF

L

= 10 µF

L

= 3 V 47 µV rms

OUT

= 3 V 95 µ V rms

OUT

ON 2.0 V
OFF 0.4 V

SHUTDOWN PIN INPUT CURRENT I

SD

V

= 12 V, 0 < SD, ≤ 12 V 1.9 9 µA

IN

0 < SD, ≤ 5 V 1.4 6 µA

GROUND CURRENT IN SHUTDOWN

MODE I

OUTPUT CURRENT IN SHUTDOWN I

GNDSD

OSD

MODE T

ERROR PIN OUTPUT LEAKAGE I

EL

SD = 0 V, V

T

= +25°C @ VIN = 12 V 1 µA

A

= +85°C @ VIN = 12 V 2 µA

A

V

= 5 V 1 µA

EO

= 12 V 0.01 2 µA

IN

ERROR PIN OUTPUT “LOW”

VOLTAGE V

NOTES

1

Ambient temperature of +85°C corresponds to a junction temperature of +125 °C under typical full load test conditions.

2

Application stable with no load.

3

See detail in Figure 19 and Application section of data sheet.

Specifications subject to change without notice.

EOL

I

= 400 µA 0.19 0.40 V

SINK

–2–

REV. A

ADP3330

ADP3330-2.5–SPECIFICATIONS

unless otherwise noted).

1, 2

(@ TA = –408C to +858C, VIN = +7 V ,CIN = 0.47 mF, C

= 0.47 mF,

OUT

Parameter Symbol Conditions Min Typ Max Units

OUTPUT VOLTAGE ACCURACY V

LINE REGULATION V

LOAD REGULATION I

GROUND CURRENT I

GROUND CURRENT IN DROPOUT I

DROPOUT VOLTAGE V

∆V
∆

OUT

∆V

V

∆

I

GND

GND

DROP

O

IN

O

L

VIN = +2.9 V to +12 V

= 0.1 mA to 200 mA

I

L

= +25°C –0.7 +0.7 %

T

A

V

= +2.9 V to +12 V

IN

= 0.1 mA to 150 mA

I

L

= –40°C to +85°C –1.4 +1.4 %

T

A

V

= +2.9 V to +12 V

IN

= 0.1 mA to 200 mA

I

L

T

= –20°C to +85°C –1.4 +1.4 %

A

= +2.9 V to +12 V

IN

T

= +25°C 0.04 mV/V

A

= 0.1 mA to 200 mA

L

T

= +25°C 0.04 mV/mA

A

IL = 200 mA, T

= 150 mA 1.2 3.1 mA

I

L

I

= 50 mA 0.4 1.1 mA

L

I

= 0.1 mA 34 50 µA

L

VIN = V

OUTNOM

I

= 0.1 mA 37 55 µA

L

V

= 98% of V

OUT

IL = 200 mA, T
I

= 150 mA 0.11 0.3 V

L

= 10 mA 0.042 0.06 V

I

L

= –20°C to +85°C 1.6 4.0 mA

A

– 100 mV

OUTNOM

= –20°C to +85°C 0.14 0.4 V

A

IL = 1 mA 0.025 0.052V

PEAK LOAD CURRENT I

OUTPUT NOISE

3

SHUTDOWN THRESHOLD V

LDPK

V

NOISE

THSD

VIN = V

f = 10 Hz–100 kHz, C

= 200 mA, CNR = 10 nF, V

I

L

f = 10 Hz–100 kHz, C
IL = 200 mA, CNR = 0 nF, V

+ 1 V 300 mA

OUTNOM

= 10 µF

L

= 10 µF

L

= 3 V 47 µV rms

OUT

= 3 V 95 µ V rms

OUT

ON 2.0 V
OFF 0.4 V

SHUTDOWN PIN INPUT CURRENT I

SD

V

= 12 V, 0 < SD, ≤ 12 V 1.9 9 µA

IN

0 < SD, ≤ 5 V 1.4 6 µA

GROUND CURRENT IN SHUTDOWN

MODE I

OUTPUT CURRENT IN SHUTDOWN I

GNDSD

OSD

MODE T

ERROR PIN OUTPUT LEAKAGE I

EL

SD = 0 V, V

T

= +25°C @ VIN = 12 V 1 µA

A

= +85°C @ VIN = 12 V 2 µA

A

V

= 5 V 1 µA

EO

= 12 V 0.01 2 µA

IN

ERROR PIN OUTPUT “LOW”

VOLTAGE V

NOTES

1

Ambient temperature of +85°C corresponds to a junction temperature of +125 °C under typical full load test conditions.

2

Application stable with no load.

3

See detail in Figure 19 and Application section of data sheet.

Specifications subject to change without notice.

EOL

I

= 400 µA 0.19 0.40 V

SINK

–3–REV. A

ADP3330

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

Input Supply Voltage . . . . . . . . . . . . . . . . . . . . –0.3 V to +16 V

Shutdown Input Voltage . . . . . . . . . . . . . . . . . –0.3 V to +16 V

Power Dissipation . . . . . . . . . . . . . . . . . . . . Internally Limited

Operating Ambient Temperature Range . . . . . –40°C to +85°C

Operating Junction Temperature Range . . . . –40°C to +125°C

θ

(4-Layer Board) . . . . . . . . . . . . . . . . . . . . . . . +165°C/W

JA

θ

(2-Layer Board) . . . . . . . . . . . . . . . . . . . . . . . +190°C/W

JA

Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300°C

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

*This is a stress rating only; operation beyond these limits can cause the device to

be permanently damaged.

ORDERING GUIDE

Voltage Package Marking

Model Output Option* Code

ADP3330ART-2.5 2.5 V RT-6 (SOT-23-6) L1B
ADP3330ART-2.75 2.75 V RT-6 (SOT-23-6) L2B
ADP3330ART-2.85 2.85 V RT-6 (SOT-23-6) L3B
ADP3330ART-3 3.0 V RT-6 (SOT-23-6) L4B
ADP3330ART-3.3 3.3 V RT-6 (SOT-23-6) L5B
ADP3330ART-3.6 3.6 V RT-6 (SOT-23-6) L6B
ADP3330ART-5 5.0 V RT-6 (SOT-23-6) L8B

*Contact the factory for the availability of other output voltage options.

PIN FUNCTION DESCRIPTIONS

Pin Name Function

1 OUT Output of the Regulator. Bypass to ground

with a 0.47 µF or larger capacitor.

2 IN Regulator Input.
3 ERR Open Collector Output that goes low to

indicate that the output is about to go out

of regulation.
4 GND Ground Pin.
5 NR Noise Reduction Pin. Used for further

reduction of output noise (see text for

detail). No connection if not used.
6 SD Active Low Shutdown Pin. Connect to

ground to disable the regulator output.

When shutdown is not used, this pin

should be connected to the input pin.

PIN CONFIGURATION

OUT

ERR

1

2

IN

3

ADP3330

TOP VIEW

(Not to Scale)

6

SD

5

NR

4

GND

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADP3330 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

–4–

REV. A