Datasheet ADP323 Datasheet (ANALOG DEVICES)

Triple, 200 mA, Low Noise,

O

Data Sheet

FEATURES

Fixed (ADP322) and adjustable output (ADP323) options Bias voltage range (VBIAS): 2.5 V to 5.5 V LDO input voltage range (VIN1/VIN2, VIN3): 1.8 V to 5.5 V Three 200 mA low dropout voltage regulators (LDOs) 16-lead, 3 mm × 3 mm LFCSP Initial accuracy: ±1% Stable with 1 μF ceramic output capacitors No noise bypass capacitor required 3 independent logic controlled enables Overcurrent and thermal protection Key specifications

High PSRR

76 dB PSRR up to 1 kHz 70 dB PSRR at 10 kHz 60 dB PSRR at 100 kHz 40 dB PSRR at 1 MHz

Low output noise

29 μV rms typical output noise at V

55 μV rms typical output noise at V Excellent transient response Low dropout voltage: 110 mV at 200 mA load 85 μA typical ground current at no load, all LDOs enabled 100 μs fast turn-on circuit Guaranteed 200 mA output current per regulator

−40°C to +125°C junction temperature

APPLICATIONS

Mobile phones Digital cameras and audio devices Portable and battery-powered equipment Portable medical devices Post dc-to-dc regulation

= 1.2 V

OUT

= 2.8 V

OUT

High PSRR Voltage Regulator

ADP322/ADP323

TYPICAL APPLICATION CIRCUITS

VBIAS

LDO 1

EN LD1

VBIAS

LDO 2

EN LD2

VBIAS

LDO 3

EN LD3

GND

VBIAS

LDO 1

EN LD1

VBIAS

LDO 2

EN LD2

VBIAS

LDO 3

EN LD3

GND

FB1

FB2

FB3

VOUT1

+

1µF

VOUT2

+

1µF

VOUT3

+

1µF

VOUT1

+

1µF

VOUT2

+

1µF

VOUT3

+

1µF

2.5V T

1.8V T

2.5V TO

5.5V

1.8V TO

5.5V

1.8V TO

5.5V

OFF

ADP322

ON

5.5V

VBIAS

VIN1/VIN2

VIN3

+

1µF

+

1µF

EN1

EN2

+

1µF

EN3

Figure 1. Typical Application Circuit for ADP322

VBIAS

VIN1/VIN2

VIN3

+

1µF

+

1µF

EN1

EN2

+

1µF

EN3

ADP323

ON

OFF

ON

OFF

ON

OFF

Figure 2. Typical Application Circuit for ADP323

09288-001

09288-053

GENERAL DESCRIPTION

The ADP322/ADP323 200 mA triple output LDOs combine high PSRR, low noise, low quiescent current, and low dropout voltage to extend the battery life of portable devices and are ideally suited for wireless applications with demanding performance and board space requirements.

The ADP322/ADP323 PSRR is greater than 60 dB for frequencies as high as 100 kHz while operating with a low headroom voltage. The ADP322/ADP323 offer much lower noise performance than competing LDOs without the need for a noise bypass capacitor.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

The ADP322/ADP323 are available in a miniature 16-lead, 3 mm × 3 mm LFCSP package and are stable with tiny 1 µF ±30% ceramic output capacitors providing the smallest possible board area for a wide variety of portable power needs.

The ADP322 is available in output voltage combinations ranging from 0.8 V to 3.3 V and offers overcurrent and thermal protection to prevent damage in adverse conditions. The APDP323 adjustable triple LDO can be configured for any output voltage between 0.5 V and 5 V with two resistors for each output.

ADP322/ADP323 Data Sheet

REVISION HISTORY

9/11—Rev.0 to Rev. A

Added Figure 2, Renumbered Sequentially .................................. 1

Changes to Theory of Operation Section.................................... 15

Added Figure 45, Renumbered Sequentially .............................. 15

Changes to Ordering Guide.......................................................... 21

Theory of Operation ...................................................................... 15

Applications Information.............................................................. 16

Capacitor Selection .................................................................... 16

Undervoltage Lockout............................................................... 17

Enable Feature ............................................................................ 17

Current-Limit and Thermal Overload Protection................. 18

Thermal Considerations............................................................ 18

Printed Circuit Board Layout Considerations ....................... 20

Outline Dimensions....................................................................... 21

Ordering Guide .......................................................................... 21

9/10—Revision 0: Initial Version

Rev. A | Page 2 of 24

Data Sheet ADP322/ADP323

SPECIFICATIONS

V C

Table 1.

Parameter Symbol Conditions Min Typ Max Unit

VOLTAGE RANGE

CURRENT

I I I I I

T

EN1 = EN2 = EN3 = GND, TJ = −40°C to +125°C 2.5 μA FEEDBACK INPUT CURRENT FBIN 0.01 μA VOLTAGE ACCURACY

LINE REGULATION ∆V V LOAD REGULATION2 ∆V I DROPOUT VOLTAGE3 V

I I I START-UP TIME4 T V

V CURRENT LIMIT THRESHOLD5 I THERMAL SHUTDOWN

= V

IN1/VIN2

= C

IN

OUT1

IN3

= C

= (V

OUT2

Input Bias Voltage Range V Input LDO Voltage Range V

Ground Current with All

+ 0.5 V) or 1.8 V (whichever is greater), V

OUT

= C

= 1 µF, and TA = 25°C, unless otherwise noted.

OUT3

T

BIAS

IN1/VIN2/VIN3

I

GND

= −40°C to +125°C 2.5 5.5 V

J

TJ = −40°C to +125°C 1.8 5.5 V

OUT

BIAS

= 0 μA 85 μA

Regulators On

= 0 μA, TJ = −40°C to +125°C 160 μA

OUT

= 10 mA 120 μA

OUT

= 10 mA, TJ = −40°C to +125°C 220 μA

OUT

= 200 mA 250 μA

OUT

= 200 mA, TJ = −40°C to +125°C 380 μA

OUT

Bias Voltage Input Current I

Shutdown Current I

Output Voltage Accuracy

66 μA

BIAS

= −40°C to +125°C 140 μA

J

EN1 = EN2 = EN3 = GND 0.1 μA

GND-SD

−1 +1 %

V

OUT

(ADP322)

0.495 0.5 0.505 V

Feedback Voltage Accuracy

(ADP323)

1

V

FB

100 μA < I T

= −40°C to +125°C

J

100 μA < I

= −40°C to +125°C

T

J

/∆VIN VIN = (V

OUT

= (V

IN

/∆I

I

OUT

DROPOUT

V

START-UP

= 1 mA to 200 mA 0.001 %/mA

OUT

= 1 mA to 200 mA, TJ = −40°C to +125°C 0.005 %/mA

OUT

V

= 3.3 V mV

OUT

I

= 10 mA 6 mV

OUT

= 10 mA, TJ = −40°C to +125°C 9 mV

OUT

= 200 mA 110 mV

OUT

= 200 mA, TJ = −40°C to +125°C 170 mV

OUT

= 3.3 V, all V

OUT

= 0.8 V 100 μs

OUT

= 3.3 V, one V

V

OUT

< 200 mA, VIN = (V

OUT

< 200 mA, VIN = (V

OUT

+ 0.5 V) to 5.5 V 0.01 %/ V

OUT

+ 0.5 V) to 5.5 V, TJ = −40°C to +125°C −0.03 +0.03 %/ V

OUT

third LDO

= 0.8 V 20 μs

OUT

250 360 600 mA

LIMIT

Thermal Shutdown Threshold TSSD T Thermal Shutdown Hysteresis TS

15 °C

SD-HYS

rising 155 °C

J

= 2.5 V, EN1, EN2, EN3 = V

+ 0.5 V) to 5.5 V,

OUT

+ 0.5 V) to 5.5 V,

OUT

, I

= I

BIAS

OUT1

OUT2

= 10 mA,

OUT3

−2 +2 %

0.490 0.510 V

initially off, enable any LDO 240 μs

initially on, enable second or

OUT

160 μs

Rev. A | Page 3 of 24

ADP322/ADP323 Data Sheet

Parameter Symbol Conditions Min Typ Max Unit

EN INPUT

EN Input Logic High VIH 2.5 V ≤ V EN Input Logic Low VIL 2.5 V ≤ V EN Input Leakage Current V

EN1 = EN2 = EN3 = VIN or GND 0.1 μA

I-LEAKAGE

EN1 = EN2 = EN3 = V

= −40°C to +125°C

T

J

UNDERVOLTAGE LOCKOUT UVLO

Input Bias Voltage (VBIAS)

UVLO

2.45 V

RISE

Rising

Input Bias Voltage (VBIAS)

UVLO

2.0 V

FAL L

Falling

Hysteresis UVLO

OUTPUT NOISE OUT

180 mV

HYS

10 Hz to 100 kHz, VIN = 5 V, V

NOISE

10 Hz to 100 kHz, VIN = 5 V, V 10 Hz to 100 kHz, VIN = 3.6 V, V 10 Hz to 100 kHz, VIN = 3.6 V, V POWER SUPPLY REJECTION RATIO PSRR VIN = 1.8 V, V 100 Hz 70 dB 1 kHz 70 dB 10 kHz 70 dB 100 kHz 60 dB 1 MHz 40 dB V

= 3.8 V, V

IN

100 Hz 68 dB 1 kHz 62 dB 10 kHz 68 dB 100 kHz 60 dB 1 MHz 40 dB

1

Accuracy when VOUTx is connected directly to FBx. When the VOUTx voltage is set by external feedback resistors, the absolute accuracy in adjust mode depends on

the tolerances of the resistors used.

2

Based on an end-point calculation using 1 mA and 200 mA loads.

3

The dropout voltage specification applies only to output voltages greater than 1.8 V. Dropout voltage is defined as the input-to-output voltage differential when the

input voltage is set to the nominal output voltage.

4

Start-up time is defined as the time between the rising edge of ENx to VOUTx being at 90% of its nominal value.

5

Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V

output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, that is, 2.7 V.

≤ 5.5 V 1.2 V

BIAS

≤ 5.5 V 0.4 V

BIAS

1 μA

= 0.8 V, I

OUT

= 2.8 V, I

OUT

or GND,

IN

= 3.3 V 63 μV rms

OUT

= 2.8 V 55 μV rms

OUT

= 2.5 V 50 μV rms

OUT

= 1.2 V 29 μV rms

OUT

= 100 mA

OUT

= 100 mA

OUT

INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS

Table 2.

Parameter Symbol Conditions Min Typ Max Unit

MINIMUM INPUT AND OUTPUT CAPACITANCE1 C CAPACITOR ESR R

1

The minimum input and output capacitance should be greater than 0.70 μF over the full range of operating conditions. The full range of operating conditions in the

application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended; Y5V and Z5U capacitors are not recommended for use with LDOs.

TA = −40°C to +125°C 0.70 μF

MIN

T

ESR

Rev. A | Page 4 of 24

= −40°C to +125°C 0.001 1 Ω

A

Data Sheet ADP322/ADP323

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

VIN1/VIN2, VIN3, VBIAS to GND –0.3 V to +6.5 V VOUT1, VOUT2, FB1, FB2 to GND –0.3 V to VIN1/VIN2 VOUT3, FB3 to GND –0.3 V to VIN3 EN1, EN2, EN3 to GND –0.3 V to +6.5 V Storage Temperature Range –65°C to +150°C Operating Junction Temperature Range –40°C to +125°C Soldering Conditions JEDEC J-STD-020

Junction-to-ambient thermal resistance (θ based on modeling and calculation using a 4-layer board. The junction-to-ambient thermal resistance is highly dependent on the application and board layout. In applications where high maximum power dissipation exists, close attention to thermal board design is required. The value of θJA may vary, depending on PCB material, layout, and environmental conditions. The specified values of θ circuit board. See JEDEC JESD 51-9 for detailed information on the board construction. For additional information, see the AN-617 Application Note, MicroCSP™ Wafer Level Chip Scale

Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL DATA

Absolute maximum ratings apply individually only, not in combination.

The ADP322/ADP323 triple LDO can be damaged when the junction temperature limits are exceeded. Monitoring ambient temperature does not guarantee that the junction temperature (T

) is within the specified temperature limits. In applications

J

with high power dissipation and poor thermal resistance, the maximum ambient temperature may have to be derated. In applications with moderate power dissipation and low PCB

Package.

Ψ

is the junction to board thermal characterization parameter

JB

with units of °C/W. Ψ calculation using a 4-layer board. The JESD51-12, Guidelines for Reporting and Using Package Thermal Information, states that thermal characterization parameters are not the same as thermal resistances. Ψ multiple thermal paths rather than a single path as in thermal resistance, θ from the top of the package as well as radiation from the package, factors that make Ψ Maximum junction temperature (T temperature (T formula:

T

= TB + (PD × ΨJB)

J

See JEDEC JESD51-8 and JESD51-12 for more detailed information about Ψ

thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits.

The junction temperature (T ambient temperature (T (P

), and the junction-to-ambient thermal resistance of the

D

package (θ

). Maximum junction temperature (TJ) is calculated

JA

from the ambient temperature (T

) of the device is dependent on the

J

), the power dissipation of the device

A

) and power dissipation (PD)

A

THERMAL RESISTANCE

θJA and ΨJB are specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.

Table 4.

Package Type θJA ΨJB Unit

16-Lead, 3 mm × 3 mm LFCSP 49.5 25.2 °C/W

using the following formula:

T

= TA + (PD × θJA)

J

ESD CAUTION

are based on a 4-layer, 4 inch × 3 inch

JA

of the package is based on modeling and

JB

measures the component power flowing through

JB

. Therefore, ΨJB thermal paths include convection

JB

more useful in real-world applications.

JB

) is calculated from the board

J

) and power dissipation (PD) using the following

B

.

JB

) of the package is

JA

Rev. A | Page 5 of 24

ADP322/ADP323 Data Sheet

C

2

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

EN2

EN3

NC

16

1

EN1

2

VBIAS

VIN1/VIN2

NC

NOTES

1. NC = NO CONNE . CONNECT EXP OSED PAD TO GROUND PLANE.

3

4

ADP322

5

VOUT1

TOP VIEW

(Not to Scale)

T.

Figure 3. ADP322 Pin Configuration

Table 5. ADP322 Pin Function Descriptions

Pin No. Mnemonic Description

1 EN1

Enable Input for Regulator 1. Drive EN1 high to turn on Regulator 1; drive it low to turn off Regulator 1. For

automatic startup, connect EN1 to VBIAS. 2 VBIAS Input Voltage Bias Supply. Bypass VBIAS to GND with a 1 μF or greater capacitor. 3 VIN1/VIN2

Regulator Input Supply for Output Voltage 1 and Output Voltage 2. Bypass VIN1/VIN2 to GND with a 1 μF or

greater capacitor. 4 NC Not connected internally. 5 VOUT1 Regulated Output Voltage 1. Connect a 1 μF or greater output capacitor between VOUT1 and GND. 6 VOUT2 Regulated Output Voltage 2. Connect a 1 μF or greater output capacitor between VOUT2 and GND. 7 NC Not connected internally. 8 VOUT3 Regulated Output Voltage 3. Connect a 1 μF or greater output capacitor between VOUT3 and GND. 9 NC Not connected internally. 10 VIN3 Regulator Input Supply for Output Voltage 3. Bypass VIN3 to GND with a 1 μF or greater capacitor. 11 NC Not connected internally. 12 GND Ground Pin. 13 NC Not connected internally. 14 NC Not connected internally. 15 EN3

Enable Input for Regulator 3. Drive EN3 high to turn on Regulator 3; drive it low to turn off Regulator 3. For

automatic startup, connect EN3 to VBIAS. 16 EN2

Enable Input for Regulator 2. Drive EN3 high to turn on Regulator 2; drive it low to turn off Regulator 2. For

automatic startup, connect EN2 to VBIAS. EP Exposed pad for enhanced thermal performance. Connect to copper ground plane.

NC

13

15

14

12

GND

11

NC

10

VIN3

9NC

8

7

6

NC

VOUT2

VOUT3

09288-002

Rev. A | Page 6 of 24

Data Sheet ADP322/ADP323

C

2

EN2

EN3

NC

16

1

EN1

2

VBIAS

VIN1/VIN2

FB1

NOTES

1. NC = NO CONNE . CONNECT EXP OSED PAD TO GROUND PLANE.

3

4

ADP323

5

VOUT1

TOP VIEW

(Not to Scale)

T.

Figure 4. ADP323 Pin Configuration

Table 6. ADP323 Pin Function Descriptions

Pin No. Mnemonic Description

1 EN1

Enable Input for Regulator 1. Drive EN1 high to turn on Regulator 1; drive it low to turn off Regulator 1. For

automatic startup, connect EN1 to VBIAS. 2 VBIAS Input Voltage Bias Supply. Bypass VBIAS to GND with a 1 μF or greater capacitor. 3 VIN1/VIN2

Regulator Input Supply for Output Voltage 1 and Output Voltage 2. Bypass VIN1/VIN2 to GND with a 1 μF or

greater capacitor. 4 FB1 Connect the midpoint of the voltage divider from VOUT1 to GND to set VOUT1. 5 VOUT1 Regulated Output Voltage 1. Connect a 1 μF or greater output capacitor between VOUT1 and GND. 6 VOUT2 Regulated Output Voltage 2. Connect a 1 μF or greater output capacitor between VOUT2 and GND. 7 FB2 Connect the midpoint of the voltage divider from VOUT2 to GND to set VOUT2. 8 VOUT3 Regulated Output Voltage 3. Connect a 1 μF or greater output capacitor between VOUT3 and GND. 9 FB3 Connect the midpoint of the voltage divider from VOUT3 to GND to set VOUT3. 10 VIN3 Regulator Input Supply for Output Voltage 3. Bypass VIN3 to GND with a 1 μF or greater capacitor. 11 NC Not connected internally. 12 GND Ground Pin. 13 NC Not connected internally. 14 NC Not connected internally. 15 EN3

Enable Input for Regulator 3. Drive EN3 high to turn on Regulator 3; drive it low to turn off Regulator 3. For

automatic startup, connect EN3 to VBIAS. 16 EN2

Enable Input for Regulator 2. Drive EN3 high to turn on Regulator 2; drive it low to turn off Regulator 2. For

automatic startup, connect EN2 to VBIAS. EP Exposed pad for enhanced thermal performance. Connect to copper ground plane.

NC

13

15

14

12

GND

11

NC

10

VIN3

9FB3

8

7

6

FB2

VOUT2

VOUT3

09288-054

Rev. A | Page 7 of 24

ADP322/ADP323 Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

V enable voltage, T

IN1/VIN2

3.33

3.32

3.31

(V)

3.30

OUT

V

3.29

3.28

= V

=V

IN3

LOAD = 1mA LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA

= 4 V, V

BIAS

= 25°C, unless otherwise noted.

A

= 3.3 V, V

OUT1

= 1.8 V, V

OUT2

OUT3

= 1.5 V, I

= 10 mA, CIN = C

OUT

1.820

1.815

1.810

1.805

(V)

1.800

OUT

V

1.795

1.790

1.785

OUT1

LOAD = 1mA LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA

= C

OUT2

= C

OUT3

= 1 µF, V

ENX

is the

3.27

–40–52585125

T

(°C)

J

Figure 5. Output Voltage vs. Junction Temperature

3.320

3.315

(V)

3.310

OUT

V

3.305

3.300

1 10 100 1000

I

(mA)

LOAD

Figure 6. Output Voltage vs. Load Current

3.320

3.315

LOAD = 1mA LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA

1.780

09288-003

–40 –5 25 85 125

(°C)

T

J

09288-006

Figure 8. Output Voltage vs. Junction Temperature

1.820

1.815

(V)

1.810

OUT

V

1.805

1.800

1 10 100 1000

(mA)

I

09288-004

LOAD

09288-007

Figure 9. Output Voltage vs. Load Current

1.820

1.815

LOAD = 1mA LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA

(V)

3.310

OUT

V

3.305

3.300

3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4

(V)

V

IN

Figure 7. Output Voltage vs. Input Voltage

09288-005

Rev. A | Page 8 of 24

(V)

1.810

OUT

V

1.805

1.800

2.1 2.5 2.9 3.3 3. 7 4 .1 4.5 4.9 5.3

V

(V)

IN

Figure 10. Output Voltage vs. Input Voltage

09288-008

Data Sheet ADP322/ADP323

(V)

OUT

V

1.520

1.515

1.510

1.505

1.500

1.495

1.490

1.485

1.480

LOAD = 1mA LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA

–40 –5 25 85 125

T

(°C)

J

Figure 11. Output Voltage vs. Junction Temperature

1.510

09288-009

140

120

100

80

60

40

GROUND CURRENT (µA)

20

0

–40 –5 25 85 125

(°C)

T

J

LOAD = 1mA LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA

09288-012

Figure 14. Ground Current vs. Junction Temperature, Single Output Loaded

120

1.508

1.506

(V)

OUT

V

1.504

1.502

1.500

1 10 100 1000

I

(mA)

LOAD

Figure 12. Output Voltage vs. Load Current

1.510

1.508

1.506

(V)

OUT

V

1.504

1.502

1.500

LOAD = 1mA LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA

1.80 2.20 2.60 3.00 3. 40 3.80 4.20 4.60 5.00 5. 40

VIN (V)

Figure 13. Output Voltage vs. Input Voltage

100

80

60

40

GROUND CURRENT (µA)

20

0

1 10 100 1000

(mA)

I

09288-010

LOAD

09288-013

Figure 15. Ground Current vs. Load Current, Single Output Loaded

120

100

80

60

40

GROUND CURRENT (µA)

09288-011

LOAD = 1mA LOAD = 5mA LOAD = 10mA

20

LOAD = 50mA LOAD = 100mA LOAD = 200mA

0

1.8 2.2 2.6 3.0 3.4 3.8 4.2 4.6 5. 0 5.4

(V)

V

IN

09288-014

Figure 16. Ground Current vs. Input Voltage, Single Output Loaded

Rev. A | Page 9 of 24

ADP322/ADP323 Data Sheet

350

120

300

250

200

150

100

GROUND CURRENT (µA)

50

0

–40 –5 25 85 125

T

(°C)

J

LOAD = 1mA LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA

Figure 17. Ground Current vs. Junction Temperature,

All Outputs Loaded Equally

300

250

200

150

100

GROUND CURRENT (µA)

50

0

1 10 100 1000

TOTAL LOAD CURRENT (mA)

Figure 18. Ground Current vs. Load Current, All Outputs Loaded Equally

300

100

80

60

40

BIAS CURRENT (µA)

20

0

–40 –5 25 85 125

(°C)

T

09288-015

J

LOAD = 1mA LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA

09288-018

Figure 20. Bias Current vs. Junction Temperature, Single Output Loaded

100

90

80

70

60

50

40

BIAS CURRENT (µA)

30

20

10

0

1 10 100 1000

I

(mA)

09288-016

LOAD

09288-019

Figure 21. Bias Current vs. Load Current, Single Output Loaded

76

250

200

150

100

GROUND CURRENT (µA)

LOAD = 1mA LOAD = 5mA

50

LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA

0

1.7 2.1 2.5 2.9 3.3 3.7 4.1 4.5 4.9 5.3

(V)

V

IN

09288-017

Figure 19. Ground Current vs. Input Voltage, All Outputs Loaded Equally

Rev. A | Page 10 of 24

74

LOAD = 1mA LOAD = 5mA LOAD = 10mA LOAD = 50mA

72

LOAD = 100mA LOAD = 200mA

70

68

BIAS CURRENT (µA)

66

64

2.52.93.33.74.14.54.95.3

V

(V)

IN

Figure 22. Bias Current vs. Input Voltage, Single Output Loaded

09288-020

Data Sheet ADP322/ADP323

0.9

3.6

3.8

0.8

4.2

4.4

4.8

0.7

5.5

0.6

0.5

0.4

0.3

SHUTDOWN CURRENT (µA)

0.2

0.1

0

–50 –25 0 25 50 75 100 125

TEMPERATURE (° C)

Figure 23. Shutdown Current vs. Temperature at Various Input Voltages

09288-021

350

300

250

200

150

100

GROUND CURRENT (µA)

LOAD = 1mA LOAD = 5mA LOAD = 10mA

50

LOAD = 50mA LOAD = 100mA LOAD = 200mA

0

3.10 3.15 3.20 3.25 3.30 3.35 3.40 3.45 3.50

(V)

V

IN

Figure 26. Ground Current vs. Input Voltage (in Dropout), V

OUT1

= 3.3 V

09288-024

100

90

80

70

60

50

40

DROPOUT (mV)

30

20

10

0

1 10 100 1000

LOAD (mA)

Figure 24. Dropout Voltage vs. Load Current and Output Voltage,

= 3.3 V

V

OUT1

3.35 LOAD = 1mA LOAD = 5mA LOAD = 10mA

3.30 LOAD = 50mA LOAD = 100mA LOAD = 200mA

3.25

3.20

(V)

3.15

OUT

V

3.10

3.05

3.00

2.95

3.10 3.15 3.20 3.25 3.30 3. 35 3.40 3.45 3. 50

(V)

V

IN

Figure 25. Output Voltage vs. Input Voltage (in Dropout),

= 3.3 V

V

OUT1

300

250

200

150

DROPOUT (mV)

100

50

0

1 10 100 1000

09288-022

LOAD (mA)

09288-025

Figure 27. Dropout Voltage vs. Load Current and Output Voltage,

= 1.8 V

V

OUT2

1.85

1.80

1.75

1.70

(V)

1.65

OUT

V

1.60

1.55

1.50

1.45

1.70 1.80 1.90 2.00 2.10

(V)

V

09288-023

IN

LOAD = 1mA LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA

09288-026

Figure 28. Output Voltage vs. Input Voltage (in Dropout),

= 1.8 V

V

OUT2

Rev. A | Page 11 of 24

ADP322/ADP323 Data Sheet

A

√

160

140

120

100

80

60

GROUND CURRENT (µA)

LOAD = 1mA

40

LOAD = 5mA LOAD = 10mA LOAD = 50mA

20

LOAD = 100mA LOAD = 200mA

0

1.70 1.80 1.90 2.00 2.10

V

(V)

IN

Figure 29. Ground Current vs. Input Voltage (in Dropout), V

0

200mA 100mA

–10

10mA 1mA

–20

–30

–40

–50

PSRR (dB)

–60

–70

–80

–90

–100

10 100 1k 10k 100k 1M 10M

FREQUENCY ( Hz)

V

RIPPLE

V

IN

V

OUT

C

OUT

= 2.8V

= 1.8V = 1µF

= 50mV

Figure 30. Power Supply Rejection Ratio vs. Frequency, 1.8 V

0

200mA 100mA

–10

10mA 1mA

–20

–30

–40

–50

PSRR (dB)

–60

–70

–80

–90

–100

10 100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

V

RIPPLE

V

IN

V

OUT

C

OUT

= 4.3V

= 3.3V = 1µF

= 50mV

Figure 31. Power Supply Rejection Ratio vs. Frequency, 3.3 V

OUT2

= 1.8 V

09288-027

09288-028

09288-029

0

V

= 50mV

RIPPLE

V

= 2.5V

IN

–10

V

= 1.5V

OUT

C

= 1µF

OUT

–20

–30

–40

–50

PSRR (dB)

–60

–70

–80

–90

–100

10 100 1k 10k 100k 1M 10M

FREQUENCY ( Hz)

Figure 32. Power Supply Rejection Ratio vs. Frequency, 1.5 V

0

1.8V/200mA

1.8V/100mA

–10

1.8V/10mA

1.2V/200mA

–20

1.2V/100mA

1.2V/10mA

–30

–40

–50

PSRR (dB)

–60

–70

–80

–90

–100

10 100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

V

RIPPLE

1V HEADROOM

1.8V PSRR

1.2 XTALK

Figure 33. Power Supply Rejection Ratio vs. Frequency,

Channel-to-Channel Crosstalk

10

Hz)

1

L DENSITY (nV/

0.1

NOISE SPECTR

0.01 10 100 1k 10k 100k

FREQUENCY ( Hz)

Figure 34. Output Noise Spectral Density vs. Frequency, V

= 10 mA

I

LOAD

200mA 100mA 10mA 1mA

= 50mV

3.3V

1.8V

1.5V

IN

= 5 V,

09288-030

09288-031

09288-032

Rev. A | Page 12 of 24

Data Sheet ADP322/ADP323

70

3.3V

1.8V

1.5V

60

1

50

40

I

LOAD2

30

NOISE (µV rms)

20

10

0

0.001 0.01 0.1 1 10 100

LOAD CURRENT (mA)

Figure 35. Output Noise vs. Load Current and Output Voltage, V

I

LOAD1

1

2

3

4

V

OUT1

V

OUT2

V

OUT3

CH1 100mA CH2 50mV

CH3 10mV CH4 10mV

B

Ω

W

B

W

B

M40µs A CH1 44mA

W

B

T 9.8%

W

Figure 36. Load Transient Response,

= 1 mA to 200 mA, I

I

LOAD1

CH1 = I

LOAD1

, CH2 = V

OUT1

LOAD2

, CH3 = V

= I

LOAD3

OUT2

= 1 mA,

, CH4 = V

OUT3

1000

= 5 V

IN

V

CH2

LOAD2

I

LOAD3

V

OUT2

B

W

T 10.4%

= 1 mA to 200 mA, C

LOAD2

, CH2 = V

OUT3

B

W

T 10.2%

OUT2

09288-036

= 1 μF,

OUT2

09288-037

2

CH1 200mA 50mV M40 µs A CH1 84mA

09288-033

B

Ω

W

Figure 38. Load Transient Response, I

CH1 = I

1

2

09288-034

CH1 200mA CH2 50mV M40 µs A CH1 124mA

B

Ω

W

Figure 39. Load Transient Response,

= 1 mA to 200 mA, C

I

LOAD3

CH1 = I

LOAD3

, CH2 = V

OUT3

= 1 μF,

I

LOAD1

1

V

CH2

50mV

OUT1

B

W

T 10.2%

2

CH1 200mA M40µs A CH1 124mA

B

Ω

W

Figure 37. Load Transient Response,

= 1 mA to 200 mA, C

I

LOAD1

CH1 = I

LOAD1

, CH2 = V

OUT1

= 1 μF,

09288-035

Rev. A | Page 13 of 24

V

IN

1

V

OUT1

OUT2

OUT3

B

W

B

W

T 15%

2

3

4

CH1 1V CH2 10mV M1µs A CH1 4.62V

CH3 10mV

B

W

B

W

CH4 10mV

Figure 40. Line Transient Response,

= 4 V to 5 V, I

V

IN

CH1 = V

, CH2 = V

IN

LOAD1

OUT1

= I

LOAD2

, CH3 = V

= I

LOAD3

OUT2

=100 mA,

, CH4 = V

OUT3

09288-038

ADP322/ADP323 Data Sheet

V

IN

1

V

OUT1

OUT2

OUT3

2

3

4

V

ENx

1

2

V

OUT1

OUT2

OUT3

10mV

B

CH2

W

B

CH4

W

CH1 1V 10mV M2µs A CH1 4.58V

CH3

10mV

B

W

B

W

T 12%

Figure 41. Line Transient Response,

= 4 V to 5 V, I

V

IN

CH1 = V

, CH2 = V

IN

LOAD1

OUT1

= I

LOAD2

, CH3 = V

= I

OUT2

=1 mA,

LOAD3

, CH4 = V

OUT3

B

CH1 1V 500mV M100µs A CH1 540mV CH3

09288-039

500mV

W

B

W

CH2

CH4 500mV

Figure 42. Turn-On Response, I

CH1 = V

(the Enable Voltage), CH2 = V

ENx

B

CH4 = V

W

LOAD1

OUT3

T 10.2%

= I

LOAD2

= I

LOAD3

, CH3 = V

OUT1

=100 mA,

OUT2

09288-040

,

Rev. A | Page 14 of 24

Data Sheet ADP322/ADP323

V

2.5V

V

THEORY OF OPERATION

The ADP322/ADP323 triple LDO are low quiescent current, low dropout linear regulators that operate from 1.8 V to 5.5 V on VIN1/VIN2 and VIN3 and provide up to 200 mA of current from each output. Drawing a low 250 A quiescent current (typical) at full load makes the ADP322/ADP323 ideal for battery-operated portable equipment. Shutdown current consumption is typically 100 nA. Optimized for use with small 1 µF ceramic capacitors, the ADP322/ADP323 provide excellent transient performance.

Internally, the ADP322 consists of a reference, three error amplifiers, three feedback voltage dividers, and three PMOS pass transistors. Output current is delivered via the PMOS pass device, which is controlled by the error amplifier. The error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the difference. If the feedback voltage is lower than the reference voltage, the gate of the PMOS device is pulled lower, allowing more current to flow and increasing the output voltage. If the feedback voltage is higher than the reference voltage, the gate of the PMOS device is pulled higher, allowing less current to flow and decreasing the output voltage.

VIN1/VIN2

VBIAS

EN1

EN2

EN3

VIN3

GND

INTERNAL BI AS

VOLTAGE S/CURRENTS,

UVLO AND THERM AL

PROTECT

SHUTDOWN

VOUT1

SHUTDOWN

VOUT2

SHUTDOWN

VOUT3

OVERCURRENT

0.5V REF

Figure 43. ADP322 Internal Block Diagram

+ –

OUT1

OUT2

OUT3

09288-041

The ADP323 differs from the ADP322 except in that the output voltage dividers are internally disconnected and the feedback inputs of the error amplifiers are brought out for each output.

VIN1/VIN2

VOUT1

The output voltage can be set using the following formulas:

V

= 0.5 V(1 + R1/R2) + (FBIN)(R1)

OUT

V

= 0.5 V(1 + R3/R4) + (FBIN)(R3)

OUT2

= 0.5 V(1 + R5/R6) + (FBIN)(R5)

V

OUT3

The value of R1, R3, R5 should be less than 200 k to minimize errors in the output voltage caused by the FBx pin input current. For example, when R1 and R2 each equal 200 k, the output voltage is 1.0 V. The output voltage error introduced by the FBx pin input current is 2 mV or 0.20%, assuming a typical FBx pin input current of 10 nA at 25°C.

The ADP322 is available in multiple output voltage options ranging from 0.8 V to 3.3 V.

The ADP322/ADP323 use the EN1/EN2 and EN3 pins to enable and disable the VOUT1/VOUT2/VOUT3 pins under normal operating conditions. When the EN1/EN2 and EN3 pins are high, VOUT1/VOUT2/VOUT3 turn on; when the EN1/EN2 and EN3 pins are low, VOUT1/VOUT2/VOUT3 turn off. For automatic startup, the EN1/EN2 and EN3 pins can be tied to VBIAS.

ADP323

VBIAS

LDO 1

EN LD1

VBIAS

LDO 2

EN LD2

VBIAS

LDO 3

EN LD3

GND

FB1

FB2

FB3

VOUT1

+

R1

1µF

R2

VOUT2

+

R3

1µF

R4

VOUT3

+

R5

1µF

R6

9288-145

1.8

TO

5.5V

TO

5.5V

TO

5.5V

+

1µF

+

1µF

+

1µF

VBIAS

VIN1/VIN2

EN1

OFF

EN2

OFF

VIN3

EN3

OFF

ON

Figure 45. ADP323 Application Circuit Diagram

0.5V REF

+

–

+ –

+

–

INTERNAL BI AS

EN1

EN2

EN3

VIN3

GND

VOLTAG ES/CURRENTS,

UVLO AND THERM AL

PROTECT

SHUTDOWN

VOUT1

SHUTDOWN

VOUT2

SHUTDOWN

VOUT3

Figure 44. ADP323 Internal Block Diagram

VBIAS

OVERCURRENT

FB1

VOUT2

FB2

VOUT3

FB3

9288-055

Rev. A | Page 15 of 24

ADP322/ADP323 Data Sheet

APPLICATIONS INFORMATION

CAPACITOR SELECTION

Output Capacitor

The ADP322/ADP323 are designed for operation with small, space-saving ceramic capacitors, but the parts function with most commonly used capacitors as long as care is taken with the effective series resistance (ESR) value. The ESR of the output capacitor affects the stability of the LDO control loop. A minimum of 0.70 µF capacitance with an ESR of 1 Ω or less is recommended to ensure the stability of the ADP322/ADP323.

Transient response to changes in load current is also affected by output capacitance. Using a larger value of output capacitance improves the transient response of the ADP322/ADP323 to large changes in the load current. Figure 46 shows the transient response for an output capacitance value of 1 µF.

I

LOAD1

1

V

2

3

4

CH1 100mA Ω CH2 50mV

B

W

B

CH4 10mVCH3 10mV

W

Figure 46. Output Transient Response,

= 1 mA to 200 mA, I

I

LOAD1

CH1 = I

LOAD1

, CH2 = V

OUT1

V

OUT2

V

OUT3

B

M40µs A CH1 44mA

W

B

T 9.8%

W

= 1 mA, I

LOAD2

, CH3 = V

OUT1

OUT2

= 1 mA,

LOAD3

, CH4 = V

OUT3

09288-042

Input Bypass Capacitor

Connecting a 1 µF capacitor from VIN1/VIN2, VIN3, and VBIAS to GND reduces the circuit sensitivity to the PCB layout, especially when long input traces or high source impedance is encountered. If an output capacitance greater than 1 µF is required, the input capacitor should be increased to match it.

Input and Output Capacitor Properties

Any good quality ceramic capacitor can be used with the ADP322/ ADP323, as long as the capacitor meets the minimum capacitance and maximum ESR requirements. Ceramic capacitors are manufactured with a variety of dielectrics, each with a different behavior over temperature and applied voltage. Capacitors must have an adequate dielectric to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. X5R or X7R dielectrics with a voltage rating of 6.3 V or 10 V are recommended. Y5V and Z5U dielectrics are not recommended due to their poor temperature and dc bias characteristics.

Figure 47 depicts the capacitance vs. voltage bias characteristic of a 0402 1 µF, 10 V, X5R capacitor. The voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rating. In general, a capacitor in a larger package or with a higher voltage rating exhibits better stability. The temperature variation of the X5R dielectric is about ±15% over the −40°C to +85°C temperature range and is not a function of the package or voltage rating.

1.2

1.0

0.8

Rev. A | Page 16 of 24

0.6

0.4

CAPACITANCE (µF )

0.2

0

024681

VOLTAGE (V)

Figure 47. Capacitance vs. Voltage Bias Characteristic

0

09288-043

Data Sheet ADP322/ADP323

Use Equation 1 to determine the worst-case capacitance, accounting for capacitor variation over temperature, component tolerance, and voltage.

C

= C

EFF

× (1 − TEMPCO) × (1 − TOL) (1)

BIAS

where: C

is the effective capacitance at the operating voltage.

BIAS

TEMPCO is the worst-case capacitor temperature coefficient. TOL is the worst-case component tolerance.

In this example, TEMPCO over −40°C to +85°C is assumed to be 15% for an X5R dielectric. TOL is assumed to be 10%, and C

is 0.94 F at 1.8 V (from the graph in Figure 47).

BIAS

Substituting these values into Equation 1 yields

C

= 0.94 F × (1 − 0.15) × (1 − 0.1) = 0.719 F

EFF

Therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the LDO over temperature and tolerance at the chosen output voltage.

To guarantee the performance of the ADP322/ADP323 triple LDO, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application.

UNDERVOLTAGE LOCKOUT

The ADP322/ADP323 have an internal undervoltage lockout circuit that disables all inputs and the output when the input voltage bias, VBIAS, is less than approximately 2.2 V. This ensures that the inputs of the ADP322/ADP323 and the output behave in a predictable manner during power-up.

ENABLE FEATURE

The ADP322/ADP323 use the ENx pins to enable and disable the VOUTx pins under normal operating conditions. Figure 48 shows that, when a rising voltage on ENx crosses the active threshold, VOUTx turns on. When a falling voltage on ENx crosses the inactive threshold, VOUTx turns off.

1.4

V

@ 4.5V

OUT

1.2

IN

As shown in Figure 48, the ENx pin has built-in hysteresis. This prevents on/off oscillations that can occur due to noise on the ENx pin as it passes through the threshold points.

The active/inactive thresholds of the ENx pin are derived from the V

voltage. Therefore, these thresholds vary with

BIAS

changing input voltage. Figure 49 shows typical ENx active/ inactive thresholds when the input voltage varies from 2.5 V to 5.5 V (note that V

1.00

0.95

0.90

0.85

0.80

0.75

0.70

0.65

ENABLE THRESHOLDS

0.60

0.55

0.50

V

2.5 3.0 3.5 4.0 4.5 5.0 5.5

Figure 49. Typical ENx Pins Thresholds vs. Input Voltage

is the enable voltage).

ENx

RISE

ENx

INPUT VOLTAGE (V)

V

FALL

ENx

09288-045

The ADP322/ADP323 use an internal soft start to limit the inrush current when the output is enabled. The start-up time for the 2.8 V option is approximately 220 µs from the time the ENx active threshold is crossed to when the output reaches 90% of its final value. The start-up time is somewhat dependent on the output voltage setting and increases slightly as the output voltage increases.

V

ENx

1

V

OUT1

OUT2

OUT3

1.0

0.8

(V)

0.6

OUT

V

0.4

0.2

0

0.4 0.60.5 0.7 0.90.8 1.0 1.1 1.2

ENABLE VOLTAGE (V)

Figure 48. Typical ENx Pin Operation

09288-044

Rev. A | Page 17 of 24

2

B

CH1 1V 500mV M100µs A CH1 540mV

500mV

CH3

W

B

W

CH2

CH4 500mV

Figure 50. Typical Start-Up Time,I

CH1 = V

(the Enable Voltage), CH2 = V

ENx

B

W

B

W

T 10.2%

= I

OUT1

= I

LOAD2

, CH3 = V

LOAD1

= 100 mA,

LOAD3

OUT2

, CH4 = V

09288-046

OUT3

ADP322/ADP323 Data Sheet

CURRENT-LIMIT AND THERMAL OVERLOAD PROTECTION

The ADP322/ADP323 are protected against damage due to excessive power dissipation by current and thermal overload protection circuits. The ADP322/ADP323 are designed to current limit when the output load reaches 300 mA (typical). When the output load exceeds 300 mA, the output voltage is reduced to maintain a constant current limit.

Thermal overload protection is built in, which limits the junction temperature to a maximum of 155°C (typical). Under extreme conditions (that is, high ambient temperature and power dissipation) when the junction temperature starts to rise above 155°C, the output is turned off, reducing the output current to zero. When the junction temperature drops below 140°C, the output is turned on again and the output current is restored to its nominal value.

Consider the case where a hard short from VOUTx to GND occurs. At first, the ADP322/ADP323 limits current so that only 300 mA is conducted into the short. If self-heating of the junction is great enough to cause its temperature to rise above 155°C, thermal shutdown activates, turning off the output and reducing the output current to zero. As the junction temperature cools and drops below 140°C, the output turns on and conducts 300 mA into the short, again causing the junction temperature to rise above 155°C. This thermal oscillation between 140°C and 155°C causes a current oscillation between 0 mA and 300 mA that continues as long as the short remains at the output.

Current and thermal limit protections are intended to protect the device against accidental overload conditions. For reliable operation, device power dissipation must be externally limited so that junction temperatures do not exceed 125°C.

THERMAL CONSIDERATIONS

In most applications, the ADP322/ADP323 do not dissipate a lot of heat due to high efficiency. However, in applications with a high ambient temperature and high supply voltage to output voltage differential, the heat dissipated in the package is large enough that it can cause the junction temperature of the die to exceed the maximum junction temperature of 125°C.

When the junction temperature exceeds 155°C, the converter enters thermal shutdown. It recovers only after the junction temperature decreases below 140°C to prevent any permanent damage. Therefore, thermal analysis for the chosen application is very important to guarantee reliable performance over all conditions. The junction temperature of the die is the sum of the ambient temperature of the environment and the temperature rise of the package due to the power dissipation, as shown in Equation 2.

To guarantee reliable operation, the junction temperature of the ADP322/ADP323 must not exceed 125°C. To ensure that the junction temperature stays below this maximum value, the user must be aware of the parameters that contribute to junction temperature changes. These parameters include ambient temperature, power dissipation in the power device, and thermal resistances between the junction and ambient air (θ

). The θJA

JA

number is dependent on the package assembly compounds used and the amount of copper to which the GND pins of the package are soldered on the PCB. Ta b le 7 shows typical θ

values for the

JA

ADP322/ADP323 for various PCB copper sizes.

Table 7. Typical θ

Values

JA

Copper Size (mm2) ADP322/ADP323 Triple LDO (°C/W)

JEDEC1 49.5 100 83.7 500 68.5 1000 64.7

1

Device soldered to JEDEC standard board.

The junction temperature of the ADP322/ADP323 can be calculated from the following equation:

T

= TA + (PD × θJA) (2)

J

where:

T

is the ambient temperature.

A

P

is the power dissipation in the die, given by

D

P

= Σ[(VIN − V

D

OUT

) × I

] + Σ(VIN × I

LOAD

) (3)

GND

where:

I

is the load current.

LOAD

I

is the ground current.

GND

V

and V

IN

are input and output voltages, respectively.

OUT

Power dissipation due to ground current is quite small and can be ignored. Therefore, the junction temperature equation simplifies to

T

= TA + {Σ[(VIN − V

J

OUT

) × I

] × θJA} (4)

LOAD

As shown in Equation 4, for a given ambient temperature, input-to-output voltage differential, and continuous load current, there exists a minimum copper size requirement for the PCB to ensure that the junction temperature does not rise above 125°C. Figure 51 to Figure 54 show junction temperature calculations for different ambient temperatures, total power dissipation, and areas of PCB copper.

In cases where the board temperature is known, the thermal characterization parameter, Ψ junction temperature rise. T

, can be used to estimate the

JB

is calculated from TB and PD using

J

the formula

T

= TB + (PD × ΨJB) (5)

J

The typical Ψ

value for the 16-lead, 3 mm × 3 mm LFCSP is

JB

25.2°C/W.

Rev. A | Page 18 of 24

Data Sheet ADP322/ADP323

A

R

A

140

120

(°C)

J

100

TURE, T

80

60

40

JUNCTION TEM PER

20

0

0 0.2 0.4 0.6 0. 8 1.0 1.2

TOTAL POWER DISSIPATION (W)

Figure 51. Junction Temperature vs. Total Power Dissipation, T

140

120

(°C)

J

100

TURE, T

80

60

1000mm 500mm 100mm 50mm JEDEC T

MAX

J

2 2 2

2

= 25°C

A

140

120

(°C)

J

100

TURE, T

80

60

40

JUNCTION TEMPER

20

0

0 0.2 0.4 0.6 0.8 1.0 1.2

09288-047

TOTAL POWER DISSIPATION (W )

Figure 53. Junction Temperature vs. Total Power Dissipation, T

140

120

(°C)

J

100

TURE, T

80

60

1000mm 500mm 100mm 50mm JEDEC T

MAX

J

2 2 2

2

= 85°C

A

09288-049

40

JUNCTION TEM PE

20

0

00.20.40.6

TOTAL POWER DISSIPATION (W)

0.8 1. 0

1000mm 500mm 100mm 50mm JEDEC T

MAX

J

Figure 52. Junction Temperature vs. Total Power Dissipation, T

2 2 2

2

1.2

= 50°C

A

40

JUNCTION TEMPER

20

0

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8

09288-048

TOTAL POWER DISSIPATION (W)

TB = 25°C T

= 50°C

B

T

= 85°C

B

T

MAX

J

09288-050

Figure 54. Junction Temperature vs. Total Power Dissipation and

Board Temperature

Rev. A | Page 19 of 24

ADP322/ADP323 Data Sheet

PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS

Heat dissipation from the package can be improved by increasing the amount of copper attached to the pins of the ADP322/ADP323. However, as can be seen from Tabl e 7, a point of diminishing returns is eventually reached, beyond which an increase in the copper size does not yield significant heat dissipation benefits.

Place the input capacitor as close as possible to the VINx and GND pins. Place the output capacitors as close as possible to the VOUTx and GND pins. Use 0402 or 0603 size capacitors and resistors to achieve the smallest possible footprint solution on boards where area is limited.

09288-051

Figure 55. Example of PCB Layout, Top Side

09288-052

Figure 56. Example of PCB Layout, Bottom Side

Rev. A | Page 20 of 24

Data Sheet ADP322/ADP323

OUTLINE DIMENSIONS

PIN 1

INDICATOR

0.80

0.75

0.70

SEATING

PLANE

3.10

3.00 SQ

2.90

0.50

BSC

0.50

0.40

0.30

0.05 MAX

0.02 NOM

0.20 REF

0.30

0.25

0.20

13

12

9

8

BOTTOM VIEWTOP VIEW

COPLANARITY

0.08

1

P

N

I

C

I

N

I

D

16

1

EXPOSED

PAD

5

FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.

1.65

1.50 SQ

1.45

4

0.20 MIN

R

A

O

T

COMPLIANTTOJEDEC STANDARDS MO-229.

091609-A

Figure 57. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

3 mm × 3 mm Body, Very, Very Thin Quad

(CP-16-27)

Dimensions shown in millimeters

ORDERING GUIDE

Temperature

Model1

Range

VOUT1 VOUT2 VOUT3

ADP322ACPZ-115-R7 −40°C to +125°C 3.3 V 2.8 V 1.8 V 16-Lead LFCSP_WQ CP-16-27 LGU ADP322ACPZ-135-R7 −40°C to +125°C 3.3 V 2.5 V 1.8 V 16-Lead LFCSP_WQ CP-16-27 LGT ADP322ACPZ-145-R7 −40°C to +125°C 3.3 V 2.5 V 1.2 V 16-Lead LFCSP_WQ CP-16-27 LJC ADP322ACPZ-155-R7 −40°C to +125°C 3.3 V 1.8 V 1.5 V 16-Lead LFCSP_WQ CP-16-27 LGS ADP322ACPZ-165-R7 −40°C to +125°C 3.3 V 1.8 V 1.2V 16-Lead LFCSP_WQ CP-16-27 LLX ADP322ACPZ-175-R7 −40°C to +125°C 2.8 V 1.8 V 1.2 V 16-Lead LFCSP_WQ CP-16-27 LGR ADP322ACPZ-189-R7 −40°C to +125°C 2.5 V 1.8 V 1.2 V 16-Lead LFCSP_WQ CP-16-27 LJD ADP323ACPZ-R7 −40°C to +125°C Adjustable Adjustable Adjustable 16-Lead LFCSP_WQ CP-16-27 LGQ ADP322CP-EVALZ Evaluation board ADP323CP-EVALZ Evaluation board ADP322CPZ-REDYKIT Evaluation board kit

1

Z = RoHS Compliant Part.

2

For additional voltage options, contact a local sales or distribution representative.

Output Voltage (V)2

Package Description

Package Option Branding

Rev. A | Page 21 of 24

ADP322/ADP323 Data Sheet

NOTES

Rev. A | Page 22 of 24

Data Sheet ADP322/ADP323

NOTES

Rev. A | Page 23 of 24

ADP322/ADP323 Data Sheet

NOTES

Rev. A | Page 24 of 24

Datasheet ADP323 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

TYPICAL APPLICATION CIRCUITS

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

THEORY OF OPERATION

APPLICATIONS INFORMATION

CAPACITOR SELECTION

Output Capacitor

Input Bypass Capacitor

Input and Output Capacitor Properties

UNDERVOLTAGE LOCKOUT

ENABLE FEATURE

CURRENT-LIMIT AND THERMAL OVERLOAD PROTECTION

THERMAL CONSIDERATIONS

PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS

OUTLINE DIMENSIONS

ORDERING GUIDE