ANALOG DEVICES ADP323 Service Manual

Triple, 200 mA, Low Noise,

O

Data Sheet

FEATURES

Fixed (ADP322) and adjustable output (ADP323) options Bias voltage range (VBIAS): 2.5 V to 5.5 V LDO input voltage range (VIN1/VIN2, VIN3): 1.8 V to 5.5 V Three 200 mA low dropout voltage regulators (LDOs) 16-lead, 3 mm × 3 mm LFCSP Initial accuracy: ±1% Stable with 1 μF ceramic output capacitors No noise bypass capacitor required 3 independent logic controlled enables Overcurrent and thermal protection Key specifications

High PSRR

76 dB PSRR up to 1 kHz 70 dB PSRR at 10 kHz 60 dB PSRR at 100 kHz 40 dB PSRR at 1 MHz

Low output noise

29 μV rms typical output noise at V

55 μV rms typical output noise at V Excellent transient response Low dropout voltage: 110 mV at 200 mA load 85 μA typical ground current at no load, all LDOs enabled 100 μs fast turn-on circuit Guaranteed 200 mA output current per regulator

−40°C to +125°C junction temperature

APPLICATIONS

Mobile phones Digital cameras and audio devices Portable and battery-powered equipment Portable medical devices Post dc-to-dc regulation

= 1.2 V

OUT

= 2.8 V

OUT

High PSRR Voltage Regulator

ADP322/ADP323

TYPICAL APPLICATION CIRCUITS

VBIAS

LDO 1

EN LD1

VBIAS

LDO 2

EN LD2

VBIAS

LDO 3

EN LD3

GND

VBIAS

LDO 1

EN LD1

VBIAS

LDO 2

EN LD2

VBIAS

LDO 3

EN LD3

GND

FB1

FB2

FB3

VOUT1

+

1µF

VOUT2

+

1µF

VOUT3

+

1µF

VOUT1

+

1µF

VOUT2

+

1µF

VOUT3

+

1µF

2.5V T

1.8V T

2.5V TO

5.5V

1.8V TO

5.5V

1.8V TO

5.5V

OFF

ADP322

ON

5.5V

VBIAS

VIN1/VIN2

VIN3

+

1µF

+

1µF

EN1

EN2

+

1µF

EN3

Figure 1. Typical Application Circuit for ADP322

VBIAS

VIN1/VIN2

VIN3

+

1µF

+

1µF

EN1

EN2

+

1µF

EN3

ADP323

ON

OFF

ON

OFF

ON

OFF

Figure 2. Typical Application Circuit for ADP323

09288-001

09288-053

GENERAL DESCRIPTION

The ADP322/ADP323 200 mA triple output LDOs combine high PSRR, low noise, low quiescent current, and low dropout voltage to extend the battery life of portable devices and are ideally suited for wireless applications with demanding performance and board space requirements.

The ADP322/ADP323 PSRR is greater than 60 dB for frequencies as high as 100 kHz while operating with a low headroom voltage. The ADP322/ADP323 offer much lower noise performance than competing LDOs without the need for a noise bypass capacitor.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

The ADP322/ADP323 are available in a miniature 16-lead, 3 mm × 3 mm LFCSP package and are stable with tiny 1 µF ±30% ceramic output capacitors providing the smallest possible board area for a wide variety of portable power needs.

The ADP322 is available in output voltage combinations ranging from 0.8 V to 3.3 V and offers overcurrent and thermal protection to prevent damage in adverse conditions. The APDP323 adjustable triple LDO can be configured for any output voltage between 0.5 V and 5 V with two resistors for each output.

ADP322/ADP323 Data Sheet

REVISION HISTORY

9/11—Rev.0 to Rev. A

Added Figure 2, Renumbered Sequentially .................................. 1

Changes to Theory of Operation Section.................................... 15

Added Figure 45, Renumbered Sequentially .............................. 15

Changes to Ordering Guide.......................................................... 21

Theory of Operation ...................................................................... 15

Applications Information.............................................................. 16

Capacitor Selection .................................................................... 16

Undervoltage Lockout............................................................... 17

Enable Feature ............................................................................ 17

Current-Limit and Thermal Overload Protection................. 18

Thermal Considerations............................................................ 18

Printed Circuit Board Layout Considerations ....................... 20

Outline Dimensions....................................................................... 21

Ordering Guide .......................................................................... 21

9/10—Revision 0: Initial Version

Rev. A | Page 2 of 24

Data Sheet ADP322/ADP323

SPECIFICATIONS

V C

Table 1.

Parameter Symbol Conditions Min Typ Max Unit

VOLTAGE RANGE

CURRENT

I I I I I

T

EN1 = EN2 = EN3 = GND, TJ = −40°C to +125°C 2.5 μA FEEDBACK INPUT CURRENT FBIN 0.01 μA VOLTAGE ACCURACY

LINE REGULATION ∆V V LOAD REGULATION2 ∆V I DROPOUT VOLTAGE3 V

I I I START-UP TIME4 T V

V CURRENT LIMIT THRESHOLD5 I THERMAL SHUTDOWN

= V

IN1/VIN2

= C

IN

OUT1

IN3

= C

= (V

OUT2

Input Bias Voltage Range V Input LDO Voltage Range V

Ground Current with All

+ 0.5 V) or 1.8 V (whichever is greater), V

OUT

= C

= 1 µF, and TA = 25°C, unless otherwise noted.

OUT3

T

BIAS

IN1/VIN2/VIN3

I

GND

= −40°C to +125°C 2.5 5.5 V

J

TJ = −40°C to +125°C 1.8 5.5 V

OUT

BIAS

= 0 μA 85 μA

Regulators On

= 0 μA, TJ = −40°C to +125°C 160 μA

OUT

= 10 mA 120 μA

OUT

= 10 mA, TJ = −40°C to +125°C 220 μA

OUT

= 200 mA 250 μA

OUT

= 200 mA, TJ = −40°C to +125°C 380 μA

OUT

Bias Voltage Input Current I

Shutdown Current I

Output Voltage Accuracy

66 μA

BIAS

= −40°C to +125°C 140 μA

J

EN1 = EN2 = EN3 = GND 0.1 μA

GND-SD

−1 +1 %

V

OUT

(ADP322)

0.495 0.5 0.505 V

Feedback Voltage Accuracy

(ADP323)

1

V

FB

100 μA < I T

= −40°C to +125°C

J

100 μA < I

= −40°C to +125°C

T

J

/∆VIN VIN = (V

OUT

= (V

IN

/∆I

I

OUT

DROPOUT

V

START-UP

= 1 mA to 200 mA 0.001 %/mA

OUT

= 1 mA to 200 mA, TJ = −40°C to +125°C 0.005 %/mA

OUT

V

= 3.3 V mV

OUT

I

= 10 mA 6 mV

OUT

= 10 mA, TJ = −40°C to +125°C 9 mV

OUT

= 200 mA 110 mV

OUT

= 200 mA, TJ = −40°C to +125°C 170 mV

OUT

= 3.3 V, all V

OUT

= 0.8 V 100 μs

OUT

= 3.3 V, one V

V

OUT

< 200 mA, VIN = (V

OUT

< 200 mA, VIN = (V

OUT

+ 0.5 V) to 5.5 V 0.01 %/ V

OUT

+ 0.5 V) to 5.5 V, TJ = −40°C to +125°C −0.03 +0.03 %/ V

OUT

third LDO

= 0.8 V 20 μs

OUT

250 360 600 mA

LIMIT

Thermal Shutdown Threshold TSSD T Thermal Shutdown Hysteresis TS

15 °C

SD-HYS

rising 155 °C

J

= 2.5 V, EN1, EN2, EN3 = V

+ 0.5 V) to 5.5 V,

OUT

+ 0.5 V) to 5.5 V,

OUT

, I

= I

BIAS

OUT1

OUT2

= 10 mA,

OUT3

−2 +2 %

0.490 0.510 V

initially off, enable any LDO 240 μs

initially on, enable second or

OUT

160 μs

Rev. A | Page 3 of 24

ADP322/ADP323 Data Sheet

Parameter Symbol Conditions Min Typ Max Unit

EN INPUT

EN Input Logic High VIH 2.5 V ≤ V EN Input Logic Low VIL 2.5 V ≤ V EN Input Leakage Current V

EN1 = EN2 = EN3 = VIN or GND 0.1 μA

I-LEAKAGE

EN1 = EN2 = EN3 = V

= −40°C to +125°C

T

J

UNDERVOLTAGE LOCKOUT UVLO

Input Bias Voltage (VBIAS)

UVLO

2.45 V

RISE

Rising

Input Bias Voltage (VBIAS)

UVLO

2.0 V

FAL L

Falling

Hysteresis UVLO

OUTPUT NOISE OUT

180 mV

HYS

10 Hz to 100 kHz, VIN = 5 V, V

NOISE

10 Hz to 100 kHz, VIN = 5 V, V 10 Hz to 100 kHz, VIN = 3.6 V, V 10 Hz to 100 kHz, VIN = 3.6 V, V POWER SUPPLY REJECTION RATIO PSRR VIN = 1.8 V, V 100 Hz 70 dB 1 kHz 70 dB 10 kHz 70 dB 100 kHz 60 dB 1 MHz 40 dB V

= 3.8 V, V

IN

100 Hz 68 dB 1 kHz 62 dB 10 kHz 68 dB 100 kHz 60 dB 1 MHz 40 dB

1

Accuracy when VOUTx is connected directly to FBx. When the VOUTx voltage is set by external feedback resistors, the absolute accuracy in adjust mode depends on

the tolerances of the resistors used.

2

Based on an end-point calculation using 1 mA and 200 mA loads.

3

The dropout voltage specification applies only to output voltages greater than 1.8 V. Dropout voltage is defined as the input-to-output voltage differential when the

input voltage is set to the nominal output voltage.

4

Start-up time is defined as the time between the rising edge of ENx to VOUTx being at 90% of its nominal value.

5

Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V

output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, that is, 2.7 V.

≤ 5.5 V 1.2 V

BIAS

≤ 5.5 V 0.4 V

BIAS

1 μA

= 0.8 V, I

OUT

= 2.8 V, I

OUT

or GND,

IN

= 3.3 V 63 μV rms

OUT

= 2.8 V 55 μV rms

OUT

= 2.5 V 50 μV rms

OUT

= 1.2 V 29 μV rms

OUT

= 100 mA

OUT

= 100 mA

OUT

INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS

Table 2.

Parameter Symbol Conditions Min Typ Max Unit

MINIMUM INPUT AND OUTPUT CAPACITANCE1 C CAPACITOR ESR R

1

The minimum input and output capacitance should be greater than 0.70 μF over the full range of operating conditions. The full range of operating conditions in the

application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended; Y5V and Z5U capacitors are not recommended for use with LDOs.

TA = −40°C to +125°C 0.70 μF

MIN

T

ESR

Rev. A | Page 4 of 24

= −40°C to +125°C 0.001 1 Ω

A

Data Sheet ADP322/ADP323

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

VIN1/VIN2, VIN3, VBIAS to GND –0.3 V to +6.5 V VOUT1, VOUT2, FB1, FB2 to GND –0.3 V to VIN1/VIN2 VOUT3, FB3 to GND –0.3 V to VIN3 EN1, EN2, EN3 to GND –0.3 V to +6.5 V Storage Temperature Range –65°C to +150°C Operating Junction Temperature Range –40°C to +125°C Soldering Conditions JEDEC J-STD-020

Junction-to-ambient thermal resistance (θ based on modeling and calculation using a 4-layer board. The junction-to-ambient thermal resistance is highly dependent on the application and board layout. In applications where high maximum power dissipation exists, close attention to thermal board design is required. The value of θJA may vary, depending on PCB material, layout, and environmental conditions. The specified values of θ circuit board. See JEDEC JESD 51-9 for detailed information on the board construction. For additional information, see the AN-617 Application Note, MicroCSP™ Wafer Level Chip Scale

Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL DATA

Absolute maximum ratings apply individually only, not in combination.

The ADP322/ADP323 triple LDO can be damaged when the junction temperature limits are exceeded. Monitoring ambient temperature does not guarantee that the junction temperature (T

) is within the specified temperature limits. In applications

J

with high power dissipation and poor thermal resistance, the maximum ambient temperature may have to be derated. In applications with moderate power dissipation and low PCB

Package.

Ψ

is the junction to board thermal characterization parameter

JB

with units of °C/W. Ψ calculation using a 4-layer board. The JESD51-12, Guidelines for Reporting and Using Package Thermal Information, states that thermal characterization parameters are not the same as thermal resistances. Ψ multiple thermal paths rather than a single path as in thermal resistance, θ from the top of the package as well as radiation from the package, factors that make Ψ Maximum junction temperature (T temperature (T formula:

T

= TB + (PD × ΨJB)

J

See JEDEC JESD51-8 and JESD51-12 for more detailed information about Ψ

thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits.

The junction temperature (T ambient temperature (T (P

), and the junction-to-ambient thermal resistance of the

D

package (θ

). Maximum junction temperature (TJ) is calculated

JA

from the ambient temperature (T

) of the device is dependent on the

J

), the power dissipation of the device

A

) and power dissipation (PD)

A

THERMAL RESISTANCE

θJA and ΨJB are specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.

Table 4.

Package Type θJA ΨJB Unit

16-Lead, 3 mm × 3 mm LFCSP 49.5 25.2 °C/W

using the following formula:

T

= TA + (PD × θJA)

J

ESD CAUTION

are based on a 4-layer, 4 inch × 3 inch

JA

of the package is based on modeling and

JB

measures the component power flowing through

JB

. Therefore, ΨJB thermal paths include convection

JB

more useful in real-world applications.

JB

) is calculated from the board

J

) and power dissipation (PD) using the following

B

.

JB

) of the package is

JA

Rev. A | Page 5 of 24

ADP322/ADP323 Data Sheet

C

2

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

EN2

EN3

NC

16

1

EN1

2

VBIAS

VIN1/VIN2

NC

NOTES

1. NC = NO CONNE . CONNECT EXP OSED PAD TO GROUND PLANE.

3

4

ADP322

5

VOUT1

TOP VIEW

(Not to Scale)

T.

Figure 3. ADP322 Pin Configuration

Table 5. ADP322 Pin Function Descriptions

Pin No. Mnemonic Description

1 EN1

Enable Input for Regulator 1. Drive EN1 high to turn on Regulator 1; drive it low to turn off Regulator 1. For

automatic startup, connect EN1 to VBIAS. 2 VBIAS Input Voltage Bias Supply. Bypass VBIAS to GND with a 1 μF or greater capacitor. 3 VIN1/VIN2

Regulator Input Supply for Output Voltage 1 and Output Voltage 2. Bypass VIN1/VIN2 to GND with a 1 μF or

greater capacitor. 4 NC Not connected internally. 5 VOUT1 Regulated Output Voltage 1. Connect a 1 μF or greater output capacitor between VOUT1 and GND. 6 VOUT2 Regulated Output Voltage 2. Connect a 1 μF or greater output capacitor between VOUT2 and GND. 7 NC Not connected internally. 8 VOUT3 Regulated Output Voltage 3. Connect a 1 μF or greater output capacitor between VOUT3 and GND. 9 NC Not connected internally. 10 VIN3 Regulator Input Supply for Output Voltage 3. Bypass VIN3 to GND with a 1 μF or greater capacitor. 11 NC Not connected internally. 12 GND Ground Pin. 13 NC Not connected internally. 14 NC Not connected internally. 15 EN3

Enable Input for Regulator 3. Drive EN3 high to turn on Regulator 3; drive it low to turn off Regulator 3. For

automatic startup, connect EN3 to VBIAS. 16 EN2

Enable Input for Regulator 2. Drive EN3 high to turn on Regulator 2; drive it low to turn off Regulator 2. For

automatic startup, connect EN2 to VBIAS. EP Exposed pad for enhanced thermal performance. Connect to copper ground plane.

NC

13

15

14

12

GND

11

NC

10

VIN3

9NC

8

7

6

NC

VOUT2

VOUT3

09288-002

Rev. A | Page 6 of 24

Data Sheet ADP322/ADP323

C

2

EN2

EN3

NC

16

1

EN1

2

VBIAS

VIN1/VIN2

FB1

NOTES

1. NC = NO CONNE . CONNECT EXP OSED PAD TO GROUND PLANE.

3

4

ADP323

5

VOUT1

TOP VIEW

(Not to Scale)

T.

Figure 4. ADP323 Pin Configuration

Table 6. ADP323 Pin Function Descriptions

Pin No. Mnemonic Description

1 EN1

Enable Input for Regulator 1. Drive EN1 high to turn on Regulator 1; drive it low to turn off Regulator 1. For

automatic startup, connect EN1 to VBIAS. 2 VBIAS Input Voltage Bias Supply. Bypass VBIAS to GND with a 1 μF or greater capacitor. 3 VIN1/VIN2

Regulator Input Supply for Output Voltage 1 and Output Voltage 2. Bypass VIN1/VIN2 to GND with a 1 μF or

greater capacitor. 4 FB1 Connect the midpoint of the voltage divider from VOUT1 to GND to set VOUT1. 5 VOUT1 Regulated Output Voltage 1. Connect a 1 μF or greater output capacitor between VOUT1 and GND. 6 VOUT2 Regulated Output Voltage 2. Connect a 1 μF or greater output capacitor between VOUT2 and GND. 7 FB2 Connect the midpoint of the voltage divider from VOUT2 to GND to set VOUT2. 8 VOUT3 Regulated Output Voltage 3. Connect a 1 μF or greater output capacitor between VOUT3 and GND. 9 FB3 Connect the midpoint of the voltage divider from VOUT3 to GND to set VOUT3. 10 VIN3 Regulator Input Supply for Output Voltage 3. Bypass VIN3 to GND with a 1 μF or greater capacitor. 11 NC Not connected internally. 12 GND Ground Pin. 13 NC Not connected internally. 14 NC Not connected internally. 15 EN3

Enable Input for Regulator 3. Drive EN3 high to turn on Regulator 3; drive it low to turn off Regulator 3. For

automatic startup, connect EN3 to VBIAS. 16 EN2

Enable Input for Regulator 2. Drive EN3 high to turn on Regulator 2; drive it low to turn off Regulator 2. For

automatic startup, connect EN2 to VBIAS. EP Exposed pad for enhanced thermal performance. Connect to copper ground plane.

NC

13

15

14

12

GND

11

NC

10

VIN3

9FB3

8

7

6

FB2

VOUT2

VOUT3

09288-054

Rev. A | Page 7 of 24

ADP322/ADP323 Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

V enable voltage, T

IN1/VIN2

3.33

3.32

3.31

(V)

3.30

OUT

V

3.29

3.28

= V

=V

IN3

LOAD = 1mA LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA

= 4 V, V

BIAS

= 25°C, unless otherwise noted.

A

= 3.3 V, V

OUT1

= 1.8 V, V

OUT2

OUT3

= 1.5 V, I

= 10 mA, CIN = C

OUT

1.820

1.815

1.810

1.805

(V)

1.800

OUT

V

1.795

1.790

1.785

OUT1

LOAD = 1mA LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA

= C

OUT2

= C

OUT3

= 1 µF, V

ENX

is the

3.27

–40–52585125

T

(°C)

J

Figure 5. Output Voltage vs. Junction Temperature

3.320

3.315

(V)

3.310

OUT

V

3.305

3.300

1 10 100 1000

I

(mA)

LOAD

Figure 6. Output Voltage vs. Load Current

3.320

3.315

LOAD = 1mA LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA

1.780

09288-003

–40 –5 25 85 125

(°C)

T

J

09288-006

Figure 8. Output Voltage vs. Junction Temperature

1.820

1.815

(V)

1.810

OUT

V

1.805

1.800

1 10 100 1000

(mA)

I

09288-004

LOAD

09288-007

Figure 9. Output Voltage vs. Load Current

1.820

1.815

LOAD = 1mA LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA

(V)

3.310

OUT

V

3.305

3.300

3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4

(V)

V

IN

Figure 7. Output Voltage vs. Input Voltage

09288-005

Rev. A | Page 8 of 24

(V)

1.810

OUT

V

1.805

1.800

2.1 2.5 2.9 3.3 3. 7 4 .1 4.5 4.9 5.3

V

(V)

IN

Figure 10. Output Voltage vs. Input Voltage

09288-008

ANALOG DEVICES ADP323 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

TYPICAL APPLICATION CIRCUITS

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS