Analog Devices ADP3204 Datasheet

3-Phase IMVP-II and IMVP-III

a

FEATURES
Pin Selectable 1-, 2-, or 3-Phase Operation
Static and Dynamic Current Sharing Characteristics
Backward Compatible to IMVP-II
Superior Load Transient Response with ADOPT
Analog Devices’ Optimal Positioning Technology
Noise-Blanking for Speed and Stability
Synchronous Rectifier Control Extends Battery Life
Smooth Output Transition During VID Code Change
Cycle-by-Cycle Current Limiting
Hiccup or Latched Overload Protection
Transient-Glitch-Free Power Good
Soft Start Eliminates Power-On In-Rush Current Surge
Two-Level Overvoltage and Reverse Voltage

Protection

APPLICATIONS
IMVP-II and IMVP-III Core DC-to-DC Converters
Fixed Voltage Mobile CPU Core DC-to-DC Converters
Notebook/Laptop Power Supplies
Programmable Output Power Supplies

®

Core Controller for Mobile CPUs

*

OUT3

OUT2

OUT1

CS3

CS2

CS1

CS+

CS–

RAMP

REG

DACOUT

DACRAMP

HYSSET

DSHIFT

BSHIFT

DPRSHIFT

VID4

VID3

VID2

VID1

VID0

ADP3204

FUNCTIONAL BLOCK DIAGRAM

VCC

ADP3204

DAC
AND

FIXED

REF

VR

PHASE

SPLITTER

CURRENT

SENSE

MUX

DPSLP

DPRSLP

DPRSLP

VID

GEN

BOM

EN

CORE

VID

MUX

AND
REG

HYSTERESIS

SETTING

AND

SHIFT-MUX

CLIM

5-BIT VID

GENERAL DESCRIPTION

The ADP3204 is a 1-, 2-, or 3-phase hysteretic peak current
dc-to-dc buck converter controller dedicated to power a mobile
processor’s core. The optimized low voltage design is powered
from the 3.3 V system supply. The nominal output voltage is
set by a 5-bit VID code. To accommodate the transition time
required by the newest processors, the ADP3204 features
high speed operation to allow a minimized inductor size that
results in the fastest change of current to the output. To
further allow for the minimum number of output capacitors
to be used, the ADP3204 features active voltage positioning
with ADOPT

optimal compensation to ensure a superior
load transient response. The output signals interface with a
maximum of three ADP3415 MOSFET drivers that are
optimized for high speed and high efficiency for driving both the
top and bottom MOSFETs of the buck converter. The
ADP3204 is capable of controlling the synchronous rectifiers to
extend battery lifetime in light load conditions.

ADOPT is a trademark of Analog Devices, Inc.

*Protected by U.S.Patent No. 5,969,657; other patents pending.

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

DPSLP

DPRSLP

BOM

BOM

DPSLP

DPRSLP

PWRGD

SD

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2002

VID TRANSIENT
DETECTOR AND

SHIFT SELECTOR

PWRGD BLANKER

ENABLE UVLO-MAIN BIAS

PM MODULE

GND

VR

COREGD MONITOR

SS-HICCUP TIMER

AND OCP

SR CONTROL

OVP AND RVP

COREFB

SS

DRVLSD

CLAMP

ADP3204–SPECIFICATIONS

100 k, C

OUT1

= C

OUT2

= C

=10 pF, CSS = 0.047 F, R

OUT3

PWRGD

(0°C ⱕ TA ⱕ 100°C, High (H) = VCC, Low (L) = 0 V, VCC = 3.3 V, SD = H, V
V

DAC (VDACOUT

= 680  to 1.2 V, R

), V

REG

= V

= V

CS–

CLAMP

= 1.25 V, C

VID

= 5.1 k to VCC, HYSSET, BSHIFT, DSHIFT, and

DACRAMP

= 100 pF, R

OUT1

= R

OUT2

COREFB

= R

OUT3

=

=

1

DPRSHIFT are open, BOM = H, DPSLP = H, DPRLP = L, unless otherwise noted.) Current sunk by a pin has a positive sign, sourced by a pin has a
negative sign. Negative sign is disregarded for min and max values.

Parameter Symbol Conditions Min Typ Max Unit

SUPPLY-UVLO-SHUTDOWN

Normal Supply Current I
UVLO Supply Current I
Shutdown Supply Current I

CC

CCUVLO

CCSD

SD = L, 3.0 V ≤ VCC ≤ 3.6 V 70 ␮A

711 mA

425 ␮A

UVLO Threshold SD = H

VCC ramping up, VSS = 0 V 2.95 V
VCC ramping down, 2.60 V
V

floating

SS

55 mV

UVLO Hysteresis V

V

CCH

V

CCL

CCHYS

Shutdown Threshold

(CMOS Input) V

SDTH

VCC/2 V

POWER GOOD

Core Feedback Threshold Voltage V

Power Good Output Voltage V

(Open-Drain Output) V

Masking Time

2

COREFBH

PWRGD

t

PWRGDMSK

3

0.9 V < V
V
V
V
V
V

ramping up 1.12 V

COREFB

ramping down 1.10 V

COREFB

ramping up 0.88 V

COREFB

ramping down 0.86 V

COREFB

= V

COREFB

= 0.8 V

COREFB

< 1.675 V

DAC

DACOUT

DACOUT

1.14 V

1.12 V

0.90 V

0.88 V
V

CC

DAC

DAC

DAC

DAC

0.95 V

DAC

DAC

DAC

DAC

CC

0 0.8 V

100 ␮s

V
V
V
V
V

SOFT START/HICCUP TIMER

Charge/Discharge Current I

Soft Start Enable/Hiccup V

SS

SSEN

Termination Threshold V

Soft Start Termination/Hiccup V

SSTERM

VSS = 0 V –55 ␮A
V

= 0.5 V 1.2 ␮A

SS

V

= 1.25 V,

REG

= V

RAMP

V

ramping down 200 300 mV

SS

V

= V

RAMP

COREFB

COREFB

= 1.27 V

= 1.27 V

Enable Threshold VSS ramping up 1.70 2.00 2.25 V

VID DAC

VID Input Threshold V

VID0..4

VCC/2 V

(CMOS Inputs)

VID Input Current I

VID0..4

VID0 to VID4 = L 85 ␮A

(Internal Active Pull-Up)

Output Voltage V
Accuracy ⌬V

Settling Time t

DACRAMP Inner Resistance

5

DACS

R

DAC

DAC/VDAC

4

DACRAMP

See VID Code, Table 1 0.600 1.750 V

1.750 V ≥ V

0.825 V ≥ V
C

DACRAMP

C

DACRAMP

≥ 0.850 V –1.0 +1.0 %

DAC

≥ 0.600 V –8.5 +8.5 mV

DAC

= 100 pF 3.5 ␮s
= 1 nF 25 ␮s

10 k⍀

REV. 0–2–

ADP3204

Parameter Symbol Conditions Min Typ Max Unit

CORE COMPARATOR

Input Offset Voltage (Ramp-Reg) V
Input Bias Current I
Output Voltage V
(OUT1, OUT2, and OUT3) V
Propagation Delay Time t

Rise and Fall Time t
(OUT1, OUT2, and OUT3) t
Noise Blanking Time t

COREOS

, I

REG

RAMP

OUT_H

OUT_L

RMPOUT_PD

7

OUT_R

7

OUT_F

BLNK

CURRENT LIMIT COMPARATOR

Input Offset Voltage V
Input Bias Current I
Propagation Delay Time t

CLIMOS

, I

CS+

CLPD

6

CS–

CURRENT SENSE

MULTIPLEXER
Trans-Resistance R

R
R

, MUX switch is ON 150 ⍀

CS1–CS+

, MUX switch is OFF 50 M⍀

CS2–CS+

CS3–CS+

Common-Mode Voltage Range V

HYSTERESIS SETTING

Hysteresis Current I

–I

Hysteresis Reference Voltage V

,V

RAMP_H

CS+_H

HYSSET

CURRENT LIMIT SETTING

Hysteresis Current I

CS–

V

= 1.25 V ± 1.5 mV

REG

V

REG

= V

= 1.25 V ±1 ␮A

RAMP

VCC = 3.0 V 2.5 3.0 V
VCC = 3.6 V 0 0.4 V

6

TA = 25°C35ns
T

= Full Range 45 ns

A

7ns

7ns
OUT L-H Transition 70 ns
OUT H-L Transition 130 ns

VCS– = 1.25 V ± 1mV
V

= 1.25 V –3 ␮A

CS+

TA = 25° C55ns
TA = Full Range 65 ns

= V

= V

CS2

= 1.25 V

= 1.23 V

= 10 ␮A–8–10 –12 ␮A
= 100 ␮A –85 –100 –115 ␮A

= 1.27 V

= 10 ␮A81012 ␮A
= 100 ␮A85100 115 ␮A

= 1.23 V

= V

= V

CS–

= 1.23 V

= 10 ␮A –27 –31.5 –36 ␮A
= 100 ␮A –270 –301.5 –333 ␮A

= 1.27 V

= 10 ␮A –18 –21.5 –25 ␮A
= 100 ␮A –180 –201.5 –223 ␮A

= 1.23 V, BOM = L

V

V

V
V
V

V

V

CS1

REG

RAMP

I

HYSSET

I

HYSSET

RAMP

I

HYSSET

I

HYSSET

RAMP

REG

CS+

I

HYSSET

I

HYSSET

CS+

I

HYSSET

I

HYSSET

CS+

CS3

COREFB

= 1.25 V

02V

V

DAC

V

REV. 0

–3–

ADP3204

Parameter Symbol Conditions Min Typ Max Unit

SHIFT SETTING

Battery-Shift Current I

Battery-Shift Reference Voltage V

RAMPB

BSHIFT

, I

CS+BVVID

= 1.25 V –92.5 –100 –107.5 mA

= –100 µA, BOM = L

I

BSHIFT

DPSLP = H

V

DAC

V

Deep Sleep-Shift Current I

RAMPD

, I

CS+DVVID

= 1.25 V –92.5 –100 –107.5 mA

I

= –100 µA, BOM = H

DSHIFT

DPSLP = L

Deep Sleep-Shift Reference V

DSHIFT

V

DAC

V

Voltage

Deeper Sleep-Shift Current I

REGDPR

I

COREFBDPR

8

I

DPRSHIFT

V
I

DPRSHIFT

= –100 µA, DPRSLP = H –90 –100 –110 µA

= 1.25 V, 110 130 150 µA

VID

= –100 µA,

DPRSLP = H

Deeper Sleep-Shift Reference V

DPRSHIFT

V

DAC

V

Voltage

SHIFT CONTROL INPUTS

BOM Threshold V

BOM

VCC/2 V

(CMOS Input)

DPSLP Threshold V

(CMOS Input)

DPRSLP Mode Threshold

8

DSLP

V

DPRSLP

VCC/2 V

VCC/2 V

(CMOS Input)

LOW SIDE DRIVE CONTROL

Output Voltage (CMOS Output) V

Output Current I

DRVLSD

DRVLSD

DPRSLP = H 0 0.4 V
DPRSLP = L 0.7 V
DPRSLP = H, V
DPRSLP = L, V

= 1.5 V +0.4 mA

DRVLSD

= 1.5 V –0.4 mA

DRVLSD

CC

V

CC

V

OVER/REVERSE VOLTAGE

PROTECTION CORE FEEDBACK
Overvoltage Threshold V
Reverse-Voltage Threshold V
Output Current I

COREFB, OVP

COREFB, RVP

CLAMP

(Open-Drain Output) V

NOTES

1

All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.

2

Two test conditions: 1) PWRGD is OK but forced to fail by applying an out-of-the-Core Good-window voltage (V

COREFB pin right after the moment that BOM or DPRSLP is asserted/de-asserted. PWRGD should not fail immediately only with the specified blanking delay
time. 2) PWRGD is forced to fail (V
that BOM or DPRSLP is asserted/de-asserted. PWRGD should not go high immediately only with the specified blanking delay time.

3

Guaranteed by design

4

Measured from 50% of VID code transition amplitude to the point where V

5

Measured between DACRAMP and DACOUT pins.

6

40 mVpp amplitude impulse with 20 mV overdrive. Measured from the input threshold intercept point to 50% of the output voltage swing.

7

Measured between the 30% and 70% points of the output voltage swing.

8

DPRSLP circuit meets the minimum 30 ns DPRSLPVR signal assertion requirement; guaranteed by design.

9

COREFB pin has a resistor divider to GND whose resistance is 41.3 k⍀ (typ), guaranteed by design.

COREFB, BAD

= 1.0 V at V

9

V

COREFB

9

V

COREFB

V

= 1.25 V setting) but gets into the Core Good-window (V

VID

= 2.2 V, V

COREFB

= V

COREFB

settles within ± 1% of its steady state value.

DACOUT

DAC

, V

= 1.5 V 10 µA

CLAMP

= 1.5 V 2 6 mA

CLAMP

COREFB, BAD

= 1.0 V at V

COREFB, GOOD

2.0 V
–0.3 V

= 1.25 V setting) to the

VID

= 1.25 V) right after the moment

REV. 0–4–

ADP3204

ABSOLUTE MAXIMUM RATINGS*

Input Supply Voltage (VCC) . . . . . . . . . . . . . . . –0.3 V to +7 V

All Other Inputs/Outputs . . . . . . . . . . . . –0.3 V to V

+ 0.3 V

CC

Junction Temperature Range . . . . . . . . . . . . . . 0°C to +150°C

ORDERING GUIDE

Temperature Package Package Quantity

Model Range Description Option per Reel

ADP3204JCP-REEL 0ºC to 100ºC LFCSP-32 CP-32 5000
ADP3204JCP-REEL7 0ºC to 100ºC LFCSP-32 CP-32 1500

Table I. VID CODE

VID4 VID3 VID2 VID1 VID0 VOUT

000001.750

000011.700

000101.650

000111.600

001001.550

001011.500

001101.450

001111.400

010001.350

010011.300

010101.250

010111.200

011001.150

011011.100

011101.050

011111.000

100000.975

100010.950

100100.925

100110.900

101000.875

101010.850

101100.825

101110.800

110000.775

110010.750

110100.725

110110.700

111000.675

111010.650

111100.625

111110.600

Junction to Air Thermal Resistance (θJA) . . . . . . . . . . . 98°C/W

Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C

*This is a stress rating only; operation beyond these limits can cause the device to

be permanently damaged.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADP3204 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

REV. 0

–5–