Analog Devices ADP3203 Datasheet

2-Phase IMVP-II and IMVP-III

a

FEATURES
Pin Selectable 1- or 2-Phase Operation
Static and Dynamic Current Sharing Characteristics
Backward Compatible to IMVP-II
Superior Load Transient Response with ADOPT

Optimal Positioning Technology
Noise Blanking for Speed and Stability
Synchronous Rectifier Control Extends Battery Life
Smooth Output Transition During VID Code Change
Cycle-by-Cycle Current Limiting
Hiccup or Latched Overload Protection
Transient Glitch-Free Power Good
Soft Start Eliminates Power-On In-Rush Current Surge
2-Level Overvoltage and Reverse Voltage Protection

APPLICATIONS
IMVP-II and IMVP-III Core DC-to-DC Converters
Fixed Voltage Mobile CPU Core DC-to-DC Converters
Notebook/Laptop Power Supplies
Programmable Output Power Supplies

GENERAL DESCRIPTION

The ADP3203 is a 1- or 2-phase hysteretic peak current dc-to-dc
buck converter controller dedicated to power a mobile
processor’s core. The optimized low voltage design is powered
from the 3.3 V system supply and draws only 10 µA maximum
in shutdown. The nominal output voltage is set by a 5-bit VID
code. To accommodate the transition time required by the
newest processors for on-the-fly VID changes, the ADP3203
features high speed operation to allow a minimized inductor size
that results in the fastest change of current to the output. To
further allow for the minimum number of output capacitors to
be used, the ADP3203 features active voltage positioning with
ADOPT optimal compensation to ensure a superior load transient
response. The output signal interfaces with the ADP3415
MOSFET driver that is optimized for high speed and high effi­ciency for driving both the top and bottom MOSFETs of the buck
converter. The ADP3203 is capable of controlling the synchronous
rectifier to extend battery lifetime in light load conditions.

TM

Core Controller for Mobile CPUs

ADP3203

FUNCTIONAL BLOCK DIAGRAM

VCC

SD

ADP3203

EN

CORE

DSLP

BOM

ENABLE _UVLO MAIN BIAS

PWRGD BLANKER

VID MUX AND

SHIFT

SELECTOR

HYSTERESIS

SETTING

AND

SHIFT-MUX

PHASE

SPLITTER

CLIM

CURRENT

SENSE

MUX

5-BIT VID

DAC
AND

FIXED

REF

VR

SR CONTROL

COREGD MONITOR

SS-HICCUP TIMER AND OCP

OVP AND RVP

PM MODULE

GND

VR

OUT2

OUT1

CS2

CS1

CS+

CS–

RAMP

REG

DACOUT

DRVLSD

COREFB

SS

CLAMP

HYSSET

DSHIFT

BSHIFT

VID4

VID3

VID2

VID1

VID0

PWRGD

DPRSLP

DSLP

BOM

ADOPT is a trademark of Analog Devices.

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]www.analog.com
Fax: [phone] © Analog Devices, Inc., 2002

ADP3203–SPECIFICATIONS

100 k⍀, C

OUT1

= C

= 10 pF, CSS =0.047 ␮F, R

OUT2

= 680 ⍀ to 1.2 V, R

PWRGD

(0ⴗC ⱕ TA ⱕ 100ⴗC, High (H) = VCC, Low (L) = 0 V, VCC = 3.3 V, SD = H, V
V

DAC

(0 V

DACOUT

), V

= V

= V

REG

CS–

= 5.1 k⍀ to VCC; HYSSET, BSHIFT, DSHIFT, and

CLAMP

= 1.25 V, R

VID

OUT1

=R

OUT2

COREFB

=

1

DPRSHIFT are open; BOM = H, DSLP = H, DPRSLP = L, unless otherwise noted.) Current sunk by a pin has a positive sign, sourced by a pin has a
negative sign. Negative sign is disregarded for min and max values.

Parameter Symbol Conditions Min Typ Max Unit

SUPPLY-UVLO-SHUTDOWN

Normal Supply Current I
UVLO Supply Current I
Shutdown Supply Current I

CC

CCUVLO

CCSD

VCC = 2.63 V 75 ␮A
SD = L, 3.0 V ≤ VCC ≤ 3.6 V 10 ␮A

79 mA

UVLO Threshold SD = H

UVLO Hysteresis V

V

CCH

V

CCL

CCHYS

VCC Ramping Up, VSS= 0 V 2.95 V
VCC Ramping Down, 2.65 V
V

Floating

SS

50 mV

Shutdown Threshold

(CMOS Input) V

SDTH

VCC/2 V

POWER GOOD

Core Feedback Threshold Voltage V

Power Good Output Voltage V

COREFBH

PWRGD

(Open-Drain Output) V

Masking Time t

PWRGDMSK

3

0.9 V < V
V
V
V
V
V

Ramping Up 1.12 V

COREFB

Ramping Down 1.10 V

COREFB

Ramping Up 0.88 V

COREFB

Ramping Down 0.86 V

COREFB

= V

COREFB

= 0.8 V

COREFB

< 1.675 V

DAC

DACOUT

DACOUT

1.14 V

1.12 V

0.90 V

0.88 V
V

CC

DAC

DAC

DAC

DAC

0.95 V

DAC

DAC

DAC

DAC

CC

0 0.8 V

100 ␮s

V
V
V
V
V

SOFT START/HICCUP TIMER

Charge/Discharge Current I

SS

Soft Start Enable/Hiccup V

Termination Threshold V

V

SSENDWN

SSENUP

SSTERM

4

V

Soft Start Termination/Hiccup V

VSS = 0 V –16 ␮A
V

= 0.5 V 0.5 ␮A

SS

= 1.25 V,

REG

= V

RAMP

V

Ramping Down 80 200 mV

SS

COREFB

= 1.27 V

VSS Ramping Up 150 mV
V

RAMP

= V

COREFB

= 1.27 V

Enable Threshold VSS Ramping Up 1.75 2.00 2.25 V

VID DAC

VID Input Threshold

(CMOS Inputs) V

VID Input Current I

VID0..4

VID0..4

VID0 to VID4 = L 85 ␮A

VCC/2 V

(Internal Active Pull-Up)
Output Voltage V
Accuracy ∆V

Settling Time t

DACS

DAC

DAC/VDAC

5

See VID Code, Table I 0.600 1.750 V
0°C ≤ TA ≤ 85°C

1.75 ≥ V

0.825 ≥ V
∆V

DAC

≥ 0.850 –0.85 +0.85 %

DAC

≥ 0.600 –7.2 +7.2 mV

DAC

= 0.5 V, C

= 10 nF 3.5 ␮s

DAC

REV. 0–2–

ADP3203

Parameter Symbol Conditions Min Typ Max Unit

CORE COMPARATOR

Input Offset Voltage (Ramp-Reg) V
Input Bias Current I
Output Voltage V

COREOS

, I

REG

OUT_H

RAMP

(OUT1, OUT2) 3.0

V

Propagation Delay Time t

Rise and Fall Time

2

Noise Blanking Time t

OUT_L

RMPOUT_PD

7

t

OUT_R

7

t

OUT_F

BLNK

CURRENT LIMIT

COMPARATOR

Input Offset Voltage V
Input Bias Current I
Propagation Delay Time t

CLIMOS

, I

CS+

CLiMPD

CS–

6

CURRENT SENSE

MULTIPLEXER

Transresistance R

R
R

Common-Mode Voltage Range4V

,Switch Is ON 150 Ω

CS1–CS+

,Switch Is OFF 50 MΩ

CS2–CS+

CS3–CS+

= V

CS1

CS2

HYSTERESIS SETTING

Hysteresis Current I

–I

Hysteresis Reference Voltage V

,V

RAMP_H

CSP_H

HYSSET

CURRENT LIMIT SETTING

Hysteresis Current I

CS–

V

= 1.25 V ± 1mV

REG

V

REG

= V

= 1.25 V ± 1 ␮A

RAMP

VCC = 3.0 V 2.5 V

VCC = 3.6 V 0 0.4 V

6

TA = 25°C35ns
T

= Full Range 40 ns

A

710 ns

710 ns
OUT L-H Transition 130 ns
OUT H-L Transition 180 ns

V

= 1.25 V ± 1mV

CS–

V

= 1.25 V –3 ␮A

CS+

TA = 25° C60ns
TA = Full Range 100 ns

02V

= 1.25 V

REG

V

= 1.23 V, BOM = H

RAMP

I

= –10 ␮A–8–10 –12 ␮A

HYSSET

= –100 ␮A –85 –100 –115 ␮A

I

HYSSET

V

= 1.27 V, BOM = H

RAMP

I

= –10 ␮A81012 ␮A

HYSSET

= –100 ␮A85100 115 ␮A

I

HYSSET

V

= 1.23 V, BOM = L

RAMP

I

= –10 ␮A –6.4 –8 –9.6 ␮A

HYSSET

= –100 ␮A –68 –80 –92 ␮A

I

HYSSET

V

= 1.27 V, BOM = L

RAMP

I

= –10 ␮A 6.4 8 9.6 ␮A

HYSSET

= –100 ␮A688092␮A

I

HYSSET

1.65 1.7 1.75 V

V

= 1.23 V

RAMP

V

= V

REG

V

CS+

I

HYSSET

I

HYSSET

V

CS+

I

HYSSET

I

HYSSET

V

CS+

I

HYSSET

I

HYSSET

V

CS+

I

HYSSET

I

HYSSET

= V

CS–

= 1.23 V BOM = H

= –10 ␮A –27 –31.5 –36 ␮A
= –100 ␮A –270 –301.5 –333 ␮A

= 1.27 V, BOM = H

= –10 ␮A –18 –21.5 –25 ␮A
= –100 ␮A –180 –201.5 –223 ␮A

= 1.23 V, BOM = L

= –10 ␮A –21 –25.5 –30 ␮A
= –100 ␮A –226 –241.5 –267 ␮A

= 1.27 V, BOM = L

= –10 ␮A –14 –17.5 –21 ␮A
= –100 ␮A –144 –161.5 –179 ␮A

COREFB

= 1.25 V

REV. 0

–3–

ADP3203

Parameter Symbol Conditions Min Typ Max Unit

SHIFT SETTING

Battery Shift Current I

Battery Shift Reference Voltage V

RAMPB

BSHIFT

, I

CS+BVVID

= 1.25 V –92.5 –100 –107.5 mA

= –100 µA, BOM = L

I

BSHIFT

DSLP = H

V

DAC

V

Deep Sleep Shift Current I

Deep Sleep Shift Reference Voltage V

SHIFT CONTROL INPUTS

BOM Threshold V

(CMOS Input)
DSLP Threshold V
(V

-Level CMOS Input)

TT

DPRSLP Mode Threshold

8

(CMOS Input)

LOW SIDE DRIVE CONTROL

Output Voltage (CMOS Output) V

Output Current I

OVER/REVERSE VOLTAGE

PROTECTION-CORE FEEDBACK
Overvoltage Threshold V
Reverse Voltage Threshold V
Output Voltage

(Open-Drain Output) V
Output Current I

, I

RAMPD

CS+DVVID

I

DSHIFT

DSLP = L

DSHIFT

BOM

DSLP

V

DPRSLP

DRVLSD

DPRSLP = H 0 0.4 V
DPRSLP = L 0.7 V

DRVLSD

DPRSLP = H, V
DPRSLP = L, V

COREFB,OVPVCOREFB

COREFB,OVPVCOREFB

CLAMP

CLAMP

V

COREFB

V

COREFB

= 1.25 V –92.5 –100 –107.5 mA

= –100 µA, BOM = H

V

DAC

V

VCC/2 V

0.9 V

VCC/2 V

= 1.5 V 0.4 mA

DRVLSD

= 1.5 V –0.4 mA

DRVLSD

CC

V

CC

V

Rising 2.0 V
Falling –0.3 V

= 2.2 V, V
= V

DAC

, V

0.7 V

= 5 V 10 µA

CLAMP

= 5 V 2 4 mA

CLAMP

CC

V

CC

V

NOTES

1

All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.

2

Guaranteed by characterization.

3

Two test conditions: 1)PWRGD is OK but forced to fail by applying an out-of-the-Core-Good-window voltage (V

COREFB pin right after the moment that BOM or DPRSLP is asserted/deasserted. PWRGD should not fail immediately, only with the specified blanking delay
time. 2) PWRGD is forced to fail (V
(V

COREFB, GOOD

blanking delay time.

4

Guaranteed by design.

5

Measured from 50% of VID code transition amplitude to the point where V

6

40 mVp-p amplitude impulse with 20 mV overdrive. Measured from the input threshold intercept point to 50% of the output voltage swing.

7

Measured between the 30% and 70% points of the output voltage swing.

8

DPRSLP circuit meets the minimum 30 ns DPRSLPVR signal assertion requirement; guaranteed by design.

= 1.25 V) right after the moment that BOM or DPRSLP is asserted/deasserted. PWRGD should not go high immediately, only with the specified

COREFB, BAD

= 1.0 V at V

= 1.25 V setting) but gets into the Core Good window

VID

settles within ± 1% of its steady state value.

DACOUT

COREFB,BAD

= 1.0 V at V

= 1.25 V setting) to the

VID

REV. 0–4–

ADP3203

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

Input Supply Voltage (VCC) . . . . . . . . . . . . . . –0.3 V to +7 V

All Other Inputs/Outputs . . . . . . . . . . . –0.3 V to VCC + 0.3 V

Operating Ambient Temperature Range . . . . . . 0°C to 100°C

Junction Temperature Range . . . . . . . . . . . . . . . 0°C to 150°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98°C/W

␪

JA

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . 300°C

*This is a stress rating only; operation beyond these limits can cause the device to

be permanently damaged.

ORDERING GUIDE

Temperature Package Package

Model Range Description Option

ADP3203JRU-0.85-RL 0.85 V 0ºC to 100ºC TSSOP-28

ADP3203JRU-0.85-R7 0.85 V 0ºC to 100ºC TSSOP-28

ADP3203JRU-1.0-RL 1 V 0ºC to 100ºC TSSOP-28

ADP3203JRU-1.0-RL7 1 V 0ºC to 100ºC TSSOP-28

Table I. VID Code

VID4 VID3 VID2 VID1 VID0 VOUT

000001.750

000011.700

000101.650

000111.600

001001.550

001011.500

001101.450

001111.400

010001.350

010011.300

010101.250

010111.200

011001.150

011011.100

011101.050

011111.000

100000.975

100010.950

100100.925

100110.900

101000.875

101010.850

101100.825

101110.800

110000.775

110010.750

110100.725

110110.700

111000.675

111010.650

111100.625

111110.600

PIN CONFIGURATION

HYSSET

DSHIFT

BSHIFT

VID4

VID3

VID2

VID1

VID0

BOM

DPSLP

DPRSLP

PWRGD

CLAMP

SD

1

2

3

4

5

ADP3203

6

TOP VIEW

(Not to Scale)

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

CS–

CS+

REG

RAMP

VCC

CS2

CS1

OUT2

OUT1

GND

DACOUT

COREFB

SS

DRVLSD

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although the

ADP3203 features proprietary ESD protection circuitry, permanent damage may occur on devices

subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended

to avoid performance degradation or loss of functionality.

REV. 0

–5–