Analog Devices ADP3192A Service Manual

8-Bit Programmable 2- to 4-Phase

V

FEATURES

Selectable 2-, 3-, or 4-phase operation at up to

1 MHz per phase

±7.7 mV worst-case differential sensing error over

temperature

Logic-level PWM outputs for interface to external high

power drivers

Fast enhanced PWM (FEPWM) flex mode for excellent load

transient performance
Active current balancing between all output phases
Built-in power-good/crowbar blanking supports on-the-fly

VID code changes
Digitally programmable 0.5 V to 1.6 V output supports both

VR10.x and VR11 specifications
Programmable short-circuit protection with programmable

latch-off delay

APPLICATIONS

Desktop PC power supplies for next generation

Intel® processors

VRM modules

Synchronous Buck Controller

ADP3192A

FUNCTIONAL BLOCK DIAGRAM

CC RAMPADJRT

31 12 13

SHUNT

GND

PWRGD

TTSENSE

VRHOT

VRFAN

ILIMIT

DELAY

IREF

COMP

FBRTN

VIDSEL

REGULATOR

UVLO

SHUTDOWN

18

–

850mV

1

EN

2

10

9

8

11

7

20

5

3

40

+

DAC

+ 150mV

CSREF

+

–

DAC

– 350mV

DELAY

THERMAL

THROTTLING

CONTROL

PRECISION

REFERENCE

32

VID7

VID633VID534VID435VID336VID237VID138VID0

–

+

OSCILLATOR

VID DAC

+

CMP

–

+

CMP

–

CIRCUIT

CURRENT BALANCING

CURRENT

MEASUREMENT

AND LIMIT

–
+

Figure 1.

+

CMP

–

+

CMP

–

CROWBAR

+

–

SOFT START

CONTROL

39

ENSET

RESET

RESET

RESET

2/3/4-PHASE

DRIVER L OGIC

RESET

CURRENT
LIMIT

+

–

BOOT

VOLTAGE

AND

ADP3192A

19

30

29

28

27

25

24

23

22

17

15

16

21

4

14

6

OD

PWM1

PWM2

PWM3

PWM4

SW1

SW2

SW3

SW4

CSCOMP

CSREF

CSSUM

IMON

FB

LLSET

SS

06786-001

GENERAL DESCRIPTION

The ADP3192A1 is a highly efficient, multiphase, synchronous
buck-switching regulator controller optimized for converting a
12 V main supply into the core supply voltage required by high
performance Intel processors. It uses an internal 8-bit DAC to read
a voltage identification (VID) code directly from the processor,
which is used to set the output voltage between 0.5 V and 1.6 V.

This device uses a multimode PWM architecture to drive the
logic-level outputs at a programmable switching frequency that
can be optimized for VR size and efficiency. The phase relation­ship of the output signals can be programmed to provide 2-, 3-,
or 4-phase operation, allowing for the construction of up to
four complementary buck-switching stages.

1

Protected by U.S. Patent Number 6,683,441; other patents pending.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

The ADP3192A also includes programmable no load offset and
slope functions to adjust the output voltage as a function of the
load current, optimally positioning it for a system transient. In
addition, the ADP3192A provides accurate and reliable short­circuit protection, adjustable current limiting, and a delayed
power-good output that accommodates on-the-fly output
voltage changes requested by the CPU.

The ADP3192A has a built-in shunt regulator that allows the part
to be connected to the 12 V system supply through a series resistor.

The ADP3192A is specified over the extended commercial
temperature range of 0°C to 85°C and is available in a
40-lead LFCSP.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2007 Analog Devices, Inc. All rights reserved.

ADP3192A

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Test Circuits....................................................................................... 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 9

Theory of Operation ...................................................................... 10

Start-Up Sequence...................................................................... 10

Phase Detection Sequence......................................................... 10

Master Clock Frequency............................................................ 11

Output Voltage Differential Sensing ........................................ 11

Output Current Sensing ............................................................ 11

Active Impedance Control Mode............................................. 11

Current Control Mode and Thermal Balance ........................11

Voltage Control Mode................................................................ 12

Current Reference ......................................................................12

Fast Enhanced PWM Mode...................................................... 12

Delay Timer................................................................................. 12

Soft Start ...................................................................................... 12

Current-Limit, Short-Circuit, and Latch-Off Protection...... 13

Dynamic VID.............................................................................. 13

Power-Good Monitoring........................................................... 14

Output Crowbar......................................................................... 14

Output Enable and UVLO........................................................ 14

Thermal Monitoring.................................................................. 14

Application Information................................................................ 19

Setting the Clock Frequency..................................................... 19

Soft Start Delay Time................................................................. 19

Current-Limit Latch-Off Delay Times.................................... 19

Inductor Selection...................................................................... 19

Current Sense Amplifier............................................................ 20

Inductor DCR Temperature Correction ................................. 21

Output Offset.............................................................................. 22

C

Selection ............................................................................. 22

OUT

Power MOSFETs......................................................................... 23

Ramp Resistor Selection............................................................ 24

COMP Pin Ramp ....................................................................... 25

Current-Limit Setpoint.............................................................. 25

Feedback Loop Compensation Design.................................... 25

CIN Selection and Input Current di/dt Reduction.................. 27

Thermal Monitor Design .......................................................... 27

Shunt Resistor Design................................................................ 28

Tuning the ADP3192A .............................................................. 28

Layout and Component Placement ......................................... 30

Outline Dimensions....................................................................... 31

Ordering Guide .......................................................................... 31

REVISION HISTORY

5/07—Revision 0: Initial Version

Rev. 0 | Page 2 of 32

ADP3192A

SPECIFICATIONS

VCC = 5 V, FBRTN = GND, TA = 0°C to 85°C, unless otherwise noted.

Table 1.

Parameter Symbol Conditions Min Typ Max Unit

REFERENCE CURRENT

Reference Bias Voltage V
Reference Bias Current I

1.5 V

IREF

R

IREF

= 100 kΩ 14.25 15 15.75 μA

IREF

ERROR AMPLIFIER

Output Voltage Range
Accuracy VFB

2

V

0 4.4 V

COMP

Relative to nominal DAC output, referenced
to FBRTN, LLSET = CSREF (see

V

In startup 1.092 1.1 1.108 V

FB(BOOT)

Load Line Positioning Accuracy CSREF − LLSET = 80 mV −78 −80 −82 mV
Differential Nonlinearity −1 +1 LSB
Input Bias Current IFB I
FBRTN Current I
Output Current I
Gain Bandwidth Product GBW

65 200 μA

FBRTN

COMP

(ERR)

= I

FB

FB forced to V

COMP = FB 20 MHz
Slew Rate COMP = FB 25 V/μs
LLSET Input Voltage Range V
LLSET Input Bias Current I
Boot Voltage Hold Time t

Relative to CSREF −250 +250 mV

LLSET

−10 +10 nA

LLSET

C

BOOT

DELAY

VID INPUTS

Input Low Voltage V
Input High Voltage V
Input Current I
VID Transition Delay Time
No CPU Detection Turn-Off Delay Time

2

2

VID(X), VIDSEL 0.4 V

IL(VID)

VID(X), VIDSEL 0.8 V

IH(VID)

−1 μA

IN(VID)

VID code change to FB change 400 ns
VID code change to PWM going low 5 μs

OSCILLATOR

Frequency Range
Frequency Variation f
T
T
Output Voltage VRT R
RAMPADJ Output Voltage V
RAMPADJ Input Current Range I

2

f

0.25 4 MHz

OSC

T

PHASE

RAMPADJ

RAMPADJ

= 25°C, RT = 205 kΩ, 4-phase 180 200 220 kHz

A

= 25°C, RT = 118 kΩ, 4-phase 400 kHz

A

= 25°C, RT = 55 kΩ, 4-phase 800 kHz

A

= 205 kΩ to GND 1.9 2.0 2.1 V

T

RAMPADJ − FB −50 +50 mV

1 50 μA

CURRENT SENSE AMPLIFIER

Offset Voltage V
Input Bias Current I
Gain Bandwidth Product GBW
Slew Rate C

CSSUM − CSREF (see Figure 3) −1.0 +1.0 mV

OS(CSA)

BIAS(CSSUM)

−10 +10 nA

CSSUM = CSCOMP 10 MHz

(CSA)

CSCOMP

Input Common-Mode Range CSSUM and CSREF 0 3.5 V
Output Voltage Range 0.05 3.5 V
Output Current I
Current Limit Latch-Off Delay Time t

500 μA

CSCOMP

C

OC(DELAY)

DELAY

IMON Output IMON 10 × (CSREF − CSCOMP) > 50 mV −6 +6 %

CURRENT BALANCE AMPLIFIER

Common-Mode Range V
Input Resistance R
Input Current I
Input Current Matching

SW(X)CM

SW(X)

SW(X)

ΔI

SW(X)

−600 +200 mV
SW(X) = 0 V 10 17 26 kΩ
SW(X) = 0 V 8 12 20 μA
SW(X) = 0 V −4 +4 %

CURRENT-LIMIT COMPARATOR

ILIMIT Bias Current I

I

ILIMIT

= 2/3 × I

ILIMIT

Rev. 0 | Page 3 of 32

1

−7.7 +7.7 mV

Figure 2)

13.5 15 16.5 μA

IREF

– 3% 500 μA

OUT

= 10 nF 2 ms

= 10 pF 10 V/μs

= 10 nF 8 ms

9 10 11 μA

IREF

ADP3192A

Symbol Conditions Min Typ Max Unit Parameter

ILIMIT Voltage V

ILIMIT

Maximum Output Voltage 3 V
Current-Limit Threshold Voltage VCL V
Current-Limit Setting Ratio VCL/V

DELAY TIMER

Normal Mode Output Current I
Output Current in Current Limit I
Threshold Voltage V

DELAY

DELAY(CL)

DELAY(TH)

SOFT START

Output Current ISS During startup, ISS = I

ENABLE INPUT

Threshold Voltage V
Hysteresis V
Input Current I
Delay Time t

OD OUTPUT

Output Low Voltage V

Output High Voltage V

OD Pull-Down Resistor

TH(EN)

HYS(EN)

IN(EN)

DELAY(EN)

OL(OD)

OH(OD)

60 kΩ

THERMAL THROTTLING CONTROL

TTSENSE Voltage Range Internally limited 0 5 V
TTSENSE Bias Current −133 −123 −113 μA
TTSENSE VRFAN Threshold Voltage 1.06 1.105 1.15 V
TTSENSE VRHOT Threshold Voltage 765 810 855 mV
TTSENSE Hysteresis 50 mV
VRFAN Output Low Voltage V
VRHOT Output Low Voltage V

OL(VRFAN)

OL(VRHOT)

POWER-GOOD COMPARATOR

Undervoltage Threshold V
Overvoltage Threshold V
Output Low Voltage V

PWRGD(UV)

PWRGD(OV)

OL(PWRGD)

Power-Good Delay Time

During Soft Start

2

C
VID Code Changing 100 250 μs
VID Code Static 200 ns

Crowbar Trip Point V

CROWBAR

Crowbar Reset Point Relative to FBRTN 320 375 430 mV
Crowbar Delay Time t

CROWBAR

VID Code Changing 100 250 μs
VID Code Static 400 ns

PWM OUTPUTS

Output Low Voltage V
Output High Voltage V

OL(PWM)

OH(PWM)

SUPPLY V

2

VCC
DC Supply Current I

VCC 4.65 5 5.55 V

VCC

UVLO Turn-On Current 6.5 11 mA
UVLO Threshold Voltage V

UVLO

UVLO Turn-Off Voltage VCC falling 4.1 V

1

All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).

2

Guaranteed by design or bench characterization, not tested in production.

R

ILIMIT

CSREF

I

DELAY

I

DELAY(CL)

= 121 kΩ (V

− V

CSCOMP

82.6 mV/V

ILIMIT

= I

12 15 18 μA

IREF

= 0.25 × I

= (I

× R

ILIMIT

ILIMIT

, R

= 121 kΩ 80 100 125 mV

ILIMIT

3.0 3.75 4.5 μA

IREF

)) 1.09 1.21 1.33 V

ILIMIT

1.6 1.7 1.8 V

12 15 18 μA

IREF

800 850 900 mV

80 100 125 mV

−1 μA
EN > 950 mV, C

= 10 nF 2 ms

DELAY

160 500 mV

4 5 V

I

I

= −4 mA 150 300 mV

VRFAN(SINK)

VRHOT(SINK)

= −4 mA 150 300 mV

Relative to nominal DAC output −400 −350 −300 mV
Relative to nominal DAC output 100 150 200 mV
I

PWRGD(SINK)

= −4 mA 150 300 mV

= 10 nF 2 ms

DELAY

Relative to nominal DAC output 100 150 200 mV

Overvoltage to PWM going low

I

I

= −400 μA 160 500 mV

PWM(SINK)

PWM(SOURCE)

SYSTEM

V

SYSTEM

= 400 μA 4.0 5 V

= 12 V, R

= 13.2 V, R

= 340 Ω (see Figure 2)

SHUNT

= 340 Ω 25 mA

SHUNT

VCC rising 9 V

Rev. 0 | Page 4 of 32

ADP3192A

TEST CIRCUITS

12V

12V

ADP3192A

10nF

NC = NO CONNECT

8-BIT CODE

40

VCC

VID4

VID5

VID6

VID7

PWM1
PWM2
PWM3
PWM4

CSSUM

CSCOMP

GNDODIREF

100kΩ

20kΩ

1kΩ

1.25V

10nF

1

EN
PWRGD
FBRTN
FB
COMP
SS
DELAY
VRFAN
VRHOT
TTSENSE

250kΩ

VID0

VID1

VIDSEL

ADP3192A

ILIMITRTRAMPADJ

VID2

LLSET

VID3

CSREF

100nF

Figure 2. Closed-Loop Output Voltage Accuracy

12V

ADP3192A

680Ω 680Ω

VCC

31

+

SW1
SW2
SW3
SW4

680Ω680Ω

1µF

100nF

NC

NC

680Ω 680Ω

10kΩ

ΔV

1V

VCC

31

COMP

5

FB

4

LLSET

14

15

18

= FBΔV = 80mV – FBΔV = 0mV

ΔV

FB

–

CSREF

+

GND

VID

DAC

06786-004

Figure 4. Positioning Voltage

06786-002

CSCOMP

17

39kΩ

1kΩ

1V

100nF

CSSUM

16

CSREF

15

GND

18

VOS =

CSCOMP – 1V

Figure 3. Current Sense Amplifier V

40

06786-003

OS

Rev. 0 | Page 5 of 32

ADP3192A

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

VCC −0.3 V to +6 V
FBRTN −0.3 V to +0.3 V
PWM3 to PWM4, RAMPADJ −0.3 V to VCC + 0.3 V
SW1 to SW4 −5 V to +25 V

<200 ns −10 V to +25 V
All Other Inputs and Outputs −0.3 V to VCC + 0.3 V
Storage Temperature Range −65°C to +150°C
Operating Ambient Temperature Range 0°C to 85°C
Operating Junction Temperature 125°C
Thermal Impedance (θJA) 39°C/W
Lead Temperature

Soldering (10 sec) 300°C

Infrared (15 sec) 260°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Absolute maximum ratings apply individually only, not in
combination. Unless otherwise specified, all other voltages
referenced to GND.

ESD CAUTION

Rev. 0 | Page 6 of 32

ADP3192A

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

ID2

VID139VID040VIDSEL

38

PIN 1

1EN

INDICATOR

2PWRGD
3FBRTN
4FB
5COMP
6SS
7DELAY
8VRFAN
9VRHOT

10TTSENSE

NOTES

1. NC = NO CONNECT .

2. THE EXPO SED EPAD ON BOT TOM SI DE OF PACKAGE IS AN
ELECTRICAL CONNECTIO N AND SHOULD BE SOLDERED TO G ROUND.

ADP3192A

TOP VIEW

(Not to Scale)

11

12RT13

ILIMIT

RAMPADJ

Figure 5. Pin Configuration

VID634VID535VID436VID337V

VID731VCC

33

32

30 PWM1
29 PWM2
28 PWM3
27 PWM4
26 NC
25 SW1
24 SW2
23 SW3
22 SW4
21 IMON

15

17

16

18

14

LLSET

19OD20

ND
G

CSREF

IREF

CSSUM

CSCOMP

06786-005

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

1 EN Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the PWRGD output low.
2 PWRGD

Power-Good Output. Open-drain output that signals when the output voltage is outside of the proper

operating range.
3 FBRTN Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage.
4 FB

Feedback Input. Error amplifier input for remote sensing of the output voltage. An external resistor between

this pin and the output voltage sets the no load offset point.
5 COMP Error Amplifier Output and Compensation Point.
6 SS

Soft Start Delay Setting Input. An external capacitor connected between this pin and GND sets the soft start

ramp-up time.
7 DELAY

Delay Timer Setting Input. An external capacitor connected between this pin and GND sets the overcurrent

latch-off delay time, boot voltage hold time, EN delay time, and PWRGD delay time.
8 VRFAN

VR Fan Activation Output. Open-drain output that signals when the temperature at the monitoring point

connected to TTSENSE exceeds the programmed VRFAN temperature threshold.
9 VRHOT

VR Hot Output. Open-drain output that signals when the temperature at the monitoring point connected to

TTSENSE exceeds the programmed VRHOT temperature threshold.
10 TTSENSE

VR Hot Thermal Throttling Sense Input. An NTC thermistor between this pin and GND is used to remotely sense

the temperature at the desired thermal monitoring point.
11 ILIMIT Current-Limit Setpoint. An external resistor from this pin to GND sets the current-limit threshold of the converter.
12 RT

Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the oscillator

frequency of the device.
13 RAMPADJ

PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal

PWM ramp.
14 LLSET

Output Load Line Programming Input. This pin can be directly connected to CSCOMP, or it can be connected to

the center point of a resistor divider between CSCOMP and CSREF. Connecting LLSET to CSREF disables positioning.
15 CSREF

Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current sense

amplifier and the power-good and crowbar functions. This pin should be connected to the common point of

the output inductors.
16 CSSUM

Current Sense Summing Node. External resistors from each switch node to this pin sum the average inductor

currents together to measure the total output current.
17 CSCOMP

Current Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determines the gain of the

current sense amplifier and the positioning loop response time.
18 GND Ground. All internal biasing and the logic output signals of the device are referenced to this ground.

Rev. 0 | Page 7 of 32

ADP3192A

Mnemonic Description Pin No.

19

20 IREF

21 IMON Analog Output. Represents the total load current.
22 to 25 SW4 to SW1

26 NC No Connection.
27 to 30 PWM4 to PWM1

31 VCC

32 to 39 VID7 to VID0

40 VIDSEL

OD Output Disable Logic Output. This pin is actively pulled low when the EN input is low or when VCC is below its

UVLO threshold to signal to the driver IC that the driver high-side and low-side outputs should go low.

, I

Current Reference Input. An external resistor from this pin to ground sets the reference current for I
I

ILIMIT

, and I

TTSENSE

.

, ISS,

FB

DELAY

Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused phases
should be left open.

Logic-Level PWM Outputs. Each output is connected to the input of an external MOSFET driver such as the

ADP3120A. Connecting the PWM4 and PWM3 outputs to VCC causes that phase to turn off, allowing the

ADP3192A to operate as a 2-, 3-, or 4-phase controller.
Supply Voltage for the Device. A 340 Ω resistor should be placed between the 12 V system supply and the VCC

pin. The internal shunt regulator maintains VCC = 5 V.
Voltage Identification DAC Inputs. These eight pins are pulled down to GND, providing a Logic 0 if left open. When

in normal operation mode, the DAC output programs the FB regulation voltage from 0.5 V to 1.6 V (see

Table 4).

VID DAC Selection Pin. The logic state of this pin determines whether the internal VID DAC decodes VID0 to
VID7 as extended VR10 or VR11 inputs.

Rev. 0 | Page 8 of 32

ADP3192A

TYPICAL PERFORMANCE CHARACTERISTICS

7000

6000

5000

4000

3000

FREQUENCY (kHz)

2000

1000

MASTER CLOCK

PHASE 1
IN 4 PHASE DESIGN

0

13

20 30 43 68 75 82 130 180 270 395 430 680 850

RT (kΩ)

06786-018

Figure 6. Master Clock Frequency vs. RT

Rev. 0 | Page 9 of 32

ADP3192A

THEORY OF OPERATION

The ADP3192A combines a multimode, fixed frequency,
PWM control with multiphase logic outputs for use in 2-, 3-,
and 4-phase synchronous buck CPU core supply power
converters. The internal VID DAC is designed to interface
with the Intel 8-bit VRD/VRM 11-compatible CPU and 7-bit
VRD/VRM 10×-compatible CPU. Multiphase operation is
important for producing the high currents and low voltages
demanded by today’s microprocessors. Handling the high
currents in a single-phase converter places high thermal
demands on the components in the system, such as the
inductors and MOSFETs.

The multimode control of the ADP3192A ensures a stable,
high performance topology for the following:

• Balancing currents and thermals between phases

• High speed response at the lowest possible switching

frequency and output decoupling

• Minimizing thermal switching losses by using lower

frequency operation

• Tight load line regulation and accuracy

• High current output due to 4-phase operation

• Reduced output ripple due to multiphase cancellation

• PC board layout noise immunity

• Ease of use and design due to independent component

selection

• Flexibility in operation for tailoring design to low cost or

high performance

START-UP SEQUENCE

The ADP3192A follows the VR11 start-up sequence shown in
Figure 7. After both the EN and UVLO conditions are met,
the DELAY pin goes through one cycle (TD1). The first four
clock cycles of TD2 are blanked from the PWM outputs and
used for phase detection as explained in the
Sequence

section. Then, the soft start ramp is enabled (TD2),
and the output comes up to the boot voltage of 1.1 V. The boot
hold time is determined by the DELAY pin as it goes through a
second cycle (TD3). During TD3, the processor VID pins settle
to the required VID code. When TD3 is over, the ADP3192A
soft starts either up or down to the final VID voltage (TD4).
After TD4 is complete and the PWRGD masking time (equal to
VID on-the-fly masking) is complete, a third ramp on the
DELAY pin sets the PWRGD blanking (TD5).

Phase Detection

(ADP3192A EN)

(ADP3192A PWRGD)

PHASE DETECTION SEQUENCE

During startup, the number of operational phases and their
phase relationship is determined by the internal circuitry that
monitors the PWM outputs. Normally, the ADP3192A operates
as a 4-phase PWM controller. Connecting the PWM4 pin to
VCC programs 3-phase operation and connecting the PWM4
and PWM3 pins to VCC programs 2-phase operation.

Prior to soft start, while EN is low, the PWM3 and PWM4 pins
sink approximately 100 µA. An internal comparator checks each
pin’s voltage vs. a threshold of 3 V. If the pin is tied to VCC, it is
above the threshold. Otherwise, an internal current sink pulls
the pin to GND, which is below the threshold. PWM1 and
PWM2 are low during the phase detection interval that occurs
during the first four clock cycles of TD2. After this time, if the
remaining PWM outputs are not pulled to VCC, the 100 µA
current sink is removed, and they function as normal PWM
outputs. If they are pulled to VCC, the 100 µA current source is
removed, and the outputs are put into a high impedance state.

The PWM outputs are logic-level devices intended for driving
external gate drivers such as the
phase is monitored independently, operation approaching 100%
duty cycle is possible. In addition, more than one output can be
on at the same time to allow overlapping phases.

SUPPLY

VTT I/O

DELAY

VCC_CORE

VR READY

CPU

VID INPUTS

5V

SS

UVLO
THRESHOLD

0.85V

V

DELAY(TH)

(1.7V)

1V

TD1

TD2

50µs

VID INVALID VID VALID

Figure 7. System Start-Up Sequence

ADP3120A. Because each

V

BOOT

(1.1V)

TD3

V

BOOT

(1.1V)

V

VID

V

VID

TD4

TD5

06786-006

Rev. 0 | Page 10 of 32