Analog Devices ADP3168 b Datasheet

6-Bit, Programmable 2-, 3-, 4-Phase

FEATURES

Selectable 2-, 3-, or 4-phase operation at up to

1 MHz per phase

±10 mV worst-case differential sensing error over

temperature

Logic-level PWM outputs for interface to

external high power drivers
Active current balancing between all output phases
Built-in Power Good/crowbar blanking supports
On-the-fly VID code changes
6-bit digitally programmable 0.8375 V to 1.6 V output
Programmable short-circuit protection with

programmable latch-off delay

APPLICATIONS

Desktop PC power supplies for:

Next generation Intel® processors

VRM modules

GENERAL DESCRIPTION

The ADP3168 is a highly efficient, multiphase, synchronous
buck switching regulator controller optimized for converting a
12 V main supply into the core supply voltage required by high
performance Intel processors. It uses an internal 6-bit DAC to
read a voltage identification (VID) code directly from the
processor, which is used to set the output voltage between

0.8375 V and 1.6 V, and uses a multimode PWM architecture to
drive the logic-level outputs at a programmable switching
frequency that can be optimized for VR size and efficiency. The
phase relationship of the output signals can be programmed to
provide 2-, 3-, or 4-phase operation, allowing for the construc­tion of up to four complementary buck switching stages.

The ADP3168 also includes programmable no-load offset and
slope functions to adjust the output voltage as a function of the
load current so that it is always optimally positioned for a
system transient. The ADP3168 also provides accurate and
reliable short-circuit protection, adjustable current limiting, and
a delayed Power Good output that accommodates on-the-fly
output voltage changes requested by the CPU.

Synchronous Buck Controller

ADP3168

FUNCTIONAL BLOCK DIAGRAM

VCC RTRAMPADJ

GND

PWRGD

ILIMIT

DELAY

COMP

EN

11

19

+150mV

CSREF

DAC
–250mV

10

15

EN

12

9

28 1314

UVLO

SHUTDOWN

AND BIAS

DAC

DELAY

SOFT-

START

PRECISION

REFERENCE

OSCILLATOR

CURRENT-

BALANCING

1234 657

VID4 VID3 VID2 VID1 VID5VID0FBRTN

CIRCUIT

CURRENT-

CIRCUIT

Figure 1.

LIMIT

VID

DAC

CMP

CMP

RESET

RESET

CMP

2-, 3-, 4-PHASE
DRIVER LOGIC

RESET

RESET

CMP

CROWBAR

CURRENT

ADP3168

ENSET

LIMIT

27

PWM1

26

PWM2

25

PWM3

24

PWM4

23

SW1

22

SW2

21

SW3

20

SW4

17

CSSUM

16

CSREF

18

CSCOMP

8

FB

03258-001

The device is specified over the commercial temperature range
of 0°C to 85°C and is available in a 28-lead TSSOP package.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

www.analog.com

ADP3168

TABLE OF CONTENTS

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Typical Performance Characteristics and Test Circuits............... 7

Theory of Operation ........................................................................ 9

Number of Phases......................................................................... 9

Master Clock Frequency .............................................................. 9

Output Voltage Differential Sensing .......................................... 9

Output Current Sensing .............................................................. 9

Active Impedance Control Mode............................................. 10

Current-Control Mode and Thermal Balance........................ 10

Volt a ge Cont r ol Mo d e................................................................ 10

Soft Start ......................................................................................10

Current-Limit, Short-Circuit, and Latch-Off Protection...... 11

Soft Start and Current Limit Latch-Off Delay Times............ 13

Inductor Selection...................................................................... 13

Designing an Inductor............................................................... 15

Selecting a Standard Inductor................................................... 15

Output Droop Resistance.......................................................... 15

Inductor DCR Temperature Correction ................................. 16

Output Offset .............................................................................. 16

C

Selection ............................................................................. 17

OUT

Power MOSFETs......................................................................... 18

Ramp Resistor Selection............................................................ 19

COMP Pin Ramp ....................................................................... 19

Current-Limit Set Point............................................................. 19

Feedback Loop Compensation Design.................................... 19

C

Selection and Input Current di/dt Reduction.................. 21

IN

Tuning Procedure for the ADP3168........................................ 21

Dynamic VID..............................................................................12

Power-Good Monitoring........................................................... 12

Output Crowbar .........................................................................12

Output Enable and UVLO ........................................................ 12

Application Information................................................................ 13

Setting the Clock Frequency ..................................................... 13

REVISION HISTORY

11/04—Rev. A to Rev. B

Changes to Specifications................................................................ 3

Updated Outline Dimensions....................................................... 24

Changes to Ordering Guide.......................................................... 24

4/03—Data Sheet Changed from Rev. 0 to Rev. A.

Changes to Specifications................................................................ 2

Layout and Component Placement.............................................. 23

General Recommendations....................................................... 23

Power Circuitry .......................................................................... 23

Signal Circuitry........................................................................... 23

Outline Dimensions ....................................................................... 24

Ordering Guide .......................................................................... 24

Rev. B | Page 2 of 24

ADP3168

SPECIFICATIONS

All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). VCC = 12 V,
FBRTN = GND, T

Table 1.

Parameter Symbol Conditions Min Typ Max Unit

ERROR AMPLIFIER

Output Voltage Range V
Accuracy VFB Relative to nominal DAC output, −10 +10 mV
Referenced to FBRTN,
CSSUM = CSCOMP; see Figure 10
Line Regulation ∆VFB VCC = 10 V to 14 V 0.05 %
Input Bias Current IFB 14 15.5 17 µA
FBRTN Current I
Output Current I
Gain Bandwidth Product GBW
Slew Rate C

VID INPUTS

Input Low Voltage V
Input High Voltage V
Input Current, Input Voltage Low I
Input Current, Input Voltage High I
Pull-Up Resistance R
Internal Pull-Up Voltage 0.825 1.00 V
VID Transition Delay Time1 VID code change to FB change 400 ns
No CPU Detection Turn-Off VID code change to 11111 to 400 ns

Delay Time PWM going low

OSCILLATOR

Frequency Range1 f
Frequency Variation f
T
T
Output Voltage VRT RT = 100 kΩ to GND 1.9 2.0 2.1 V
RAMPADJ Output Voltage V
RAMPADJ Input Current Range I

CURRENT SENSE AMPLIFIER

Offset Voltage V
Input Bias Current I
Gain Bandwidth Product GBW
Slew Rate C
Input Common-Mode Range CSSUM and CSREF 0 3 V
Positioning Accuracy ∆V
Output Voltage Range I
Output Current I

CURRENT-BALANCE CIRCUIT

Common-Mode Range V
Input Resistance R
Input Current I
Input Current Matching ∆I

1

Guaranteed by design, not tested in production.

= 0°C to 85°C, unless otherwise noted.

A

0.5 3.5 V

COMP

90 120 µA

FBRTN

FB forced to V

O(ERR)

COMP = FB 20 MHz

(ERR)

IL(VID)

0.8 V

IH(VID)

VID(X) = 0 V −20 −30 µA

IL(VID)

VID(X) = 1.25 V 15 25 µA

IH(VID)

35 60 115 kΩ

VID

0.25 4 MHz

OSC

TA = 25°C, RT = 250 kΩ, 4-phase 155 200 245 kHz

PHASE

RAMPADJ − FB −50 +50 mV

RAMPADJ

0 100 µA

RAMPADJ

CSSUM − CSREF; see Figure 5 −1.5 +1.5 mV

OS(CSA)

−50 +50 nA

BIAS(CSA)

(CSA)

FB

500 µA

CSCOMP

−600 +200 mV

SW(X)CM

SW(X)

SW(X) = 0 V 4 7 10 µA

SW(X)

SW(X) = 0 V −5 +5 %

SW(X)

− 3% 500 µA

OUT

= 10 pF 25 V/µs

COMP

0.4 V

= 25°C, RT = 115 kΩ, 4-phase 400 kHz

A

= 25°C, RT = 75 kΩ, 4-phase 600 kHz

A

10 MHz

= 10 pF 10 V/µs

CSCOMP

See Figure 6 −77 −80 −83 mV

= ±100 µA 0.05 3.3 V

CSCOMP

SW(X) = 0 V 20 30 40 kΩ

Rev. B | Page 3 of 24

ADP3168

Parameter Symbol Conditions Min Typ Max Unit

CURRENT-LIMIT COMPARATOR

ILIMIT Output Voltage

Normal Mode V

Shutdown Mode V
Output Current, Normal Mode I
Current-Limit Threshold Voltage VCL V
Current-Limit Setting Ratio VCL/I
DELAY Normal Mode Voltage V
DELAY Overcurrent Threshold V
Latch-Off Delay Time t
SOFT START
Output Current, Soft-Start Mode I
Soft-Start Delay Time t

VID code = 011111
ENABLE INPUT

Input Low Voltage V
Input High Voltage V
Input Current, Input Voltage Low I
Input Current, Input Voltage High I

POWER-GOOD COMPARATOR

Undervoltage Threshold V
Overvoltage Threshold V
Output Low Voltage V
Power-Good Delay Time

VID Code Changing 100 250 µs

VID Code Static 200 ns
Crowbar Trip Point V
Crowbar Reset Point Relative to FBRTN 450 550 650 mV
Crowbar Delay Time t

VID Code Changing 100 250 µs

VID Code Static 400 ns

PWM OUTPUTS

Output Voltage Low V
Output Voltage High V

SUPPLY

DC Supply Current 5 8 mA
UVLO Threshold Voltage V
UVLO Hysteresis 0.7 0.9 1.1 V

EN > 1.7 V, R

ILIMIT(NM)

EN > 0.8 V, I

ILIMIT(SD)

EN > 1.7 V, R

ILIMIT(NM)

− V

CSREF

10.4 mV/µA

ILIMIT

2.9 3 3.1 V

DELAY(NM)

1.7 1.8 1.9 V

DELAY(OC)

R

DELAY

During startup, DELAY < 2.8 V 15 20 25 µA

DELAY(SS)

R

DELAY(SS)

IL(EN)

0.8 V

IH(EN)

EN = 0 V −1 +1 µA

IL(EN)

EN = 1.25 V 10 25 µA

IH(EN)

Relative to nominal DAC output −200 −250 −325 mV

PWRGD(UV)

Relative to nominal DAC output 90 150 200 mV

PWRGD(OV)

I

OL(PWRGD)

Relative to nominal DAC output 90 150 200 mV

CROWBAR

Overvoltage to PWM going low

CROWBAR

I

OL(PWM)

I

OH(PWM)

VCC rising 6.5 6.9 7.3 V

UVLO

= 250 kΩ, C

DELAY

= 250 kΩ, C

DELAY

0.4 V

PWRGD(SINK)

= 400 µA 160 500 mV

PWM(SINK)

PWM(SOURCE)

= 250 kΩ 2.9 3 3.1 V

ILIMIT

= −100 µA 400 mV

ILIMIT

= 250 kΩ 12 µA

ILIMIT

, R

CSCOMP

= 250 kΩ 105 125 145 mV

ILIMIT

= 4.7 nF 600 µs

DELAY

= 4.7 nF 350 µs

DELAY

= 4 mA 225 400 mV

= 400 µA 4.0 5.0 V

Rev. B | Page 4 of 24

ADP3168

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

VCC −0.3 V to +15 V

FBRTN −0.3 V to +0.3 V

VID0 to VID5, EN, DELAY, ILIMIT,

CSCOMP, RT, PWM1 to PWM4, COMP

SW1-SW4 −5 V to +25 V

All Other Inputs and Outputs −0.3 V to VCC + 0.3 V

Operating Ambient Temperature

Range

Operating Junction Temperature 125°C

Storage Temperature Range −65°C to +150°C

Junction to Air Thermal Resistance (θJA) 100°C/W

Lead Temperature (Soldering, 10 sec) 300°C

Vapor Phase (60 sec) 215°C

Infrared (15 sec) 220°C

−0.3 V to +5.5 V

0°C to 85°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. Absolute maximum ratings apply individually
only, not in combination. Unless otherwise specified, all other
voltages are referenced to GND.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on

the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. B | Page 5 of 24

ADP3168

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VID4
VID3
VID2
VID1
VID0
VID5

FBRTN

COMP

PWRGD

DELAY

RAMPADJ

128

2
3

ADP3168

4
5

6
7

TOP VIEW

8

FB

(Not to Scale)

9
10
11

EN

12

13

RT

14

27

26
25
24

23
22
21
20

19

18
17
16

15

VCC
PWM1
PWM2
PWM3
PWM4
SW1
SW2
SW3
SW4
GND
CSCOMP
CSSUM
CSREF
ILIMIT

03258-B-002

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Function

1 to 6 VID4 to VID0, VID5

Voltage Identification DAC Inputs. These six pins are pulled up to an internal reference, providing a Logic 1
if left open. When in normal operation mode, the DAC output programs the FB regulation voltage from

0.8375 V to 1.6 V. Leaving VID4 through VID0 open results in the ADP3168 going into a no CPU mode,

shutting off its PWM outputs.
7 FBRTN Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage.
8 FB

Feedback Input. Error amplifier input for remote sensing of the output voltage. An external resistor

between this pin and the output voltage sets the no -load offset point.
9 COMP Error Amplifier Output and Compensation Point.
10 PWRGD

Power Good Output. Open-drain output that pulls to GND when the output voltage is outside the proper

operating range.
11 EN Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs.
12 DELAY

Soft-Start Delay and Current Limit Latch-Off Delay Setting Input. An external resistor and capacitor

connected between this pin and GND set the soft-start ramp-up time and the overcurrent latch-off delay

time.
13 RT

Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the

oscillator frequency of the device.
14 RAMPADJ

PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal

PWM ramp.
15 ILIMIT

Current Limit Set Point/Enable Output. An external resistor from this pin to GND sets the current limit

threshold of the converter. This pin is actively pulled low when the ADP3168 EN input is low or when VCC

is below its UVLO threshold to signal to the driver IC that the driver high-side and low-side outputs should

go low.
16 CSREF

Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current-

sense amplifier and the Power Good and crowbar functions. This pin should be connected to the common

point of the output inductors.
17 CSSUM

Current-Sense Summing Node. External resistors from each switch node to this pin sum the average

inductor currents to measure the total output current.
18 CSCOMP

Current Sense Compensation Point. A resistor and a capacitor from this pin to CSSUM determine the slope

of the load line and the positioning loop response time.
19 GND Ground. All internal biasing and the logic output signals of the device are referenced to this ground.
20 to 23 SW4 to SW1

Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused

phases should be left open.
24 to 27 PWM4 to PWM1

Logic-Level PWM Outputs. Each output is connected to the input of an external MOSFET driver, such as the

ADP3413 or ADP3418. Connecting the PWM3 and/or PWM4 outputs to GND causes that phase to turn off,

allowing the ADP3168 to operate as a 2-, 3 -, or 4 -phase controller.
28 VCC Supply Voltage for the Device.

Rev. B | Page 6 of 24

ADP3168

TYPICAL PERFORMANCE CHARACTERISTICS AND TEST CIRCUITS

4.0

3.5

3.0

2.5

2.0

1.5

1.0

MASTER CLOCK FREQUENCY (MHz)

0.5
SEE EQUATION 1 FOR FREQUENCIES NOT ON THIS GRAPH

0

100 1500 50 200 250 300

VALUE (kΩ)

R

T

03258-B-003

Figure 3. Master Clock Frequency vs. RT

5.3
TA = 25°C
4-PHASE OPERATION

5.2

5.1

5.0

4.9

4.8

SUPPLY CURRENT (mA)

4.7

4.6

MASTER CLOCK FREQUENCY (MHz)

2.01.50.5 1.00 2.5 3.0 3.5 4.0

Figure 4. Supply Current vs. Master Clock Frequency

03258-B-004

ADP3168

100nF

28

VCC

CSCOMP

18

CSSUM

17

CSREF

16

19

GND

VOS =

CSCOMP – 1V

12V

39kΩ

1kΩ

1.0V

Figure 5. Test Circuit 1, Current Sense Amplifier V

ADP3168

28

VCC

8

FB

9

COMP

CSCOMP

18

CSSUM

17

CSREF

16

GND

19

200kΩ

∆V

1.0V

12V

10kΩ

200kΩ

100nF

ADP3168

1

VID4

2

VID3

3

1kΩ

VID2

4

VID1

5

VID0

6

VID5

7

FBRTN

8

FB

9

COMP

10

PWRGD

11

EN

12

DELAY

13

RT

14

RAMPADJ

6-BIT CODE

40

03258-B-005

OS

4.7nF

1.25V

250kΩ

VCC

PWM1

PWM2

PWM3

PWM4

SW1

SW2

SW3

SW4

GND

CSCOMP

CSSUM

CSREF

ILIMIT

28

27

26

25

24

23

22

21

20

19

18

17

16

15

250kΩ

+

1µF

20kΩ

100nF

100nF

12V

03258-B-007

Figure 7. Test Circuit 3, Closed-Loop Output Voltage Accuracy

∆VFB = FB∆V= 80mV – FB∆V = 0mV

03258-B-006

Figure 6. Test Circuit, Positioning Voltage

Rev. B | Page 7 of 24

ADP3168

Table 4. Output Voltage vs. VID Code (X = Don’t Care)

VID4 VID3 VID2 VID1 VID0 VID5 V

OUT(NOM)

1 1 1 1 1 X No CPU
0 1 0 1 0 0 0.8375 V
0 1 0 0 0 0 0.850 V
0 1 0 0 1 0 0.8625 V
0 1 0 0 0 1 0.875 V
0 1 0 0 0 0 0.8875 V
0 0 1 1 1 1 0.900 V
0 0 1 1 1 0 0.9125 V
0 0 1 1 0 1 0.925 V
0 0 1 1 0 0 0.9375 V
0 0 1 0 1 1 0.950 V
0 0 1 0 1 0 0.9625 V
0 0 1 0 0 1 0.975 V
0 0 1 0 0 0 0.9875 V
0 0 0 1 1 1 1.000 V
0 0 0 1 1 0 1.0125 V
0 0 0 1 0 1 1.025 V
0 0 0 1 0 0 1.0375 V
0 0 0 0 1 1 1.050 V
0 0 0 0 1 0 1.0625 V
0 0 0 0 0 1 1.075 V
0 0 0 0 0 0 1.0875 V
1 1 1 1 0 1 1.100 V
1 1 1 1 0 0 1.1125 V
1 1 1 0 1 1 1.125 V
1 1 1 0 1 0 1.1375 V
1 1 1 0 0 1 1.150 V
1 1 1 0 0 0 1.1625 V
1 1 0 1 1 1 1.175 V
1 1 0 1 1 0 1.1875 V
1 1 0 1 0 1 1.200 V
1 1 0 1 0 0 1.2125 V

VID4 VID3 VID2 VID1 VID0 VID5 V

OUT(NOM)

1 1 0 0 1 1 1.225 V
1 1 0 0 1 0 1.2375 V
1 1 0 0 0 1 1.250 V
1 1 0 0 0 0 1.2625 V
1 0 1 1 1 1 1.275 V
1 0 1 1 1 0 1.2875 V
1 0 1 1 0 1 1.300 V
1 0 1 1 0 0 1.3125 V
1 0 1 0 1 1 1.325 V
1 0 1 0 1 0 1.3375 V
1 0 1 0 0 1 1.350 V
1 0 1 0 0 0 1.3625 V
1 0 0 1 1 1 1.375 V
1 0 0 1 1 0 1.3875 V
1 0 0 1 0 1 1.400 V
1 0 0 1 0 0 1.4125 V
1 0 0 0 1 1 1.425 V
1 0 0 0 1 0 1.4375 V
1 0 0 0 0 1 1.450 V
1 0 0 0 0 0 1.4625 V
0 1 1 1 1 1 1.475 V
0 1 1 1 1 0 1.4875 V
0 1 1 1 0 1 1.500 V
0 1 1 1 0 0 1.5125 V
0 1 1 0 1 1 1.525 V
0 1 1 0 1 0 1.5375 V
0 1 1 0 0 1 1.550 V
0 1 1 0 0 0 1.5625 V
0 1 0 1 1 1 1.575 V
0 1 0 1 1 0 1.5875 V
0 1 0 1 0 1 1.600 V

Rev. B | Page 8 of 24