Analog Devices ADP3168 b Datasheet

6-Bit, Programmable 2-, 3-, 4-Phase

FEATURES

Selectable 2-, 3-, or 4-phase operation at up to

1 MHz per phase

±10 mV worst-case differential sensing error over

temperature

Logic-level PWM outputs for interface to

external high power drivers
Active current balancing between all output phases
Built-in Power Good/crowbar blanking supports
On-the-fly VID code changes
6-bit digitally programmable 0.8375 V to 1.6 V output
Programmable short-circuit protection with

programmable latch-off delay

APPLICATIONS

Desktop PC power supplies for:

Next generation Intel® processors

VRM modules

GENERAL DESCRIPTION

The ADP3168 is a highly efficient, multiphase, synchronous
buck switching regulator controller optimized for converting a
12 V main supply into the core supply voltage required by high
performance Intel processors. It uses an internal 6-bit DAC to
read a voltage identification (VID) code directly from the
processor, which is used to set the output voltage between

0.8375 V and 1.6 V, and uses a multimode PWM architecture to
drive the logic-level outputs at a programmable switching
frequency that can be optimized for VR size and efficiency. The
phase relationship of the output signals can be programmed to
provide 2-, 3-, or 4-phase operation, allowing for the construc­tion of up to four complementary buck switching stages.

The ADP3168 also includes programmable no-load offset and
slope functions to adjust the output voltage as a function of the
load current so that it is always optimally positioned for a
system transient. The ADP3168 also provides accurate and
reliable short-circuit protection, adjustable current limiting, and
a delayed Power Good output that accommodates on-the-fly
output voltage changes requested by the CPU.

Synchronous Buck Controller

ADP3168

FUNCTIONAL BLOCK DIAGRAM

VCC RTRAMPADJ

GND

PWRGD

ILIMIT

DELAY

COMP

EN

11

19

+150mV

CSREF

DAC
–250mV

10

15

EN

12

9

28 1314

UVLO

SHUTDOWN

AND BIAS

DAC

DELAY

SOFT-

START

PRECISION

REFERENCE

OSCILLATOR

CURRENT-

BALANCING

1234 657

VID4 VID3 VID2 VID1 VID5VID0FBRTN

CIRCUIT

CURRENT-

CIRCUIT

Figure 1.

LIMIT

VID

DAC

CMP

CMP

RESET

RESET

CMP

2-, 3-, 4-PHASE
DRIVER LOGIC

RESET

RESET

CMP

CROWBAR

CURRENT

ADP3168

ENSET

LIMIT

27

PWM1

26

PWM2

25

PWM3

24

PWM4

23

SW1

22

SW2

21

SW3

20

SW4

17

CSSUM

16

CSREF

18

CSCOMP

8

FB

03258-001

The device is specified over the commercial temperature range
of 0°C to 85°C and is available in a 28-lead TSSOP package.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

www.analog.com

ADP3168

TABLE OF CONTENTS

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Typical Performance Characteristics and Test Circuits............... 7

Theory of Operation ........................................................................ 9

Number of Phases......................................................................... 9

Master Clock Frequency .............................................................. 9

Output Voltage Differential Sensing .......................................... 9

Output Current Sensing .............................................................. 9

Active Impedance Control Mode............................................. 10

Current-Control Mode and Thermal Balance........................ 10

Volt a ge Cont r ol Mo d e................................................................ 10

Soft Start ......................................................................................10

Current-Limit, Short-Circuit, and Latch-Off Protection...... 11

Soft Start and Current Limit Latch-Off Delay Times............ 13

Inductor Selection...................................................................... 13

Designing an Inductor............................................................... 15

Selecting a Standard Inductor................................................... 15

Output Droop Resistance.......................................................... 15

Inductor DCR Temperature Correction ................................. 16

Output Offset .............................................................................. 16

C

Selection ............................................................................. 17

OUT

Power MOSFETs......................................................................... 18

Ramp Resistor Selection............................................................ 19

COMP Pin Ramp ....................................................................... 19

Current-Limit Set Point............................................................. 19

Feedback Loop Compensation Design.................................... 19

C

Selection and Input Current di/dt Reduction.................. 21

IN

Tuning Procedure for the ADP3168........................................ 21

Dynamic VID..............................................................................12

Power-Good Monitoring........................................................... 12

Output Crowbar .........................................................................12

Output Enable and UVLO ........................................................ 12

Application Information................................................................ 13

Setting the Clock Frequency ..................................................... 13

REVISION HISTORY

11/04—Rev. A to Rev. B

Changes to Specifications................................................................ 3

Updated Outline Dimensions....................................................... 24

Changes to Ordering Guide.......................................................... 24

4/03—Data Sheet Changed from Rev. 0 to Rev. A.

Changes to Specifications................................................................ 2

Layout and Component Placement.............................................. 23

General Recommendations....................................................... 23

Power Circuitry .......................................................................... 23

Signal Circuitry........................................................................... 23

Outline Dimensions ....................................................................... 24

Ordering Guide .......................................................................... 24

Rev. B | Page 2 of 24

ADP3168

SPECIFICATIONS

All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). VCC = 12 V,
FBRTN = GND, T

Table 1.

Parameter Symbol Conditions Min Typ Max Unit

ERROR AMPLIFIER

Output Voltage Range V
Accuracy VFB Relative to nominal DAC output, −10 +10 mV
Referenced to FBRTN,
CSSUM = CSCOMP; see Figure 10
Line Regulation ∆VFB VCC = 10 V to 14 V 0.05 %
Input Bias Current IFB 14 15.5 17 µA
FBRTN Current I
Output Current I
Gain Bandwidth Product GBW
Slew Rate C

VID INPUTS

Input Low Voltage V
Input High Voltage V
Input Current, Input Voltage Low I
Input Current, Input Voltage High I
Pull-Up Resistance R
Internal Pull-Up Voltage 0.825 1.00 V
VID Transition Delay Time1 VID code change to FB change 400 ns
No CPU Detection Turn-Off VID code change to 11111 to 400 ns

Delay Time PWM going low

OSCILLATOR

Frequency Range1 f
Frequency Variation f
T
T
Output Voltage VRT RT = 100 kΩ to GND 1.9 2.0 2.1 V
RAMPADJ Output Voltage V
RAMPADJ Input Current Range I

CURRENT SENSE AMPLIFIER

Offset Voltage V
Input Bias Current I
Gain Bandwidth Product GBW
Slew Rate C
Input Common-Mode Range CSSUM and CSREF 0 3 V
Positioning Accuracy ∆V
Output Voltage Range I
Output Current I

CURRENT-BALANCE CIRCUIT

Common-Mode Range V
Input Resistance R
Input Current I
Input Current Matching ∆I

1

Guaranteed by design, not tested in production.

= 0°C to 85°C, unless otherwise noted.

A

0.5 3.5 V

COMP

90 120 µA

FBRTN

FB forced to V

O(ERR)

COMP = FB 20 MHz

(ERR)

IL(VID)

0.8 V

IH(VID)

VID(X) = 0 V −20 −30 µA

IL(VID)

VID(X) = 1.25 V 15 25 µA

IH(VID)

35 60 115 kΩ

VID

0.25 4 MHz

OSC

TA = 25°C, RT = 250 kΩ, 4-phase 155 200 245 kHz

PHASE

RAMPADJ − FB −50 +50 mV

RAMPADJ

0 100 µA

RAMPADJ

CSSUM − CSREF; see Figure 5 −1.5 +1.5 mV

OS(CSA)

−50 +50 nA

BIAS(CSA)

(CSA)

FB

500 µA

CSCOMP

−600 +200 mV

SW(X)CM

SW(X)

SW(X) = 0 V 4 7 10 µA

SW(X)

SW(X) = 0 V −5 +5 %

SW(X)

− 3% 500 µA

OUT

= 10 pF 25 V/µs

COMP

0.4 V

= 25°C, RT = 115 kΩ, 4-phase 400 kHz

A

= 25°C, RT = 75 kΩ, 4-phase 600 kHz

A

10 MHz

= 10 pF 10 V/µs

CSCOMP

See Figure 6 −77 −80 −83 mV

= ±100 µA 0.05 3.3 V

CSCOMP

SW(X) = 0 V 20 30 40 kΩ

Rev. B | Page 3 of 24

ADP3168

Parameter Symbol Conditions Min Typ Max Unit

CURRENT-LIMIT COMPARATOR

ILIMIT Output Voltage

Normal Mode V

Shutdown Mode V
Output Current, Normal Mode I
Current-Limit Threshold Voltage VCL V
Current-Limit Setting Ratio VCL/I
DELAY Normal Mode Voltage V
DELAY Overcurrent Threshold V
Latch-Off Delay Time t
SOFT START
Output Current, Soft-Start Mode I
Soft-Start Delay Time t

VID code = 011111
ENABLE INPUT

Input Low Voltage V
Input High Voltage V
Input Current, Input Voltage Low I
Input Current, Input Voltage High I

POWER-GOOD COMPARATOR

Undervoltage Threshold V
Overvoltage Threshold V
Output Low Voltage V
Power-Good Delay Time

VID Code Changing 100 250 µs

VID Code Static 200 ns
Crowbar Trip Point V
Crowbar Reset Point Relative to FBRTN 450 550 650 mV
Crowbar Delay Time t

VID Code Changing 100 250 µs

VID Code Static 400 ns

PWM OUTPUTS

Output Voltage Low V
Output Voltage High V

SUPPLY

DC Supply Current 5 8 mA
UVLO Threshold Voltage V
UVLO Hysteresis 0.7 0.9 1.1 V

EN > 1.7 V, R

ILIMIT(NM)

EN > 0.8 V, I

ILIMIT(SD)

EN > 1.7 V, R

ILIMIT(NM)

− V

CSREF

10.4 mV/µA

ILIMIT

2.9 3 3.1 V

DELAY(NM)

1.7 1.8 1.9 V

DELAY(OC)

R

DELAY

During startup, DELAY < 2.8 V 15 20 25 µA

DELAY(SS)

R

DELAY(SS)

IL(EN)

0.8 V

IH(EN)

EN = 0 V −1 +1 µA

IL(EN)

EN = 1.25 V 10 25 µA

IH(EN)

Relative to nominal DAC output −200 −250 −325 mV

PWRGD(UV)

Relative to nominal DAC output 90 150 200 mV

PWRGD(OV)

I

OL(PWRGD)

Relative to nominal DAC output 90 150 200 mV

CROWBAR

Overvoltage to PWM going low

CROWBAR

I

OL(PWM)

I

OH(PWM)

VCC rising 6.5 6.9 7.3 V

UVLO

= 250 kΩ, C

DELAY

= 250 kΩ, C

DELAY

0.4 V

PWRGD(SINK)

= 400 µA 160 500 mV

PWM(SINK)

PWM(SOURCE)

= 250 kΩ 2.9 3 3.1 V

ILIMIT

= −100 µA 400 mV

ILIMIT

= 250 kΩ 12 µA

ILIMIT

, R

CSCOMP

= 250 kΩ 105 125 145 mV

ILIMIT

= 4.7 nF 600 µs

DELAY

= 4.7 nF 350 µs

DELAY

= 4 mA 225 400 mV

= 400 µA 4.0 5.0 V

Rev. B | Page 4 of 24

ADP3168

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

VCC −0.3 V to +15 V

FBRTN −0.3 V to +0.3 V

VID0 to VID5, EN, DELAY, ILIMIT,

CSCOMP, RT, PWM1 to PWM4, COMP

SW1-SW4 −5 V to +25 V

All Other Inputs and Outputs −0.3 V to VCC + 0.3 V

Operating Ambient Temperature

Range

Operating Junction Temperature 125°C

Storage Temperature Range −65°C to +150°C

Junction to Air Thermal Resistance (θJA) 100°C/W

Lead Temperature (Soldering, 10 sec) 300°C

Vapor Phase (60 sec) 215°C

Infrared (15 sec) 220°C

−0.3 V to +5.5 V

0°C to 85°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. Absolute maximum ratings apply individually
only, not in combination. Unless otherwise specified, all other
voltages are referenced to GND.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on

the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. B | Page 5 of 24

ADP3168

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VID4
VID3
VID2
VID1
VID0
VID5

FBRTN

COMP

PWRGD

DELAY

RAMPADJ

128

2
3

ADP3168

4
5

6
7

TOP VIEW

8

FB

(Not to Scale)

9
10
11

EN

12

13

RT

14

27

26
25
24

23
22
21
20

19

18
17
16

15

VCC
PWM1
PWM2
PWM3
PWM4
SW1
SW2
SW3
SW4
GND
CSCOMP
CSSUM
CSREF
ILIMIT

03258-B-002

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Function

1 to 6 VID4 to VID0, VID5

Voltage Identification DAC Inputs. These six pins are pulled up to an internal reference, providing a Logic 1
if left open. When in normal operation mode, the DAC output programs the FB regulation voltage from

0.8375 V to 1.6 V. Leaving VID4 through VID0 open results in the ADP3168 going into a no CPU mode,

shutting off its PWM outputs.
7 FBRTN Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage.
8 FB

Feedback Input. Error amplifier input for remote sensing of the output voltage. An external resistor

between this pin and the output voltage sets the no -load offset point.
9 COMP Error Amplifier Output and Compensation Point.
10 PWRGD

Power Good Output. Open-drain output that pulls to GND when the output voltage is outside the proper

operating range.
11 EN Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs.
12 DELAY

Soft-Start Delay and Current Limit Latch-Off Delay Setting Input. An external resistor and capacitor

connected between this pin and GND set the soft-start ramp-up time and the overcurrent latch-off delay

time.
13 RT

Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the

oscillator frequency of the device.
14 RAMPADJ

PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal

PWM ramp.
15 ILIMIT

Current Limit Set Point/Enable Output. An external resistor from this pin to GND sets the current limit

threshold of the converter. This pin is actively pulled low when the ADP3168 EN input is low or when VCC

is below its UVLO threshold to signal to the driver IC that the driver high-side and low-side outputs should

go low.
16 CSREF

Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current-

sense amplifier and the Power Good and crowbar functions. This pin should be connected to the common

point of the output inductors.
17 CSSUM

Current-Sense Summing Node. External resistors from each switch node to this pin sum the average

inductor currents to measure the total output current.
18 CSCOMP

Current Sense Compensation Point. A resistor and a capacitor from this pin to CSSUM determine the slope

of the load line and the positioning loop response time.
19 GND Ground. All internal biasing and the logic output signals of the device are referenced to this ground.
20 to 23 SW4 to SW1

Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused

phases should be left open.
24 to 27 PWM4 to PWM1

Logic-Level PWM Outputs. Each output is connected to the input of an external MOSFET driver, such as the

ADP3413 or ADP3418. Connecting the PWM3 and/or PWM4 outputs to GND causes that phase to turn off,

allowing the ADP3168 to operate as a 2-, 3 -, or 4 -phase controller.
28 VCC Supply Voltage for the Device.

Rev. B | Page 6 of 24

ADP3168

TYPICAL PERFORMANCE CHARACTERISTICS AND TEST CIRCUITS

4.0

3.5

3.0

2.5

2.0

1.5

1.0

MASTER CLOCK FREQUENCY (MHz)

0.5
SEE EQUATION 1 FOR FREQUENCIES NOT ON THIS GRAPH

0

100 1500 50 200 250 300

VALUE (kΩ)

R

T

03258-B-003

Figure 3. Master Clock Frequency vs. RT

5.3
TA = 25°C
4-PHASE OPERATION

5.2

5.1

5.0

4.9

4.8

SUPPLY CURRENT (mA)

4.7

4.6

MASTER CLOCK FREQUENCY (MHz)

2.01.50.5 1.00 2.5 3.0 3.5 4.0

Figure 4. Supply Current vs. Master Clock Frequency

03258-B-004

ADP3168

100nF

28

VCC

CSCOMP

18

CSSUM

17

CSREF

16

19

GND

VOS =

CSCOMP – 1V

12V

39kΩ

1kΩ

1.0V

Figure 5. Test Circuit 1, Current Sense Amplifier V

ADP3168

28

VCC

8

FB

9

COMP

CSCOMP

18

CSSUM

17

CSREF

16

GND

19

200kΩ

∆V

1.0V

12V

10kΩ

200kΩ

100nF

ADP3168

1

VID4

2

VID3

3

1kΩ

VID2

4

VID1

5

VID0

6

VID5

7

FBRTN

8

FB

9

COMP

10

PWRGD

11

EN

12

DELAY

13

RT

14

RAMPADJ

6-BIT CODE

40

03258-B-005

OS

4.7nF

1.25V

250kΩ

VCC

PWM1

PWM2

PWM3

PWM4

SW1

SW2

SW3

SW4

GND

CSCOMP

CSSUM

CSREF

ILIMIT

28

27

26

25

24

23

22

21

20

19

18

17

16

15

250kΩ

+

1µF

20kΩ

100nF

100nF

12V

03258-B-007

Figure 7. Test Circuit 3, Closed-Loop Output Voltage Accuracy

∆VFB = FB∆V= 80mV – FB∆V = 0mV

03258-B-006

Figure 6. Test Circuit, Positioning Voltage

Rev. B | Page 7 of 24

ADP3168

Table 4. Output Voltage vs. VID Code (X = Don’t Care)

VID4 VID3 VID2 VID1 VID0 VID5 V

OUT(NOM)

1 1 1 1 1 X No CPU
0 1 0 1 0 0 0.8375 V
0 1 0 0 0 0 0.850 V
0 1 0 0 1 0 0.8625 V
0 1 0 0 0 1 0.875 V
0 1 0 0 0 0 0.8875 V
0 0 1 1 1 1 0.900 V
0 0 1 1 1 0 0.9125 V
0 0 1 1 0 1 0.925 V
0 0 1 1 0 0 0.9375 V
0 0 1 0 1 1 0.950 V
0 0 1 0 1 0 0.9625 V
0 0 1 0 0 1 0.975 V
0 0 1 0 0 0 0.9875 V
0 0 0 1 1 1 1.000 V
0 0 0 1 1 0 1.0125 V
0 0 0 1 0 1 1.025 V
0 0 0 1 0 0 1.0375 V
0 0 0 0 1 1 1.050 V
0 0 0 0 1 0 1.0625 V
0 0 0 0 0 1 1.075 V
0 0 0 0 0 0 1.0875 V
1 1 1 1 0 1 1.100 V
1 1 1 1 0 0 1.1125 V
1 1 1 0 1 1 1.125 V
1 1 1 0 1 0 1.1375 V
1 1 1 0 0 1 1.150 V
1 1 1 0 0 0 1.1625 V
1 1 0 1 1 1 1.175 V
1 1 0 1 1 0 1.1875 V
1 1 0 1 0 1 1.200 V
1 1 0 1 0 0 1.2125 V

VID4 VID3 VID2 VID1 VID0 VID5 V

OUT(NOM)

1 1 0 0 1 1 1.225 V
1 1 0 0 1 0 1.2375 V
1 1 0 0 0 1 1.250 V
1 1 0 0 0 0 1.2625 V
1 0 1 1 1 1 1.275 V
1 0 1 1 1 0 1.2875 V
1 0 1 1 0 1 1.300 V
1 0 1 1 0 0 1.3125 V
1 0 1 0 1 1 1.325 V
1 0 1 0 1 0 1.3375 V
1 0 1 0 0 1 1.350 V
1 0 1 0 0 0 1.3625 V
1 0 0 1 1 1 1.375 V
1 0 0 1 1 0 1.3875 V
1 0 0 1 0 1 1.400 V
1 0 0 1 0 0 1.4125 V
1 0 0 0 1 1 1.425 V
1 0 0 0 1 0 1.4375 V
1 0 0 0 0 1 1.450 V
1 0 0 0 0 0 1.4625 V
0 1 1 1 1 1 1.475 V
0 1 1 1 1 0 1.4875 V
0 1 1 1 0 1 1.500 V
0 1 1 1 0 0 1.5125 V
0 1 1 0 1 1 1.525 V
0 1 1 0 1 0 1.5375 V
0 1 1 0 0 1 1.550 V
0 1 1 0 0 0 1.5625 V
0 1 0 1 1 1 1.575 V
0 1 0 1 1 0 1.5875 V
0 1 0 1 0 1 1.600 V

Rev. B | Page 8 of 24

ADP3168

THEORY OF OPERATION

The ADP3168 combines a multimode, fixed frequency PWM
control with multiphase logic outputs for use in 2-, 3-, and
4-phase synchronous buck CPU core supply power converters.
The internal 6-bit VID DAC conforms to Intel’s VRD/VRM 10
specifications. Multiphase operation is important for producing
the high currents and low voltages demanded by today’s
microprocessors. Handling the high currents in a single-phase
converter would place high thermal demands on system
components such as inductors and MOSFETs.

The multimode control of the ADP3168 ensures a stable, high
performance topology for

• Balancing currents and thermals between phases

• High speed response at the lowest possible switching

frequency and output decoupling

• Minimizing thermal switching losses due to lower

frequency operation

• Tight load-line regulation and accuracy

• High current output resulting from having up to a 4-phase

operation

• Reduced output ripple due to multiphase cancellation

• PC board layout noise immunity

• Ease of use and design due to independent component

selection

• Flexibility in operation for tailoring design to low cost or

high performance

NUMBER OF PHASES

The number of operational phases and their phase relationship
is determined by the internal circuitry that monitors the PWM
outputs. Normally, the ADP3168 operates as a 4-phase PWM
controller. Grounding the PWM4 pin programs 3-phase
operation; grounding the PWM3 and PWM4 pins programs
2-phase operation.

When the ADP3168 is enabled, the controller outputs a voltage
on PWM3 and PWM4 of approximately 550 mV. An internal
comparator checks each pin’s voltage vs. a threshold of 400 mV.
If the pin is grounded, the voltage is below the threshold and
the phase is disabled. The output resistance of the PWM pin is
approximately 5 kΩ during this detection time. Any external
pull-down resistance connected to the PWM pin should be at
least 25 kΩ to ensure proper operation. The phase detection is
made during the first two clock cycles of the internal oscillator.
After this time, if the PWM output is not grounded, the 5 kΩ
resistance is removed and switches between 0 V and 5 V. If the
PWM output was grounded, it remains off.

The PWM outputs become logic-level devices once normal
operation starts. The detection is normal and is intended for
driving external gate drivers such as the ADP3418. Because
each phase is monitored independently, operation approaching
100% duty cycle is possible. Also, more than one output can be
on at any given time for overlapping phases.

MASTER CLOCK FREQUENCY

The clock frequency of the ADP3168 is set with an external
resistor connected from the RT pin to ground. The frequency
follows the graph in Figure 3. To determine the frequency per
phase, the clock is divided by the number of phases in use. If
PWM4 is grounded, divide the master clock by 3 for the
frequency of the remaining phases. If PWM3 and PWM4 are
grounded, divide by 2. If all phases are in use, divide by 4.

OUTPUT VOLTAGE DIFFERENTIAL SENSING

The ADP3168 combines differential sensing with a high
accuracy VID DAC and reference and a low offset error amp­lifier to maintain a worst-case specification of ±10 mV differ­ential sensing error with a VID input of 1.6000 V over its full
operating output voltage and temperature range. The output
voltage is sensed between the FB and FBRTN pins. FB should
be connected through a resistor to the regulation point, usually
the remote sense pin of the microprocessor. FBRTN should be
connected directly to the remote sense ground point. The
internal VID DAC and precision reference are referenced to
FBRTN, which has a minimal current of 90 µA to allow
accurate remote sensing. The internal error amplifier compares
the output of the DAC to the FB pin to regulate the output
voltage.

OUTPUT CURRENT SENSING

The ADP3168 provides a dedicated current sense amplifier
(CSA) to monitor the total output current for proper voltage
positioning vs. load current and for current limit detection.
Sensing the load current at the output gives the total average
current being delivered to the load, which is an inherently more
accurate method than peak current detection or sampling the
current across a sense element such as the low-side MOSFET.
This amplifier can be configured several ways, depending on
the objectives of the system:

• Output inductor ESR sensing without thermistor for lowest

cost

• Output inductor ESR sensing with thermistor for improved

accuracy with tracking of inductor temperature

• Sense resistors for most accurate measurements

Rev. B | Page 9 of 24

ADP3168

The positive input of the CSA is connected to the CSREF pin,
which is connected to the output voltage. The inputs to the
amplifier are summed together through resistors from the
sensing element (such as the switch node side of the output
inductors) to the inverting input, CSSUM. The feedback resistor
between CSCOMP and CSSUM sets the gain of the amplifier,
and a filter capacitor is placed in parallel with this resistor.
The gain of the amplifier is programmable by adjusting the
feedback resistor to set the load line required by the micro­processor. The current information is then given as the differ­ence of CSREF − CSCOMP. This difference signal is used
internally to offset the VID DAC for voltage positioning and
as a differential input for the current-limit comparator.

To provide the best accuracy for the current sensing, the CSA
was designed to have a low offset input voltage. Also, the
sensing gain is determined by external resistors so that it can
be made extremely accurate.

ACTIVE IMPEDANCE CONTROL MODE

For controlling the dynamic output voltage droop as a function
of output current, a signal proportional to the total output
current at the CSCOMP pin can be scaled to be equal to the
droop impedance of the regulator times the output current.
This droop voltage is then used to set the input control voltage
to the system. The droop voltage is subtracted from the DAC
reference input voltage directly to tell the error amplifier where
the output voltage should be. This differs from previous
implementations and allows enhanced feed-forward response.

CURRENT-CONTROL MODE AND THERMAL BALANCE

The ADP3168 has individual inputs that are used for
monitoring the current in each phase. This information is
combined with an internal ramp to create a current-balancing
feedback system that has been optimized for initial current
balance accuracy and dynamic thermal balancing during
operation. This current-balance information is independent of
the average output current information used for positioning
described previously.

The magnitude of the internal ramp can be set to optimize
the transient response of the system. It also monitors the
supply voltage for feed-forward control for changes in the
supply. A resistor connected from the power input voltage to
the RAMPADJ pin determines the slope of the internal PWM
ramp. Detailed information about programming the ramp is
given in the Application Information section.

External resistors can be placed in series with individual phases,
for example, to create an intentional current imbalance so one
phase may have better cooling and can support higher currents.

Resistors R
in Figure 11) can be used for adjusting thermal balance. It is
best to add these resistors during the initial design, so make
sure placeholders are provided in the layout.

To increase the current in any given phase, make R
phase larger. (Make R
change during balancing.) Increasing R
a substantial increase in phase current. Increase each R
by small amounts to achieve balance, starting with the coolest
phase first.

VOLTAGE CONTROL MODE

A high gain bandwidth voltage mode error amplifier is used for
the voltage-mode control loop. The control input voltage to the
positive input is set via the VID 6-bit logic code, according to
the voltages listed in Table 4. This voltage is also offset by the
droop voltage for active positioning of the output voltage as a
function of current, commonly known as active voltage
positioning. The output of the amplifier is the COMP pin,
which sets the termination voltage for the internal PWM ramps.

The negative input (FB) is tied to the output sense location with
a resistor, R
voltage at this point. A current source from the FB pin flowing
through R
the VID voltage. The no-load voltage is negative with respect to
the VID DAC. The main loop compensation is incorporated
into the feedback network between FB and COMP.

SOFT START

The power-on ramp-up time of the output voltage is set with a
capacitor and a resistor in parallel from the DELAY pin to
ground. The RC time constant also determines the current-limit
latch-off time, as explained in the following section. In UVLO
or when EN is a logic low, the DELAY pin is held at ground.
After the UVLO threshold is reached and EN is a logic high, the
DELAY capacitor is charged up with an internal 20 µA current
source. The output voltage follows the ramping voltage on the
DELAY pin, limiting the inrush current. The soft-start time
depends on the values of VID DAC and C
effect from R
for detailed information on setting C

When the PWRGD threshold is reached, the soft-start cycle is
stopped and the DELAY pin is pulled up to 3 V. This ensures
that the output voltage is at the VID voltage when the PWRGD
signals to the system that the output voltage is good. If EN is
taken low or VCC drops below UVLO, the DELAY capacitor is
reset to ground to be ready for another soft-start cycle. Figure 8
shows a typical start-up sequence for the ADP3168.

through R

SW1

and is used for sensing and controlling the output

B,

is used for setting the no-load offset voltage from

B

. Refer to the Application Information section

DLY

(see the typical applica-tion circuit

SW4

for that

SW

= 0 for the hottest phase and do not

SW

to only 500 Ω makes

SW

, with a secondary

DLY

.

DLY

value

SW

Rev. B | Page 10 of 24

ADP3168

The latch-off function can be reset either by removing and
reapplying VCC to the ADP3168, or by pulling the EN pin low
for a short time. To disable the short-circuit latch-off function,
the external resistor to ground should be left open, and a high
value (>1 MΩ) resistor should be connected from DELAY to
VCC. This prevents the DELAY capacitor from discharging, so
the 1.8 V threshold is never reached. The resistor has an impact
on the soft-start time because the current through it adds to the
internal 20 µA current source.

03258-B-008

Figure 8. Start-Up Waveforms, Circuit of Figure 12. Channel 1—PWRGD,

Channel 2—V

CURRENT-LIMIT, SHORT-CIRCUIT, AND LATCH-OFF PROTECTION

The ADP3168 compares a programmable current-limit set
point to the voltage from the output of the current-sense
amplifier. The level of current limit is set with the resistor from
the ILIMIT pin to ground. During normal operation, the
voltage on ILIMIT is 3 V. The current through the external
resistor is internally scaled to give a current-limit threshold of

10.4 mV/µA. If the difference in voltage between CSREF and
CSCOMP rises above the current-limit threshold, the internal
current-limit amplifier controls the internal COMP voltage to
maintain the average output current at the limit.

After the limit is reached, the 3 V pull-up on the DELAY pin is
disconnected, and the external delay capacitor is discharged
through the external resistor. A comparator monitors the
DELAY voltage and shuts off the controller when the voltage
drops below 1.8 V. The current-limit latch-off delay time is
therefore set by the RC time constant discharging from 3 V to

1.8 V. The Application Information section discusses the
selection of C

Because the controller continues to cycle the phases during the
latch-off delay time, if the short is removed before the 1.8 V
threshold is reached, the controller returns to normal operation.
The recovery characteristic depends on the state of PWRGD. If
the output voltage is within the PWRGD window, the controller
resumes normal operation. However, if a short circuit has
caused the output voltage to drop below the PWRGD threshold,
a soft-start cycle is initiated.

DLY

, Channel 3—High-Side MOSFET VGS,

OUT

Channel 4—Low-Side MOSFET V

and R

DLY

.

GS

03258-B-009

Figure 9. Overcurrent Latch-Off Waveforms, Circuit of Figure 11. Channel 1—

PWRGD, Channel 2—V

Channel 4—High-Side MOSFET V

, Channel 3—CSCOMP Pin of ADP3168,

OUT

GS

During startup, when the output voltage is below 200 mV, a
secondary current limit is active. This is necessary because the
voltage swing of CSCOMP cannot go below ground. This
secondary current limit controls the internal COMP voltage
to the PWM comparators to 2 V. This limits the voltage drop
across the low-side MOSFETs through the current-balance
circuitry.

There is also an inherent per-phase current limit that protects
individual phases in the case where one or more phases stop
functioning because of a faulty component. This limit is based
on the maximum normal mode COMP voltage.

Rev. B | Page 11 of 24

ADP3168

DYNAMIC VID

The ADP3168 incorporates the ability to dynamically change
the VID input while the controller is running. This allows the
output voltage to change while the supply is running and
supplying current to the load. This is commonly referred to as
VID on-the-fly (OTF). A VID OTF can occur under either light
load or heavy load conditions. The processor signals the
controller by changing the VID inputs in multiple steps from
the start code to the finish code. This change can be either
positive or negative.

When a VID input changes state, the ADP3168 detects the
change and ignores the DAC inputs for a minimum of 400 ns.
This prevents a false code due to logic skew while the six VID
inputs are changing. Additionally, the first VID change initiates
the PWRGD and CROWBAR blanking functions for a mini­mum of 250 µs to prevent a false PWRGD or CROWBAR event.
Each VID change resets the internal timer. Figure 10 shows VID
on-the-fly performance when the output voltage is stepping up
and the output current is switching between minimum and
maximum values, which is the worst-case situation.

OUTPUT CROWBAR

As part of the protection for the load and output components of
the supply, the PWM outputs are driven low (turning on the
low-side MOSFETs) when the output voltage exceeds the upper
Power-Good threshold. This crowbar action stops once the
output voltage has fallen below the release threshold of
approximately 450 mV.

Turning on the low-side MOSFETs pulls down the output as the
reverse current builds up in the inductors. If the output over­voltage is due to a short of the high-side MOSFET, this action
current limits the input supply or blows its fuse, protecting the
microprocessor from destruction.

OUTPUT ENABLE AND UVLO

The input supply (VCC) to the controller must be higher than
the UVLO threshold, and the EN pin must be higher than its
logic threshold for the ADP3168 to begin switching. If UVLO is
less than the threshold or the EN pin is a logic low, the
ADP3168 is disabled. This holds the PWM outputs at ground,
shorts the DELAY capacitor to ground, and holds the ILIMIT
pin at ground.

Figure 10. VID On-the-Fly Waveforms, Circuit of Figure 12.

VID Change = 5 mV, 5 µs per Step, 50 Steps, I

Change =5 A to 65 A

OUT

POWER-GOOD MONITORING

The Power-Good comparator monitors the output voltage via
the CSREF pin. The PWRGD pin is an open-drain output
whose high level (when connected to a pull-up resistor)
indicates that the output voltage is within the nominal limits
specified in Table 1 based on the VID voltage setting. PWRGD
goes low if the output voltage is outside of this specified range.
PWRGD is blanked during a VID OTF event for a period of
250 µs to prevent false signals during the time the output is
changing.

In the application circuit, the ILIMIT pin should be connected

OD

to the

pins of the ADP3418 drivers. Because ILIMIT is
grounded, this disables the drivers so that both DRVH and
DRVL are grounded. This feature is important to prevent
discharging of the output capacitors when the controller is shut
off. If the driver outputs were not disabled, a negative voltage
could be generated on the output due to the high current
discharge of the output capacitors through the inductors.

03258-B-010

Rev. B | Page 12 of 24

ADP3168

t

(

()(

)

(

)

APPLICATION INFORMATION

The design parameters for a typical Intel VRD 10 compliant
CPU application are as follows:

• Input voltage (V

• VID setting voltage (V

) = 12 V

IN

) = 1.500 V

VID

• Duty cycle (D) = 0.125

• Nominal output voltage at no load (V

• Nominal output voltage at 65 A load (V

• Static output voltage drop based on a 1.3 mΩ load line (R

) = 1.480 V

ONL

) = 1.3955 V

OFL

O

from no load to full load

• (V

) = V

D

• Maximum output current (I

• Maximum output current step (∆I

ONL

− V

= 1.480 V − 1.3955 V = 84.5 mV

OFL

) = 65 A

O

) = 60 A

O

• Number of phases (n) = 3

• Switching frequency per phase (f

) = 267 kHz

SW

SETTING THE CLOCK FREQUENCY

The ADP3168 uses a fixed-frequency control architecture. The
frequency is set by an external timing resistor (R
frequency and the number of phases determine the switching
frequency per phase, which relates directly to switching losses
and the sizes of the inductors and input and output capacitors.
With n = 3 for three phases, a clock frequency of 800 kHz sets
the switching frequency, f

of each phase to 267 kHz, which

SW,

represents a practical trade-off between the switching losses and
the sizes of the output filter components. Figure 3 shows that to
achieve an 800 kHz oscillator frequency, the correct value for R
is 249 kΩ. Alternatively, the value for R

R

=

T

()

fn

SW

1

pF83.5

−××

can be calculated using

T

(1)

1

ΩM5.1

where 5.83 pF and 1.5 MΩ are internal IC component values.
For good initial accuracy and frequency stability, a 1% resistor
is recommended.

). The clock

T

The closest standard value for C
chosen, R

can be calculated for the current-limit latch-off

DLY

is 39 nF. Once C

DLY

time using

96.1

DELAY

R×=

DLY

If the result for R

C

DLY

(3)

DLY

is less than 200 kΩ, a smaller soft-start time

should be considered by recalculating the equation for C

)

longer latch-off time should be used. In no case should R
less than 200 k . In this example, a delay time of 8 ms gives

= 402 kΩ. The closest standard 5% value is 390 kΩ.

R

DLY

INDUCTOR SELECTION

The choice of inductance for the inductor determines the
ripple current in the inductor. Less inductance leads to more
ripple current, which increases the output ripple voltage and
conduction losses in the MOSFETs but allows using smaller
inductors and, for a specified peak-to-peak transient deviation,
less total output capacitance. Conversely, a higher inductance
means lower ripple current and reduced conduction losses but
requires larger inductors and more output capacitance for the
same peak-to-peak transient deviation. In any multiphase con­verter, a practical value for the peak-to-peak inductor ripple
current is less than 50% of the maximum dc current in the
same inductor. Equation 4 shows the relationship between
the inductance, oscillator frequency, and peak-to-peak ripple

T

current in the inductor.

Equation 5 can be used to determine the minimum inductance
based on a given output ripple voltage.

)

DV

−×=1

VID

I

R

L

SW

≥

(4)

Lf

×

DnRV

×−××

1

OVID

Vf

×

RIPPLESW

(5)

has been

DLY

DLY

DLY

, or a

be

SOFT START AND CURRENT LIMIT LATCH-OFF DELAY TIMES

Because the soft-start and current limit latch-off delay functions

Solving Equation 5 for a 10 mV p-p output ripple voltage yields:

375.01Ωm3.1V5.1

≥L

−××

mV10kHz267

×

=

nH456

share the DELAY pin, these two parameters must be considered
together. The first step is to set C

for the soft-start ramp. This

DLY

ramp is generated with a 20 µA internal current source. The
value of R

has a second-order impact on the soft-start time

DLY

because it sinks part of the current source to ground. However,
as long as R
The value for C

where t
390 kΩ and a desired a soft-start time of 3 ms, C

is kept greater than 200 kΩ, this effect is minor.

DLY

can be approximated using

DLY

⎛
⎜

−µ=220

DLY

SS

AC ×

⎜
⎝

is the desired soft-start time. Assuming an R

⎞

V

VID

×

R

DLY

t

ss

⎟
⎟

⎠

(2)

V

VID

is 36 nF.

DLY

of

DLY

Rev. B | Page 13 of 24

If the resulting ripple voltage is less than that designed for, the
inductor can be made smaller until the ripple value is met. This
allows optimal transient response and minimum output
decoupling.

The smallest possible inductor should be used to minimize the
number of output capacitors. Choosing a 600 nH inductor is a
good starting point and gives a calculated ripple current of

8.2 A. The inductor should not saturate at the peak current of

25.8 A and should be able to handle the sum of the power
dissipation caused by the average current of 22.7 A in the
winding and core loss.

ADP3168

Another important factor in the inductor design is the DCR,
which is used for measuring the phase currents. A large DCR
causes excessive power losses, while too small a value leads to

L1

470µF/16V × 6

1.6µH

V

IN

V

IN

12V

RTN

D1

1N4148WS

NICHICON PW SERIES

++

C1

D2

1N4148WS

C7

4.7µF

D3

1N4148WS

C11

4.7µF

D4

1N4148WS

C15

4.7µF

C6

ADP3418

1

BST

2

IN

3

OD

4

VCC

ADP3418

1

BST

2

IN

3

OD

4

VCC

ADP3418

1

BST

2

IN

3

OD
VCC

4

U2

U3

U4

DRVH

PGND

DRVL

DRVH

PGND

DRVL

DRVH

PGND

DRVL

SW

SW

SW

C8

100nF

C12

100nF

8

7

6

5

8

7

6

5

8

7

6

5

C16

100nF

IPD06N03L

increased measurement error. A good rule is to have the DCR
be about 1 to 1½ times the droop resistance (R
uses an inductor with a DCR of 1.6 mΩ.

C9

4.7µF

Q2

IPD06N03L

Q5

IPD06N03L

Q8

Q1

IPD12N03L

Q3

IPD06N03L

C13

4.7µF

Q4

IPD12N03L

Q6

IPD06N03L

C17

4.7µF

Q7

IPD12N03L

Q9

IPD06N03L

L2

600nH/1.6mΩ

C10

4.7nF
R1

2.2Ω

L3

600nH/1.6mΩ

C14

4.7nF
R2

2.2Ω

L4

600nH/1.6mΩ

C18

4.7nF
R3

2.2Ω

820µF/2.5V × 8

FUJITSU RE SERIES

8mΩ ESR (EACH)

++
C21

10µF × 23MLCC

AROUND
SOCKET

R

TH

100kΩ, 5%

C28

V

CC(CORE)

0.8375V–1.6V
65A AVG, 74A PK

V

CC(CORE) RTN

). Our example

O

POWER

GOOD

ENABLE

C19
1µF

FROM CPU

R

A

16.9kΩ

R

249kΩ

T

+

33µF

33pF

C

C20

U1

R

R

383kΩ

ADP3168

VID4

1

2

VID3

3

VID2

4

VID1

5

VID0

6

VID5

7

FBRTN

8

FB

FB

9

COMP

10

PWRGD

11

EN

12

DELAY

13

RT

14

RAMPADJ



VCC

PWM1

PWM2

PWM3

PWM4

SW1

SW2

SW3

SW4

GND

CSCOMP

CSSUM

CSREF

ILIMIT

28

27

26

25

24

23

R

SW2

22

21

20

19

18

17

C

CS1

2.2nF

16

15

C

CS2

1.5nF

1

R

R

35.7kΩ

R

LIM

200kΩ

R

SW1

SW3

1

1

CS1

R4

10Ω

C

B

1.5nF

C

R

A

B

390pF

1.33kΩ

C

DLY

R

39nF

NOTE:

1

FOR A DESCRIPTION OF OPTIONAL RSW RESISTORS, SEE THE THEORY OF OPERATION SECTION.

DLY

390kΩ

Figure 11. 65 A Intel Pentium 4-CPU Supply Circuit, VRD 10 Design

Rev. B | Page 14 of 24

R

CS2

73.2kΩ

R

PH3

124kΩ

R

PH2

124kΩ

R

PH1

124kΩ

03258-011

ADP3168

DESIGNING AN INDUCTOR

Once the inductance and DCR are known, the next step is to
either design an inductor or find a standard inductor that
comes as close as possible to meeting the overall design goals.
It is also important to have the inductance and DCR tolerance
specified to control the accuracy of the system. 15% inductance
and 8% DCR (at room temperature) are reasonable tolerances
that most manufacturers can meet.

The first decision in designing the inductor is to choose the
core material. There are several possibilities for providing low
core loss at high frequencies. Two examples are the powder
cores (e.g., Kool-Mµ® from Magnetics, Inc. or Micrometals)
and the gapped soft ferrite cores (e.g., 3F3 or 3F4 from Philips).
Low frequency powdered iron cores should be avoided due to
their high core loss, especially when the inductor value is
relatively low and the ripple current is high.

The best choice for a core geometry is a closed-loop type such
as a pot core, PQ, U, or E core or toroid. A good compromise
between price and performance is a core with a toroidal shape.

There are many useful references for quickly designing a power
inductor, such as the following:

• Magnetic Designer Software

Intusoft (www.intusoft.com)

• Designing Magnetic Components for High-Frequency

DC-DC Converters, by William T. McLyman, Kg

Magnetics, Inc., ISBN 1883107008

OUTPUT DROOP RESISTANCE

The design requires that the regulator output voltage measured
at the CPU pins drops when the output current increases. The
specified voltage drop corresponds to a dc output resistance (R

The output current is measured by summing together the
voltage across each inductor and passing the signal through a
low-pass filter. This summer filter is the CS amplifier config­ured with resistors R
The output resistance of the regulator is set by the following
equations, where R

R

CS

R ×= (6)

O

R

()

xPH

C

L

=

CS

RR

×

L

One has the flexibility of choosing either R
to select R

equal to 100 kΩ, and then solve for R

CS

rearranging Equation 6.

PH

R

()

xPH

R

R

xR

()

Next, use Equation 6 to solve for C

=

C

CS

(summers), and RCS and CCS (filter).

PH(X)

is the DCR of the output inductors:

L

R

L

(7)

CS

or R

CS

L

×=

R

CS

O

Ωm6.1
Ωm3.1

nH600

×

=×=

=

Ωk100Ωm6.1

Ωk123Ωk100

.

CS

nF75.3

. It is best

PH(X)

PH(X)

by

O

).

SELECTING A STANDARD INDUCTOR

The companies listed below can provide design consultation
and deliver power inductors optimized for high power
applications upon request.

Power Inductor Manufacturers

• Coilcraft

[phone]
www.coilcraft.com

• Coiltronics

[phone]
www.coiltronics.com

• Sumida Electric Company

[phone]
www.sumida.com

• Vishay Inter technology

[phone]
www.vishay.com

It is best to have a dual location for C
values can be used in parallel to get as close to the value desired.
For this example, choosing C
parallel is a good choice. For best accuracy, C
or 10% NPO capacitor. The closest standard 1% value for R
is 124 kΩ.

Rev. B | Page 15 of 24

in the layout so standard

CS

to be 1.5 nF and 2.2 nF in

CS

should be a 5%

CS

PH(X)

ADP3168

(

)

(

)

(

−

INDUCTOR DCR TEMPERATURE CORRECTION

With the inductor’s DCR being used as the sense element and
copper wire being the source of the DCR, one needs to com­pensate for temperature changes of the inductor’s winding.
Fortunately, copper has a well-known temperature coefficient
(TC) of 0.39%/°C.

is designed to have an opposite and equal percentage

If R

CS

change in resistance to that of the wire, it cancels the temper­ature variation of the inductor’s DCR. Due to the nonlinear
nature of NTC thermistors, resistors R

CS1

and R

are needed

CS2

(see Figure 12) to linearize the NTC and produce the desired
temperature tracking.

PLACE AS CLOSE AS POSSIBLE

TO NEAREST INDUCTOR

OR LOW-SIDE MOSFET

R

TH

TO

SWITCH

NODES

TO

V

OUT

SENSE

4. Compute the relative values for R

R

=

2

CS

=

R

1

CS

1

=

R

TH

5. Calculate R

()

1

A

)

1

−

R

−

2

1

1

−

−

1

= RTH × RCS, then select the closest value of

TH

(8)

A

R

−γ

1

2

CSCS

1

RR

CS1CS2

thermistor available. Also compute a scaling factor k based
on the ratio of the actual thermistor value used relative to
the computed one:

R

()

k

=

ACTUALTH

R

()

CALCULATEDTH

(9)

, R

, and RTH using:

CS1

CS2

()

() ( )

11

21

ABBABA

11

BAABBA

−−γ×−×−γ×−×

γ×−×+γ×−×−×γ×γ×−

1221

ADP3168

R

C

CS

1.8nF

CS1

CSCOMP

18

CSSUM

17

CSREF

16

Figure 12. Temperature Compensation Circuit Values

PH1

R

CS2

AS SHORT AS POSSIBLE

AND WELL AWAY FROM

SWITCH NODE LINES

KEEP THIS PATH

PH2

PH3

R

R

R

The following procedure and expressions yield values to use for

, R

R

, and RTH (the thermistor value at 25°C) for a given RCS

CS1

CS2

value.

1. Select an NTC based on type and value. Because there is no

value yet, start with a thermistor with a value close to R

.

CS

The NTC should also have an initial tolerance of better
than 5%.

2. Based on the type of NTC, find its relative resistance

value at two temperatures. The temperatures that work
well are 50°C and 90°C. We will call these resistance values
A (R

TH(50°C

)/R

TH(25°C)

) and B (R

TH(90°C

)/R

TH(25°C)

). Note that

the NTC’s relative value is always 1 at 25°C.

3. Find the relative value of R

required for each of these

CS

temperatures. This is based on the percentage change
needed, which in this example is initially 0.39%/°C.
These are called r
(1/(1 + TC × (T

= 90°C.

and T

2

(1/(1 + TC × (T1 − 25))) and r2

1

− 25))), where TC = 0.0039, T1 = 50°C,

2

6. Finally, calculate values for R

kRR

γ

××=

1

CSCSCS1

()( )()

1

kkRR

×+−×=

γ

CS1

CSCSCS2

and R

2

using Equation 10:

CS2

(10)

For this example, R

has been chosen to be 100 kΩ , so we start

CS

with a thermistor value of 100 kΩ. Looking through available
0603 size thermistors, we find a Vishay NTHS0603N01N1003JR
NTC thermistor with A = 0.3602 and B = 0.09174. From these

03258-B-012

we compute R
Solving for R

= 0.3796, R

CS1

yields 107.51 kΩ, so we choose 100 kΩ, making

TH

k = 0.9302. Finally, we find R

= 0.7195, and R

CS2

CS1

and R

to be 35.3 kΩ and

CS2

= 1.0751.

TH

73.9 kΩ. Choosing the closest 1% resistor values yields a choice
of 35.7 kΩ and 73.2 kΩ.

OUTPUT OFFSET

Intel’s specification requires that at no load the nominal output
voltage of the regulator be offset to a lower value than the
nominal voltage corresponding to the VID code. The offset is
set by a constant current source flowing out of the FB pin (I
and flowing through R

. The value of RB can be found using

B

Equation 11:

VVR−

ONLVID

=

B

I

FB

(11)

=BR

V480.1V5.1=−

µA15

Ωk33.1

The closest standard 1% resistor value is 1.33 kΩ.

)

FB

Rev. B | Page 16 of 24

ADP3168

C

SELECTION

OUT

The required output decoupling for the regulator is typically
recommended by Intel for various processors and platforms.
One can also use some simple design guidelines to determine
what is required. These guidelines are based on having both
bulk and ceramic capacitors in the system.

The first thing is to select the total amount of ceramic capaci­tance. This is based on the number and type of capacitor to be
used. The best location for ceramics is inside the socket, with
12 to 18 of size 1206 being the physical limit. Others can be
placed along the outer edge of the socket as well.

Combined ceramic values of 200 µF to 300 µF are recom­mended, usually made up of multiple 10 µF or 22 µF capacitors.
Select the number of ceramics and then find the total ceramic
capacitance (C

).

Z

For our example, 23 10 µF 1206 MLC capacitors (C
were used. The VID on-the-fly step change is 250 mV in 150 µs
with a setting error of 2.5 mV. Solving for the bulk capacitance
yields

C

()

MINx

C

()

MAXx

⎛

⎛

⎜

⎜

1

+

⎜

⎜

⎜

⎝

⎝

=

⎛
⎜

≤

⎜
⎝

≤

2

mF9.23

A60nH600

×

××

()

−

V5.1Ωm3.13

×

mV250nH600

2

×××

V5.1Ωm3.16.43

Ωm3.16.43V5.1µs150

××××

nH600mV250

×

where k = 4.6

⎞
⎟

⎟
⎠

×

=

2

⎞
⎟

⎟
⎠

= 230 µF)

Z

mF92.5µF230

⎞
⎟

−

−

⎟
⎟
⎠

µF2301

Next, there is an upper limit imposed on the total amount of
bulk capacitance (C
voltage stepping of the output (voltage step V
error of V

) and a lower limit based on meeting the critical

ERR

capacitance for load release for a given maximum load step ∆I

≥

()

MINx

C

()

MAXx

L

22

RnK

O

) when one considers the VID on-the-fly

X

⎛
⎜

⎜
⎝

≤

=

ILCΔ

×

O

VRn

××

VID

O

⎛
⎜

V

V

⎜

V

⎜

VID

⎝

⎛

V

ERR

⎜

nK 1where

⎜

V

V

⎝

⎞
⎟

(12)

C

−

z

⎟
⎠

⎛
⎜

t

v

⎜
⎝

⎞
⎟
⎟
⎠

nKR

V

VID

V

V

O

×+×× 11

L

in time tV with

V

2

⎞

⎞

⎟

⎟

−

⎟
⎠

(13)

−

C

⎟

z

⎟
⎠

O

To meet the conditions of these expressions and transient re­sponse, the ESR of the bulk capacitor bank (R
than two times the droop resistance, R
than C

, the system does not meet the VID on-the-fly

X(MAX)

O

) should be less

X

. If the C

X(MIN)

is larger

specification and may require the use of a smaller inductor or
more phases (and may have to increase the switching frequency
to keep the output ripple the same).

Using eight 820 µF A1-Polys with a typical ESR of 8 mΩ each
yields C

= 6.56 mF with an RX = 1.0 mΩ.

X

One last check should be made to ensure that the ESL of the

:

bulk capacitors (L
frequency transient spike. This is tested using

L

x

In this example, L
which satisfies this limitation. If the L

) is low enough to limit the initial high

X

×≤

RCL

zx

()

is 375 pH for the eight A1-Polys capacitors,

X

2

=×≤

(14)

pH389Ωm3.1µF230

of the chosen bulk

X

capacitor bank is too large, the number of capacitors must be
increased.

One should note that for this multimode control technique, all
ceramic designs can be used as long as the conditions of
Equations 11, 12, and 13 are satisfied.

Rev. B | Page 17 of 24

ADP3168

POWER MOSFETS

For this example, the N-channel power MOSFETs have been
selected for one high-side switch and two low-side switches per
phase. The main selection parameters for the power MOSFETs

GS(TH)

, QG, C

are V
voltage (the supply voltage to the ADP3418) dictates whether
standard threshold or logic-level threshold MOSFETs must be
used. With V
<2.5 V) are recommended.

The maximum output current I
ment for the low-side (synchronous) MOSFETs. The ADP3168,
balances currents between phases, thus the current in each low­side MOSFET is the output current divided by the total number
of MOSFETs (n
following expression shows the total power being dissipated in
each synchronous MOSFET in terms of the ripple current per
phase (I

) and average total output current (IO):

R

SF

Knowing the maximum output current being designed for and
the maximum allowed power dissipation, one can find the
required R

DS(ON)

an ambient temperature of 50°C, a safe limit for PSF is 1 W to

1.5 W at 120°C junction temperature. Thus, for this example
(65 A maximum), we find R
This R

is also at a junction temperature of about 120°C,

DS(SF)

so we need to make sure we account for this when making
this selection. For this example, we selected two lower-side
MOSFETs at 7 mΩ each at room temperature, which gives

8.4 mΩ at high temperature.

Another important factor for the synchronous MOSFET is
the input capacitance and feedback capacitance. The ratio
of the feedback to input needs to be small (less than 10%
is recommended) to prevent accidental turn-on of the
synchronous MOSFETs when the switch node goes high.

Also, the time to switch the synchronous MOSFETs off should
not exceed the nonoverlap dead time of the MOSFET driver
(40 ns typical for the ADP3418). The output impedance of
the driver is about 2 Ω and the typical MOSFET input gate
resistances are about 1 Ω to 2 Ω, so a total gate capacitance of
less than 6000 pF should be adhered to. Because there are
two MOSFETs in parallel, the input capacitance for each
synchronous MOSFET should be limited to 3000 pF.

The high-side (main) MOSFET must be able to handle two
main power dissipation components: conduction and switching
losses. The switching loss relates to the amount of time it takes
for the main MOSFET to turn on and off, and to the current
and voltage that are being switched. Basing the switching speed
on the rise and fall time of the gate driver impedance and

, C

, and R

ISS

RSS

~10 V, logic-level threshold MOSFETs (V

GATE

). With conduction losses being dominant, the

SF

⎡

⎞

⎛

I

O

⎢

⎟

1

()

⎜

DP ×

×−=

⎟

⎜

n

⎢

SF

⎠

⎝

⎣

. The minimum gate drive

DS(ON)

determines the R

O

12

⎛

In

1

R

⎜

×+

⎜

n

SF

⎝

DS(ON)

22

⎤

⎞

⎥

⎟

R

⎟

⎥

⎠

⎦

for the MOSFET. For D-PAK MOSFETs up to

(per MOSFET) < 8.7 mΩ.

DS(SF)

require-

(15)

()

SFDS

GS(TH)

MOSFET input capacitance, the following expression provides
an approximate value for the switching loss per main MOSFET,
where n

Here, R

is the total number of main MOSFETs:

MF

IV

×

fP ×××

()

is the total gate resistance (2 Ω for the ADP3418 and

G

××= 2

SWMFS

OCC

n

MF

n

MF

R

G

n

(16)

C

ISS

about 1 Ω for typical high speed switching MOSFETs, making

= 3 Ω) and C

R

G

MOSFET. Note that adding more main MOSFETs (n

is the input capacitance of the main

ISS

) does

MF

not really help the switching loss per MOSFET because the
additional gate capacitance slows switching. The best thing to
reduce switching loss is to use lower gate capacitance devices.

The conduction loss of the main MOSFET is given by the
following, where R

DP ×

() ()

MFC

Typically, for main MOSFETs, the highest speed (low C

is the ON resistance of the MOSFET:

DS(MF)

⎡

⎞

⎛

I

O

⎢

⎟

⎜

×=

⎟

⎜

n

⎢

MF

⎠

⎝

⎣

12

⎛

1

⎜

×+

⎜
⎝

22

⎞

×

In

R

⎟
⎟

n

MF

⎠

⎤
⎥

R

⎥
⎦

(17)

MFDS

)

ISS

device is preferred, but these usually have higher ON resistance.
Select a device that meets the total power dissipation (about

1.5 W for a single D-PAK) when combining the switching and
conduction losses.

For this example, an Infineon IPD12N03L was selected as the
main MOSFET (three total; n
(max) and R

= 14 mΩ (max at TJ = 120°C), and an

DS(MF)

= 3), with a C

MF

= 1460 pF

ISS

Infineon IPD06N03L was selected as the synchronous
MOSFET (six total; n

= 8.4 mΩ (max at TJ = 120°C). The synchronous

R

DS(SF)

MOSFET C

is less than 3000 pF, satisfying that requirement.

ISS

= 6), with C

SF

Solving for the power dissipation per MOSFET at I

= 8.2 A yields 863 mW for each synchronous MOSFET and

I

R

= 2370 pF (max) and

ISS

= 65 A and

O

1.44 W for each main MOSFET. These numbers work well
considering there is usually more PCB area available for each
main MOSFET vs. each synchronous MOSFET.

One last thing to consider is the power dissipation in the driver
for each phase. This is best described in terms of the Q
MOSFETs and is given by the following, where Q
gate charge for each main MOSFET and Q

is the total gate

GSF

G

is the total

GMF

for the

charge for each synchronous MOSFET:

⎡

f

SW

P ×

⎢

DRV

⎣

()

n

×=2

Also shown is the standby dissipation factor (I

⎤

+×+××

⎥
⎦

× VCC) for

CC

VIQnQn

CCCCGSFSFGMFMF

the driver. For the ADP3418, the maximum dissipation should
be less than 400 mW. For our example, with I

= 22.8 nC, and Q

Q

GMF

= 34.3 nC, we find 260 mW in each

GSF

= 7 mA,

CC

driver, which is below the 400 mW dissipation limit. See the
ADP3418 data sheet for more details.

(18)

Rev. B | Page 18 of 24

ADP3168

RAMP RESISTOR SELECTION

The ramp resistor (RR) is used for setting the size of the internal
PWM ramp. The value of this resistor is chosen to provide the
best combination of thermal balance, stability, and transient
response. This expression determines the optimum value:

LA

×

R

=

R

R

=

R

where A

is the internal ramp amplifier gain, AD is the current

R

balancing amplifier gain, R
resistance, and C

R

3

is the internal ramp capacitor value. The

R

CRA

×××

RDSD

nH6002.0

×

pF5Ωm2.453

×××

is the total low-side MOSFET ON

DS

Ωk381

=

(19)

closest standard 1% resistor value is 383 kΩ.

The internal ramp voltage magnitude can be calculated using

()

×−×

=

V

R

=

V

R

1

VDA

VIDR

××

fCR

SWRR

()

×−×

××

(20)

V5.1125.012.0

kHz267pF5Ωk383

The size of the internal ramp can be made larger or smaller. If
it is made larger, stability and transient response improve, but
thermal balance degrades. Likewise, if the ramp is made
smaller, thermal balance improves at the sacrifice of transient
response and stability. The factor of three in the denominator of
Equation 19 sets a ramp size that gives an optimal balance for
good stability, transient response, and thermal balance.

COMP PIN RAMP

There is a ramp signal on the COMP pin due to the droop
voltage and output voltage ramps. This ramp amplitude adds to
the internal ramp to produce the following overall ramp signal
at the PWM input.

V

V

=

RT

⎛
⎜

1

−

⎜
⎝

For this example, the overall ramp signal is found to be 0.63 V.

R

()

12

×−×

(21)

⎞

Dn

⎟
⎟

RCfn

×××

OXSW

⎠

For values of R
be lower than expected, so some adjustment of R
needed. Here, I
the supply. For our example, choosing 120 A for I

to be 200 kΩ, for which we chose 200 kΩ as the nearest

R

LIM

1% value.

The per-phase current limit described earlier has its limit
determined by the following:

I +

PHLIM

For the ADP3168, the maximum COMP voltage (V

3.3 V, the COMP pin bias voltage (V
current balancing amplifier gain (A
and R

DS(MAX)

find a per-phase limit of 66 A.

This limit can be adjusted by changing the ramp voltage V
make sure not to set the per-phase limit lower than the average
per-phase current (I

There is also a per-phase initial duty cycle limit determined by

MAX

For this example, the maximum duty cycle is found to be 0.42.

FEEDBACK LOOP COMPENSATION DESIGN

Optimized compensation of the ADP3168 allows the best
possible response of the regulator’s output to a load change. The
basis for determining the optimum compensation is to make
the regulator and output decoupling appear as an output
impedance that is entirely resistive over the widest possible
frequency range, including dc, and equal to the droop resistance

). With the resistive output impedance, the output voltage

(R

O

droops in proportion with the load current at any load current
slew rate; this ensures the optimal positioning and allows the
minimization of the output decoupling.

greater than 500 kΩ, the current limit may

LIM

may be

LIM

is the average current limit for the output of

LIM

, we find

LIM

VVV

RA

MAXDSD

()

−−

≅

()

×

I

BIASRMAXCOMP

R

(23)

2

COMP(MAX)

) is 1.2 V, and the

BIAS

) is 5. Using VR of 0.63 V

D

of 4.2 mΩ (low-side ON resistance at 150°C), we

, but

R

/n).

LIM

VV

−

×=

()

DD

BIASMAXCOMP

V

RT

(24)

) is

CURRENT-LIMIT SET POINT

To select the current-limit set point, first find the resistor value
for R

. The current limit threshold for the ADP3168 is set

LIM

with a 3 V source (V

). R

(A

LIM

can be found using the following:

LIM

R

LIM

×

=

) across R

LIM

VA

LIMLIM

(22)

RI

×

OLIM

with a gain of 10.4 mV/µA

LIM

Rev. B | Page 19 of 24

With the multimode feedback structure of the ADP3168, the
feedback compensation must be set to make the converter’s
output impedance, working in parallel with the output
decoupling, meet this goal. There are several poles and zeros
created by the output inductor and decoupling capacitors
(output filter) that need to be compensated for.

A type-three compensator on the voltage feedback is adequate
for proper compensation of the output filter. The expressions
given in Equations 25 to 29 are intended to yield an optimal
starting point for the design; some adjustments may be
necessary to account for PCB and component parasitic effects
(see the Tuning Procedure for the ADP3168).

ADP3168

(

)

(

The first step is to compute the time constants for all of the poles and zeros in the system:

VR

×

RARnR

+×××=

DSDOE

RTL

V

Ωm2.45Ωm3.13

+×+×=ER

+

DID

×

V5.1

12

()

V63.0Ωm6.1

+

VDnL

××−××

RT

VRCn

×××

VIDOX

V63.0375.01nH6002

×−××

V5.1Ωm3.1mF56.63

×××

(25)

Ωm9.37

RR

'

L

() ()

OXA

X

RRCT

' =

R

O

−

O

×+−×=

R

X

Ωm6.0Ωm3.1mF56.6

pH375

×+−×=

Ωm3.1

−

Ωm0.1

()( )

CRRRT

XOXB

(27)

µs97.1mF56.6Ωm3.1Ωm6.0Ωm0.1' =×−+=×−+=

⎛
⎜

LV

RT

T

=

C

−×

⎜

2

⎝

RV

×

⎞

RA

×

DSD

⎟
⎟

f

×

SW

⎠

EVID

=

⎛
⎜

nH600V63.0

⎜
⎝

×

×

=×

×

Ωm9.37V5.1

⎞

Ωm2.45

⎟
⎟

kHz2672

⎠

µs2.6

=

(28)

2

××

RCC

=

T

D

()

OZX

'

=

×+−×

RCRRC

OZOX

()

××

2

Ωm3.1µF230mF56.6

)

Ωm3.1µF230Ωm6.0Ωm3.1mF56.6

×+−×

ns521

=

(29)

where, for the ADP3168, R' is the PCB resistance from the bulk capacitors to the ceramics and where R
ON resistance per phase. For this example, A

L

is 375 pH for the eight Al-Poly capacitors.

X

is 5, VRT equals 0.63 V, R' is approximately 0.6 mΩ (assuming a 4-layer motherboard), and

D

Ωm6.0Ωm3.1

is the total low side MOSFET

DS

(26)

µs79.4

The compensation values can be solved using the following:

××

TRn

=

C

A

AO

×

RR

BE

(30)

CA

R

C

C

=

T

C

A

C

A

T

B

B

R

B

T

D

FB

R

A

××

×

Ωk33.1Ωm9.37

µs2.6

===

pF371

µs97.1

===

Ωk33.1

ns521

===

Ωk7.16

pF371

=

(31)

Ωk7.16

(32)

nF48.1

(33)

pF2.31

µs79.4Ωm3.13

Choosing the closest standard values for the components yields

CCRC

FBBAA

pF33,nF5.1Ω,k9.16,pF390 ====

Figure 13 shows the typical transient response using the
compensation values.

Figure 13. Typical Transient Response for Design Example

03258-B-013

Rev. B | Page 20 of 24

ADP3168

CIN SELECTION AND INPUT CURRENT DI/DT REDUCTION

In continuous inductor current mode, the source current of the
high-side MOSFET is approximately a square wave with a duty
ratio equal to n × V
maximum output current. To prevent large voltage transients, a
low ESR input capacitor sized for the maximum rms current
must be used. The maximum rms capacitor current is given by

IDI

OCRMS

CRMS

Note that the capacitor manufacturer’s ripple current ratings are
often based on only 2,000 hours of life. This makes it advisable
to further derate the capacitor or choose a capacitor rated at a
higher temperature than required. Several capacitors may be
placed in parallel to meet size or height requirements in the
design. In this example, the input capacitor bank is formed by
three 2,200 µF, 16 V Nichicon capacitors with a ripple current
rating of 3.5 A each.

To reduce the input current di/dt to a level below the
recommended maximum of 0.1 A/µs, an additional small
inductor (L > 1 µH @ 15 A) should be inserted between the
converter and the supply bus. That inductor also acts as a filter
between the converter and the primary power source.

RR

NEWCS

2

()

and an amplitude of one-nth of the

OUT/VIN

1

1

××=

65125.0

OLDSC

()

2

−

DN

×

1

××=

×=

×

−

NL

−

NL

R

2

125.03

VV

FLCOLD

VV

FLHOT

()

NEWCS

AAI

5.101

=−

(35)

=

() ( ) () ( )

100

90

80

70

60

50

40

EFFICIENCY (%)

30

20

10

0

Figure 14. Efficiency of the Circuit of Figure 11 vs. Output Current

(34)

() ( )

()

20 30010 405060

OUTPUT CURRENT (A)

TUNING PROCEDURE FOR THE ADP3168

1. Build circuit based on compensation values computed

from design spreadsheet.

2. Hook up dc load to circuit, turn on, and verify operation.

Also check for jitter at no-load and full-load.

DC Loadline Setting

3. Measure output voltage at no-load (V

within tolerance.

4. Measure output voltage at full-load cold (V

board set for ~10 minutes at full-load and measure output

). If there is a change of more than a couple of

(V

FLHOT

millivolts, adjust R

CS1

and R

using Equations 35 and 37.

CS2

5. Repeat Step 4 until cold and hot voltage measurements

remain the same.

6. Measure output voltage from no-load to full-load using 5 A

steps. Compute the loadline slope for each change and then
average to get overall loadline slope (R

7. If R

following to adjust the R

is off from RO by more than 0.05 mΩ, use the

OMEAS

values:

PH

R

RR ×=

NEWPH

()

()

OMEAS

OLDPH

(36)

R

O

8. Repeat Steps 6 and 7 to check loadline and repeat

adjustments if necessary.

9. Once complete with dc loadline adjustment, do not change

, R

, R

R

PH

, or RTH for rest of procedure.

CS1

CS2

10. Measure output ripple at no-load and full-load with scope

and make sure it is within specifications.

1

+

RR

CTHOLDCS

°

251

()

−×−+×

() ( )

−

RRRRRRR

1

()

CTHCTHOLDCSNEWCSOLDCSCTHOLDCS

°°°

2525121251

03258-B-014

). Verify that it is

NL

OMEAS

(37)

FLCOLD

).

). Let

Rev. B | Page 21 of 24

ADP3168

AC Loadline Setting

11. Remove dc load from circuit and hook up dynamic load.

12. Hook up scope to output voltage and set to dc coupling

with time scale at 100 µs/div.

13. Set dynamic load for a transient step of about 40 A at 1

kHz with 50% duty cycle.

14. Measure output waveform (may have to use dc offset on

scope to see waveform). Try to use vertical scale of 100
mV/div or finer.

15. This waveform should look something like Figure 15. Use

the horizontal cursors to measure V

ACDRP

and V

DCDRP

as
shown. Do not measure the undershoot or overshoot that
happens immediately after the step.

V

ACDRP

V

DCDRP

Figure 15. AC Loadline Waveform

16. If the V

millivolts, use Equation 38 to adjust C

ACDRP

and V

are different by more than a few

DCDRP

Parallel different

CS.

values to get the right one because there are limited
standard capacitor values available. (Make sure that there
are locations for two capacitors in the layout for this.)

V

CC ×=

()

NEWCS

()

ACDRP

OLDCS

V

(38)

DCDRP

17. Repeat Steps 11 to 13, making adjustments if necessary.

Once complete, do not change C

again in the procedure.

CS

18. Set dynamic load step to maximum step size (do not use a

step size larger than needed) and verify that the output
waveform is square (which means V

ACDRP

and V

DCDRP

are
equal).Make sure load step slew rate and turn-on are set for

a slew rate of ~150 A/µs to 250 A/µs (for example, a load
step of 50 A should take 200 ns to 300 ns) with no overshoot.

Some dynamic loads have an excessive turn-on overshoot if
a minimum current is not set properly. (This is an issue if
using a VTT tool.)

Initial Transient Setting

19. With dynamic load still set at maximum step size, expand

scope time scale to see 2 µs/div to 5 µs/div. The waveform
may have two overshoots and one minor undershoot (see
Figure 16). Here, V

is the final desired value.

DROOP

V

TRAN1

V

TRAN2

Figure 16. Transient Setting Waveform

20. If both overshoots are larger than desired, try making the

adjustments described below. (Note: If these adjustments
do not change the response, you are limited by the output
decoupling.) Check the output response each time you
make a change as well as the switching nodes (to make sure
the response is still stable).

a. Make ramp resistor larger by 25% (R
b. For V

, increase CB or increase switching

TRAN1

frequency.

c. For V

, increase RA and decrease CA by 25%.

TRAN2

21. For load release (see Figure 17), if V

V

(see Figure 16), there is not enough output

TRAN1

capacitance. You will either need more capacitance or have
to make the inductor values smaller. (If you change
inductors, you will need to start the design over using the
spreadsheet and this tuning procedure.)

V

TRANREL

Figure 17. Transient Setting Waveform

Because the ADP3168 turns off all of the phases (switches
inductors to ground), there is no ripple voltage present during
load release. Thus, you do not have to add headroom for ripple,
allowing your load release V
the amount of ripple and still meet specifications.

If V

TRAN1

and V

are less than the desired final droop, this

TRANREL

implies that capacitors can be removed. When removing
capacitors, check the output ripple voltage as well to make sure
it is still within specifications.

V

DROOP

V

DROOP

to be larger than V

TRANREL

RAMP

TRANREL

).

is larger than

TRAN1

-016

-017

by

Rev. B | Page 22 of 24

ADP3168

LAYOUT AND COMPONENT PLACEMENT

The following guidelines are recommended for optimal
performance of a switching regulator in a PC system. Key layout
issues are illustrated in Figure 18.

12V CONNECTOR

THERMISTOR

OUTPUT

POWER

PLANE

KEEP-OUT

AREA

Figure 18. Layout Recommendations

GENERAL RECOMMENDATIONS

For good results, a PCB with at least four layers is recom­mended. This should allow the needed versatility for control
circuitry interconnections with optimal placement, power
planes for ground, input, and output power, and wide inter­connection traces in the rest of the power delivery current
paths. Keep in mind that each square unit of 1 ounce copper
trace has a resistance of ~0.53 mΩ at room temperature.

Whenever high currents are routed between PCB layers, vias
should be used liberally to create several parallel current paths
so that the resistance and inductance introduced by the current
paths is minimized and the via current rating is not exceeded.

If critical signal lines (including the output voltage sense lines
of the ADP3168) must cross through power circuitry, it is best
if a signal ground plane can be interposed between those signal
lines and the traces of the power circuitry. This creates a shield
to minimize noise injection into the signals at the expense of
making signal ground a bit noisier.

An analog ground plane should be used around and under the
ADP3168 as a reference for the components associated with the
controller. This plane should be tied to the nearest output de­coupling capacitor ground and should not be tied to any other
power circuitry to prevent power currents from flowing in it.

The components around the ADP3168 should be located close
to the controller with short traces. The most important traces to
keep short and away from other traces are the FB and CSSUM
pins. See Figure 18 for details on layout for the CSSUM node.

SWITCH NODE

PLANES

KEEP-OUT

AREA

CPU

SOCKET

KEEP-OUT

AREA

INPUT POWER PLANE

KEEP-OUT

AREA

03258-B-018

The output capacitors should be connected as close as possible
to the load (or connector) that receives the power (e.g., a
microprocessor core). If the load is distributed, the capacitors
should also be distributed and generally in proportion to where
the load tends to be more dynamic.

Avoid crossing signal lines over the switching power path loop,
as described next.

POWER CIRCUITRY

The switching power path should be routed on the PCB to
encompass the shortest possible length in order to minimize
radiated switching noise energy (i.e., EMI) and conduction
losses in the board. Failure to take proper precautions often
results in EMI problems for the entire PC system as well as
noise-related operational problems in the power converter
control circuitry. The switching power path is the loop formed
by the current path through the input capacitors and the power
MOSFETs including all interconnecting PCB traces and planes.
Using short and wide interconnection traces is critical in this
path because it minimizes the inductance in the switching loop,
which can cause high energy ringing, and it accommodates the
high current demand with minimal voltage loss.

Whenever a power dissipating component (e.g., a power
MOSFET) is soldered to a PCB, the liberal use of vias, both
directly on the mounting pad and immediately surrounding it,
is recommended. Two important reasons for this are improved
current rating through the vias and improved thermal
performance from vias extended to the opposite side of the
PCB, where a plane can more readily transfer the heat to the air.
Make a mirror image of any pad being used to heat sink the
MOSFETs on the opposite side of the PCB to achieve the best
thermal dissipation to the air around the board. To further
improve thermal performance, use the largest possible pad area.

The output power path should also be routed to encompass a
short distance. The output power path is formed by the current
path through the inductor, the output capacitors, and the load.

For best EMI containment, a solid power ground plane should
be used as one of the inner layers extending fully under all the
power components.

SIGNAL CIRCUITRY

The output voltage is sensed and regulated between the FB pin
and the FBRTN pin, which connects to the signal ground at the
load. To avoid differential mode noise pickup in the sensed
signal, the loop area should be small. Thus the FB and FBRTN
traces should be routed adjacent to each other on top of the
power ground plane back to the controller.

Connect the feedback traces from the switch nodes as close as
possible to the inductor. The CSREF signal should be connected
to the output voltage at the nearest inductor to the controller.

Rev. B | Page 23 of 24

ADP3168

OUTLINE DIMENSIONS

9.80

9.70

9.60

28

PIN 1

0.15

0.05

COPLANARITY

0.10

0.65
BSC

0.30

0.19

COMPLIANT TO JEDEC STANDARDS MO-153AE

1.20 MAX

SEATING

PLANE

15

4.50

4.40

4.30

0.20

0.09

6.40 BSC

8°
0°

0.75

0.60

0.45

141

Figure 19. 28-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-28)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Options Quantity per Reel

ADP3168JRU-REEL7 0°C to 85°C RU-28 (TSSOP-28) 1000
ADP3168JRU-REEL 0°C to 85°C RU-28 (TSSOP-28) 2500
ADP3168JRUZ-REEL

1

Z = Pb-free part.

1

0°C to 85°C RU-28 (TSSOP-28) 2500

© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

C03258-0-12/04(B)

Rev. B | Page 24 of 24