ANALOG DEVICES ADP3160, ADP3167 Service Manual

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5-Bit Programmable 2-Phase

a

FEATURES
ADOPT™ Optimal Positioning Technology for Superior

Load Transient Response and Fewest Output Capacitors
Complies with VRM 9.0 with Lowest System Cost
Active Current Balancing between Both Output Phases
5-Bit Digitally Programmable 1.1 V to 1.85 V Output
Dual Logic-Level PWM Outputs for Interface to External

High Power Drivers
Total Output Accuracy ⴞ0.8% over Temperature
Current-Mode Operation
Short Circuit Protection
Power Good Output
Overvoltage Protection Crowbar Protects

Microprocessors with No Additional

External Components

APPLICATIONS
Desktop PC Power Supplies for:

Intel Pentium

AMD Athlon™ Processors

VRM Modules

®

4 Processors

Synchronous Buck Controller

ADP3160/ADP3167

FUNCTIONAL BLOCK DIAGRAM

VCC

CROWBAR

CMP1

SET

RESET

CMP3

CMP2

CMP

CMP

2-PHASE

DRIVER

LOGIC

DAC+24%

DAC–18%

g

m

REF

GND

CT

COMP

UVLO

AND

BIAS

3.0V

REFERENCE

OSCILLATOR

ADP3160/ADP3167

PWM1

PWM2

PWRGD

CS–

CS+

FB

GENERAL DESCRIPTION

The ADP3160 and ADP3167 are highly efficient, dual output,
synchronous buck switching regulator controllers optimized for
converting a 5 V or 12 V main supply into the core supply voltage
required by high-performance processors, such as Pentium 4 and
Athlon. The ADP3160 uses an internal 5-bit DAC to read a volt­age identification (VID) code directly from the processor that is
used to set the output voltage between 1.1 V and 1.85 V. The
devices use a current-mode PWM architecture to drive two logic­level outputs at a programmable switching frequency that can be
optimized for VRM size and efficiency. The output signals are
180 degrees out of phase, allowing for the construction of two
complementary buck switching stages. These two stages share the
dc output current to reduce overall output voltage ripple. An
active current balancing function ensures that both phases carry
equal portions of the total load current, even under large transient
loads, to minimize the size of the inductors. The ADP3160 control

ADOPT is a trademark of Analog Devices, Inc.
Athlon is a trademark of Advanced Micro Devices, Inc.
Pentium is a registered trademark of Intel Corporation.

VID

DAC

VID4 VID3 VID2 VID1 VID0

loop has been optimized for conversion from 12 V, while the
ADP3167 is designed for conversion from a 5 V supply.

The ADP3160 and ADP3167 also use a unique supplemental
regulation technique called active voltage positioning to enhance
load transient performance. Active voltage positioning results
in a dc/dc converter that meets the stringent output voltage
specifications for high-performance processors, with the minimum
number of output capacitors and smallest footprint. Unlike
voltage-mode and standard current-mode architectures, active
voltage positioning adjusts the output voltage as a function of
the load current so that it is always optimally positioned for a
system transient. They also provide accurate and reliable short
circuit protection and adjustable current limiting.

The ADP3160 is specified over the commercial temperature
range of 0∞C to 70∞C and is available in a 16-lead narrow body
SOIC package.

REV.B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]www.analog.com
Fax: [phone] © Analog Devices, Inc., 2002

ADP3160/ADP3167–SPECIFICATIONS

(VCC = 12 V, I

1

unless otherwise noted.)

= 150 ␮A, TA = 0ⴗC to 70ⴗC,

REF

Parameter Symbol Conditions Min Typ Max Unit

FEEDBACK INPUT

Accuracy V

FB

1.1 V Output See Figure 1 1.091 1.1 1.109 V

1.475 V Output See Figure 1 1.463 1.475 1.487 V

1.85 V Output See Figure 1 1.835 1.85 1.865 V

Line Regulation ⌬V
Input Bias Current I

FB

Crowbar Trip Threshold V

FB

CROWBAR

VCC = 10 V to 14 V 0.05 %

550 nA

Percent of Nominal Output 114 124 134 %
Crowbar Reset Threshold Percent of Nominal Output 50 60 70 %
Crowbar Response Time t

CROWBAR

Overvoltage to PWM Going Low 300 ns

REFERENCE

Output Voltage V
Output Current I

REF

REF

2.952 3.0 3.048 V
300 mA

VID INPUTS

Input Low Voltage V
Input High Voltage V
Input Current I
Pull-Up Resistance R

IL(VID)

IH(VID)

VID

VID

2.2 V

VID(X) = 0 V 180 250 mA

20 28 kW

0.6 V

Internal Pull-Up Voltage 4.5 5.0 5.5 V

OSCILLATOR

Maximum Frequency
Frequency Variation ⌬f
CT Charge Current I

2

f

CT(MAX)

CT

CT

2000 kHz
TA = 25∞C, CT = 91 pF 430 500 570 kHz
TA = 25∞C, VFB in Regulation 130 150 170 mA
TA = 25∞C, VFB = 0 V 263646 mA

ERROR AMPLIFIER

Output Resistance R
Transconductance g
Output Current I
Maximum Output Voltage V
Output Disable Threshold V

O(ERR)

m(ERR)

O(ERR)

COMP(MAX)

COMP(OFF)

2.0 2.2 2.45 mmho
VFB = 0 V 1 mA
FB Forced to V

– 3% 3.0 V

OUT

ADP3160 560 720 800 mV

200 kW

ADP3167 640 800 880 mV

–3 dB Bandwidth BW

ERR

COMP = Open 500 kHz

CURRENT SENSE

Current Limit Threshold Voltage V

CS(CL)

ADP3160, CS+ = VCC 142 157 172 mV
FB Forced to V

OUT

– 3%
ADP3167, CS+ = VCC 69 79 89 mV
FB Forced to V

OUT

– 3%

0.8 V £ COMP £ 1 V 0 15 mV

Current Limit Foldback Voltage V

CS(FOLD)

ADP3160, FB £ 375 mV 75 95 115 mV
ADP3167, FB £ 750 mV 37 47 58 mV

COMP

/DV

CS

DV

Input Bias Current I
Response Time t

n

I

CS+

CS

, I

CS–

ADP3160, 1 V £ V
ADP3167, 1 V £ V

£ 3 V 12.5 V/V

COMP

£ 3 V 25 V/V

COMP

CS+ = CS– = VCC 0.5 5 mA
ADP3160, CS+ – (CS–) ≥ 172 mV 50 ns
to PWM Going Low
ADP3167, CS+ – (CS–) ≥ 89 mV 50 ns
to PWM Going Low

POWER GOOD COMPARATOR

Undervoltage Threshold V
Overvoltage Threshold V
Output Voltage Low V

PWRGD(UV)

PWRGD(OV)

OL(PWRGD)IPWRGD(SINK)

% Nominal Output 76 82 88 %
% Nominal Output 114 124 134 %

= 100 mA30200 mV

Response Time FB Going High 2 ms

FB Going Low 200 ns

REV. B–2–

ADP3160/ADP3167

Parameter Symbol Conditions Min Typ Max Unit

PWM OUTPUTS

Output Voltage Low V
Output Voltage High V
Output Current I
Duty Cycle Limit

2

OL(PWM)

OH(PWM)

PWM

D

MAX

SUPPLY

DC Supply Current

Normal Mode I
UVLO Mode I

UVLO Threshold Voltage V

CC

CC(UVLO)

UVLO

UVLO Hysteresis 0.1 0.4 0.6 V

NOTES

1

All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.

2

Guaranteed by design, not tested in production.

Specifications subject to change without notice.

I

PWM(SINK)

I

PWM(SOURCE)

= 400 mA 100 500 mV

= 400 mA 4.0 V

Per Phase, Relative to f

VCC £ V

, VCC Rising 220 400 mA

UVLO

CT

0.4 1 mA
50 %

3.8 5.5 mA

5.9 6.4 6.9 V

REV. B

–3–

ADP3160/ADP3167

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +15 V

CS+, CS– . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V

All Other Inputs and Outputs . . . . . . . . . . . . –0.3 V to +10 V

Operating Ambient Temperature Range . . . . . . . 0∞C to 70∞C

Operating Junction Temperature . . . . . . . . . . . . . . . . . . 125∞C

Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C

␪

JA

Two-Layer Board . . . . . . . . . . . . . . . . . . . . . . . . . . 125∞C/W

Four-Layer Board . . . . . . . . . . . . . . . . . . . . . . . . . . 81∞C/W

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300∞C

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 215∞C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220∞C

*This is a stress rating only; operation beyond these limits can cause the device to

be permanently damaged. Unless otherwise specified, all voltages are referenced
to GND.

PIN CONFIGURATION

VID4

VID3

VID2

VID1

VID0

COMP

FB

CT

1

2

3

ADP3160/

ADP3167

4

TOP VIEW

5

(Not to Scale)

6

7

8

16

15

14

13

12

11

10

9

VCC

REF

CS–

PWM1

PWM2

CS+

PWRGD

GND

PIN FUNCTION DESCRIPTIONS

Pin Mnemonic Function

1–5 VID4– Voltage Identification DAC Inputs.

VID0 These pins are pulled up to an internal

reference, providing a Logic 1 if left open.
The DAC output programs the FB regula­tion voltage from 1.1 V to 1.85 V. Leaving
all five DAC inputs open results in the
ADP3160/ADP3167 going into a “No
CPU” mode, shutting off its PWM outputs.

6 COMP Error Amplifier Output and Compensation

Point. The voltage at this output programs
the output current control level between
CS+ and CS–.

7FB Feedback Input. Error amplifier input for

remote sensing of the output voltage.

8CT External Capacitor CT Connection to

ground sets the frequency of the device.

9GND Ground. All internal signals of the ADP3160/

ADP3167 are referenced to this ground.

10 PWRGD Open-Drain Output that signals when the

output voltage is in the proper operating range.

11 CS+ Current Sense Positive Node. Positive input

for the current comparator. The output
current is sensed as a voltage at this pin with

respect to CS–.
12 PWM2 Logic-Level Output for Phase 2 Driver
13 PWM1 Logic-Level Output for Phase 1 Driver
14 CS– Current Sense Negative Node. Negative

input for the current comparator.
15 REF 3.0 V Reference Output
16 VCC Supply Voltage for the ADP3160/ADP3167.

ORDERING GUIDE

Temperature Package

Model Range Description Package Option

ADP3160JR 0∞C to 70∞CNarrow Body SOIC R-16A (SO-16)
ADP3167JR 0∞C to 70∞CNarrow Body SOIC R-16A (SO-16)

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADP3160/ADP3167 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

REV. B–4–

ADP3160/ADP3167

ADP3160/ADP3167

VCC

REF

CS–

PWM1

PWM2

CS+

PWRGD

GND

16

15

14

13

12

11

10

1.2V

+

1␮F

20k⍀

9

5-BIT CODE

100⍀

100nF

1

2

3

4

5

6

7

8

AD820

VID4

VID3

VID2

VID1

VID0

COMP

FB

CT

Figure 1. Closed-Loop Output Voltage Accuracy
Test Circuit

10000

4.10

12V

100nF

V

FB

4.05

4.00

3.95

SUPPLY CURRENT – mA

3.90

3.85
0 2000

250 500 750 1250 1500 1750

OSCILLATOR FREQUENCY – kHz

1000

Figure 3. Supply Current vs. Oscillator Frequency

16

TA = 25ⴗC

= 1.6V

V

OUT

12

1000

OSCILLATOR FREQUENCY – kHz

100

0

100

200 300 400 500

CT CAPACITOR – pF

Figure 2. Oscillator Frequency vs. Timing Capacitor

8

NUMBER OF PARTS – %

4

0

–1 1

OUTPUT ACCURACY – % of Nominal

0

Figure 4. Output Accuracy Distribution

REV. B

–5–

ADP3160/ADP3167

THEORY OF OPERATION

The ADP3160 and ADP3167 combine a current-mode, fixed
frequency PWM controller with antiphase logic outputs in a
controller for a 2-phase synchronous buck power converter.
Two-phase operation is important for switching the high currents
required by high-performance microprocessors. Handling the
high current in a single-phase converter would place difficult
requirements on the power components such as inductor wire
size, MOSFET ON resistance, and thermal dissipation. Their
high-side current sensing topology ensures that the load currents
are balanced in each phase, such that neither phase has to carry
more than half of the power. An additional benefit of high-

side
current sensing over output current sensing is that the average
current through the sense resistor is reduced by the duty cycle
of the converter, allowing the use of a lower power, lower cost
resistor. The outputs of the ADP3160/ADP3167 are logic
drivers only and are not intended to drive external power
MOSFETs directly. Instead, the ADP3160/ADP3167
be paired with drivers such as the ADP3414 or ADP3417.

should

A
system level block diagram of a 2-phase power supply for high
current CPUs is shown in Figure 5.

The frequency of the device is set by an external capacitor
connected to the CT pin. Each output phase operates at half of
the frequency set by the CT pin. The error amplifier and
current sense comparator control the duty cycle of the PWM
outputs to maintain regulation. The maximum duty cycle per
phase is inherently limited to 50% because the PWM outputs
toggle in 2-phase operation. While one phase is on, the other
phase is off. In no case can both outputs be high at the same time.

Output Voltage Sensing

The output voltage is sensed at the FB pin allowing for remote
sensing. To maintain the accuracy of the remote sensing, the
GND pin should also be connected close to the load. A voltage
error amplifier (g

) amplifies the difference between the output

m

voltage and a programmable reference voltage. The reference volt­age is programmed between 1.1 V and 1.85 V by an internal 5-bit
DAC that reads the code at the voltage identification (VID) pins.
Refer to Table I for the output voltage versus VID pin code
information.

Active Voltage Positioning

The ADP3160 and ADP3167 use Analog Devices Optimal
Positioning Technology (ADOPT), a unique supplemental
regulation technique that uses active voltage positioning and
provides optimal compensation for load transients. When imple­mented, ADOPT adjusts the output voltage as a function of the
load current, so that it is always optimally positioned for a load
transient. Standard (passive) voltage positioning has poor dynamic
performance, rendering it ineffective under the stringent repetitive
transient conditions required by high-performance processors.
ADOPT, however, provides optimal bandwidth for transient
response that yields optimal load transient response with the
minimum number of output capacitors.

Reference Output

A 3.0 V reference is available and is commonly used to set the
voltage positioning accurately using a resistor divider to the
COMP pin. In addition, the reference can be used for other
functions such as generating a regulated voltage with an external
amplifier. The reference is bypassed with a 1 nF capacitor to
ground. It is not intended to supply current to large capacitive
loads, and it should not be used to provide more than 1 mA of
output current.

Cycle-by-Cycle Operation

During normal operation (when the output voltage is regulated), the
voltage-error amplifier and the current comparator are the main
control elements. The voltage at the CT pin of the oscillator ramps
between 0 V and 3 V. When that voltage reaches 3 V, the oscillator
sets the driver logic, which sets PWM1 high. During the ON time
of Phase 1, the driver IC turns on the high-side MOSFET. The CS+
and CS– pins monitor the current through the sense resistor that
feeds both high-side MOSFETs. When the voltage between the
two pins exceeds the threshold level set by the voltage error ampli-

), the driver logic is reset and the PWM output goes low.

fier (g

m

This signals the driver IC to turn off the high-side MOSFET and
turn on the low-side MOSFET. On the next cycle of the oscillator,
the driver logic toggles and sets PWM2 high. On each following
cycle of the oscillator, the outputs toggle between PWM1 and
PWM2. In each case, the current comparator resets the PWM
output low when the current comparator threshold is reached. As
the load current increases, the output voltage starts to decrease.
This causes an increase in the output of the g

amplifier, which in

m

turn leads to an increase in the current comparator threshold,
thus programming more current to be delivered to the output so
that voltage regulation is maintained.

5V
OR
12V

VID INPUTS

ADP3160/

ADP3167

2-PHASE

SYNCHRONOUS

BUCK

CONTROLLER

5V

I

PWM1

PWM2

ADP3412

SYNCHRONOUS

DRIVER

5V

ADP3412

SYNCHRONOUS

DRIVER

5V OR 12V

L1

OUT

+

I

L2

I

PWM2

PWM1

OUT

I

L2

Figure 5. 2-Phase CPU Supply System Level Block Diagram

I

L1

REV. B–6–