Analog Devices ADP3166 Datasheet

5-Bit Programmable 2-, 3-, 4-Phase

Synchronous Buck Controller

FEATURES
Selectable 2-, 3- or 4-Phase Operation at up to

1 MHz per Phase

Differential Sensing Error ±1% over Temperature
Logic-Level PWM Outputs for Interface to

External High Power Drivers
Active Current Balancing between All Output Phases
Built-in Power Good Blanking Supports On-the-Fly

VID Code Changes
5-Bit Digitally Programmable 0.8 V to 1.55 V Output
Short-Circuit Protection with Programmable

Latch-Off Delay
Overvoltage Protection Crowbar Logic Output

APPLICATIONS
Desktop PC Power Supplies

Next-Generation AMD Processors

VRM Modules

GENERAL DESCRIPTION

The ADP3166 is a highly efficient, multiphase, synchronous
buck switching regulator controller optimized for converting a
12 V main supply into the core supply voltage required by high
performance AMD processors. It uses an internal 5-bit DAC to
read a

voltage identification (VID) code directly from the pro­cessor, which is used to set the output voltage between 0.8 V
and 1.55 V. The ADP3166 also uses a multimode PWM
archi

tecture to drive the logic-level outputs at a programmable
switching frequency that can be optimized for VRM size and
efficiency. The phase relationship of the output signals can be
programmed to provide 2-, 3-, or 4-phase operation, allowing
for the construction of up to four complementary buck switch­ing stages.

The ADP3166 includes programmable no-load offset and slope
functions to adjust the output voltage as a function of the load
current so that it is always optimally positioned for a system
transient. The ADP3166 also provides accurate and reliable
short-circuit protection, adjustable current limiting, and a delayed
power good output that accommodates on-the-fly output volt­age changes requested by the CPU.

ADP3166 is specified over the commercial temperature range of
0°C to 85°C and is available in a 28-lead TSSOP package.

GND

CROWBAR

PWRGD

ILIMIT

DELAY

COMP

EN

ADP3166

FUNCTIONAL BLOCK DIAGRAM

ADP3166

11

19

6

CSREF

DAC + 300mV

CSREF

DAC – 300mV

10

15

EN

12

9

VCC

28

UVLO

SHUTDOWN

AND BIAS

+
–

2.1V

+

–

+

–

DELAY

SOFT

START

PRECISION

REFERENCE

7 1 2 3 4 5

VID4 VID3 VID2 VID1 VID0FBRTN

RTRAMPADJ

14

13

OSCILLATOR

CURRENT

BALANCING

CIRCUIT

CURRENT

CIRCUIT

VID

DAC

LIMIT

+

CMP

–

+

CMP

–

+

CMP

–

+

CMP

–

CROWBAR

–

+

+
–

ENSET

RESET

RESET
2-, 3- , 4-PHASE

DRIVER LOGIC
RESET

RESET

CURRENT
LIMIT

–
+

27

26

25

24

23

22

21

20

17

16

18

8

*

PWM1

PWM2

PWM3

PWM4

SW1

SW2

SW3

SW4

CSSUM

CSREF

CSCOMP

FB

*Patent pending

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

ADP3166–SPECIFICATIONS

Parameter Symbol Conditions Min Typ Max Unit

ERROR AMPLIFIER

Accuracy V

0.8 V Output

1.175 V Output

1.55 V Output

Line Regulation ∆V
Input Bias Current I
FBRTN Current I
Output Current I
Gain Bandwidth Product GBW
Slew Rate C

VID INPUTS

Input Low Voltage V
Input High Voltage V
Input Current I
Pull-Up Resistance R
Internal Pull-Up Voltage 2.0 2.4 2.65 V
VID Transition Delay Time
No CPU Detection Turn-Off VID code change to 11111 to 400 ns

Delay Time

OSCILLATOR

Frequency Range

2

2

2

Frequency Variation f

Output Voltage V
Timing Resistor Value 500 kΩ
RAMPADJ Voltage V
RAMPADJ Input Current Range I

CURRENT SENSE AMPLIFIER

Offset Voltage V
Input Bias Current I
Gain Bandwidth Product GBW
Slew Rate C
Input Common-Mode Range CSSUM and CSREF 0 3 V
Positioning Accuracy ∆V
Output Voltage Range I
Output Current I

CURRENT BALANCE CIRCUIT

Common-Mode Range V
Input Resistance R
Input Current I
Input Current Matching ∆I

CURRENT LIMIT COMPARATOR

Output Voltage

Normal Mode V
In Shutdown V

Output Current, Normal Mode I
Maximum Output Current EN > 2 V 60 µA
Current Limit Threshold Voltage V
Current Limit Setting Ratio V
Latch-Off Delay Threshold V
Latch-Off Delay Time t

FB

FB

FB

FBRTN

O(ERR)

(ERR)

IL(VID)

IH(VID)

VID

VID

f

OSC

PHASE

RT

RAMPADJ

RAMPADJ

OS(CSA)

BIAS(CSA)

CSA

FB

CSCOMP

SW(X)CM

SW(X)

SW(X)

SW(X)

ILIMIT(NM)

ILIMIT(SD)

ILIMIT(NM)

CL

SET(DLY)

SET(DLY)

(VCC = 12 V, FBRTN = GND, TA = 0ⴗC to 85ⴗC, unless otherwise noted.)

Referenced to FBRTN, CSSUM = CSCOMP,

0.792 0.800 0.808 V
See Test Circuit 1
Referenced to FBRTN, CSSUM = CSCOMP,

1.163 1.175 1.187 V
See Test Circuit 1
Referenced to FBRTN, CSSUM = CSCOMP,

1.535 1.55 1.566 V
See Test Circuit 1
VCC = 10 V to 14 V 0.05 %

–13 –15.5 –17 µA

100 200 µA

FB forced to V

– 3% 500 µA

OUT

COMP = FB 20 MHz

= 10 pF 50 V/µs

COMP

0.8 V

2V

VID(X) = 0 V 20 26 µA

100 120 kΩ

VID code change to FB change 400 ns

PWM going low

0.25 4 MHz
TA = 25°C, RT = 250 kΩ, 4-phase 160 200 240 kHz
T

= 25°C, RT = 115 kΩ, 4-phase

A

= 25°C, RT = 75 kΩ, 4-phase

T

A

2

2

400 kHz
600 kHz

RT = 100 kΩ to GND 1.9 2.0 2.1 V

RAMPADJ – FB –50 +50 mV

050µA

CSSUM – CSREF, see Test Circuit 2 –3 +3 mV

20 100 nA
20 MHz

= 10 pF 50 V/µs

CSCOMP

See Test Circuit 3 –76 –80 –84 mV

= ±100 µA 0.05 3.3 V

CSCOMP

500 µA

–600 +200 mV

SW(X) = 0 V 24 30 36 kΩ
SW(X) = 0 V 5 7 9 µA
SW(X) = 0 V –5 +5 %

EN > 2 V 2.9 3 3.1 V
EN < 0.8 V, I
EN > 2 V, R

V

– V

CSREF

CL/IILIMIT

CSCOMP

= –100 µA 400 mV

ILIMIT

= 250 kΩ 12 µA

ILIMIT

, R

= 250 kΩ 105 125 145 mV

ILIMIT

10.4 mV/µA

In current limit 1.7 1.8 1.9 V
R

= 250 kΩ, C

DELAY

= 4.7 nF 600 µs

DELAY

1

REV. 0–2–

ADP3166

Parameter Symbol Conditions Min Typ Max Unit

SOFT START

Output Current, Soft Start Mode I
Soft Start Delay Time t

DELAY(SS)

DELAY(SS)

ENABLE INPUT

Input Low Voltage V
Input High Voltage V

IL(EN)

IH(EN)

Input Current –1 +1 µA

POWER GOOD COMPARATOR

Undervoltage Threshold V
Overvoltage Threshold V
Output Low Voltage V

PWRGD(UV)

PWRGD(OV)

OL(PWRGD)IPWRGD(SINK)

Off-State Leakage Current V
Delay Time

VID Code Changing 100 250 µs
VID Code Static 400 ns

CROWBAR COMPARATOR

Crowbar Trip Point V

CROWBAR

Crowbar Reset Point 300 400 500 mV
Crowbar Response Time t

CROWBAR

Overvoltage to PWM Low 400 ns

Overvoltage to CRWBR High 400 ns
Output Voltage Low V
Output Voltage High V

OL(CROWBAR)ICROWBAR(SINK)

OH(CROWBAR)ICROWBAR(SOURCE)

PWM OUTPUTS

Output Voltage Low V
Output Voltage High V

OL(PWM)

OH(PWM)

SUPPLY

DC Supply Current I
UVLO Threshold Voltage V

CC

UVLO

UVLO Hysteresis 0.7 0.9 1.1 V

During start-up, DELAY < 2.8 V 15 20 25 µA
R

= 250 kΩ, C

DELAY

= 4.7 nF 350 µs

DELAY

VID Code = 01111

0.8 V

2V

Relative to nominal DAC output –200 –300 –400 mV
Relative to nominal DAC output 200 300 400 mV

= 4 mA 150 400 mV

CSREF

= V

DAC

50 µA

2.0 2.1 2.2 V

= 100 µA 100 500 mV

= 100 µA 4.0 5.0 V

I

PWM(SINK)

I

PWM(SOURCE)

= 400 µA 160 500 mV

= 400 µA 4.0 5.0 V

710 mA

VCC rising 6.5 6.9 7.3 V

NOTES

1

All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC).

2

Guaranteed by design, not tested in production.

Specifications subject to change without notice.

REV. 0

–3–

ADP3166

ABSOLUTE MAXIMUM RATINGS*

VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +15 V

FBRTN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

VID0 to VID4, EN, DELAY, ILIMIT, CSCOMP, RT, COMP,

CROWBAR, PWM1 to PWM4 . . . . . . . . . –0.3 V to +5.5 V

SW1 to SW4 . . . . . . . . . . . . . . . . . . . . . . . . . . . –5 V to +25 V

All Other Inputs and Outputs . . . . . . .–0.3 V to VCC + 0.3 V

Operating Ambient Temperature Range . . . . . . . 0°C to 85°C

Operating Junction Temperature . . . . . . . . . . . . . . . . . . 125°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100°C/W

␪

JA

ORDERING GUIDE

Temperature Package Quantity

Model Range Options per Reel

ADP3166JRU-REEL7 0°C to 85°C RU-28 (TSSOP-28) 1000
ADP3166JRU-REEL 0°C to 85°C RU-28 (TSSOP-28) 2500

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only. Functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Absolute maximum
ratings apply individually only, not in combination. Unless otherwise specified, all
other voltages are referenced to GND.

5.3
TA = 25ⴗC
4-PHASE OPERATION

5.2

5.1

5.0

4.9

4.8

SUPPLY CURRENT – mA

4.7

4.6

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

MASTER CLOCK FREQUENCY – MHz

TPC 1. Supply Current vs. Master Clock Frequency

4

3

2

1

MASTER CLOCK FREQUENCY – MHz

0

050100 150 200 250 300

RT VALUE – kΩ

TPC 2. Master Clock Frequency vs. R

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADP3166 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

T

REV. 0–4–

ADP3166

ADP3166

VCC

PWM1

PWM2

PWM3

PWM4

SW1

SW2

SW3

SW4

GND

CSCOMP

CSSUM

CSREF

ILIMIT

28

27

26

25

24

23

22

21

20

19

18

17

16

15

250k⍀

+

1␮F

20k⍀

12V

100nF

100nF

5-BIT CODE

4.7nF

1.25V

1k⍀

250k⍀

1

VID4

2

VID3

3

VID2

4

VID1

5

VID0

6

CROWBAR

7

FBRTN

8

FB

9

COMP

10

PWRGD

11

EN

12

DELAY

13

RT

14

RAMPADJ

Test Circuit 1. Closed-Loop Output Voltage Accuracy

ADP3166

VCC

200k⍀

28

FB

8

COMP

9

CSCOMP

18

CSSUM

17

CSREF

16

GND

19

–

+

⌬VFB = FB – V

VID

200k⍀

80mV

1V

12V

10k⍀

+
–

+
–

Test Circuit 3. Positioning Voltage Test Circuit

ADP3166

VCC

100nF

28

CSCOMP

18

CSSUM

17

CSREF

16

GND

19

–

+

VOS =

CSCOMP – 1V

40

12V

39k⍀

1k⍀

1V

+
–

Test Circuit 2. Positioning Amplifier VOS Test Circuit

REV. 0

–5–

ADP3166

PIN CONFIGURATION

RU-28

1

VID4 VCC

2

VID3 PWM1

3

VID2 PWM2

VID1 PWM3

VID0 PWM4

CROWBAR SW1

FBRTN SW2

FB SW3

COMP SW4

PWRGD GND

EN CSCOMP

DELAY CSSUM

RT CSREF

RAMPADJ ILIMIT

4

5

6

7

8

9

10

11

12

13

14

ADP3166

TOP VIEW

(Not to Scale)

28

27

26

25

24

23

22

21

20

19

18

17

16

15

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Function

1–5 VID4–VID0

Voltage Identification DAC Inputs. These five pins are pulled up to an internal reference, providing a
logic 1 if left open. When in normal operation mode, the DAC output programs the FB regulation voltage
from 0.8 V to 1.55 V. Leaving VID4 through VID0 open results in the ADP3166 going into a “No CPU”
mode, shutting off its PWM outputs.

6 CROWBAR Crowbar Output. This logic-level output can be used to control an external device to short the 12 V supply

to ground to protect the CPU from overvoltage if CSREF exceeds 2.1 V.

7 FBRTN Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage.

8FB Feedback Input. Error amplifier input for remote sensing of the output voltage. A resistor between this pin

and the output voltage sets the no-load offset point.

9 COMP Error Amplifier Output and Compensation Point.

10 PWRGD Power Good Output. Open-drain output that pulls to GND when the output voltage is outside of the

proper operating range.

11 EN Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs.

12 DELAY Soft Start Delay and Current Limit Latch-Off Delay Setting Input. A resistor and capacitor connected

between this pin and GND sets the soft start ramp-up time and the overcurrent latch-off delay time.

13 RT Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the oscil-

lator frequency of the device.

14 RAMPADJ

PWM Ramp Current Input. A resistor from the converter input voltage to this pin sets the internal PWM ramp.

15 ILIMIT Current Limit Set Point/Enable Output. A resistor from this pin to GND sets the current limit threshold of

the converter. This pin is actively pulled low when the ADP3166 EN input is low, or when VCC is below
its UVLO threshold to signal to the driver IC that the driver high-side and low-side outputs should go low.

16 CSREF Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current

sense amplifiers and the Power Good and Crowbar functions. This pin should be connected to the com­mon point of the output inductors.

17 CSSUM Current Sense Summing Node. Resistors from each switch node to this pin sum the average inductor cur-

rents together to measure the total output current.

18 CSCOMP Current Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determine the slope

of the load line and the positioning loop response time.

19 GND Ground. All internal biasing and the logic output signals of the device are referenced to this ground.

20–23 SW4–SW1 Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused

phases should be grounded.

24–27 PWM4–PWM1 Logic-Level PWM Outputs. Each output is connected to the input of an external MOSFET driver such

as the ADP3413 or ADP3418. Connecting the PWM3 and/or PWM 4 outputs to GND will cause that
phase to turn off, allowing the ADP3166 to operate as a 2-, 3-, or 4-phase controller.

28 VCC Supply Voltage for the Device.

REV. 0–6–