Analog Devices ADP3161 Datasheet

4-Bit Programmable 2-Phase
a
FEATURES ADOPT™ Optimal Positioning Technology for Superior
Load Transient Response and Fewest Output
Capacitors Active Current Balancing Between Both Output Phases VRM 8.4-Compatible Digitally Programmable 1.3 V to
2.05 V Output
Dual Logic-Level PWM Outputs for Interface to External
High-Power Drivers Total Output Accuracy 0.8% Over Temperature Current-Mode Operation Short Circuit Protection Power-Good Output Overvoltage Protection Crowbar Protects
Microprocessors with No Additional
External Components
APPLICATIONS Desktop PC Power Supplies for:
Intel Pentium
VRM Modules
®
III Processors
Synchronous Buck Controller
ADP3161
FUNCTIONAL BLOCK DIAGRAM
VCC
CROWBAR
CMP
CMP1
SET
RESET
CMP3
CMP2
CMP
2-PHASE
DRIVER
LOGIC
DAC+24%
DAC–18%
g
m
REF
GND
COMP
CT
UVLO
& BIAS
3.0V
REFERENCE
OSCILLATOR
ADP3161
PWM1
PWM2
PWRGD
CS–
CS+
FB
GENERAL DESCRIPTION
The ADP3161 is a highly efficient dual output synchronous buck switching regulator controller optimized for converting a 5 V or 12 V main supply into the core supply voltage required by high­performance processors such as Pentium
®
III. The ADP3161 uses an internal 4-bit DAC to read a voltage identification (VID) code directly from the processor, which is used to set the output voltage between 1.3 V and 2.05 V. The ADP3161 uses a current mode PWM architecture to drive two logic-level outputs at a programmable switching frequency that can be optimized for VRM size and efficiency. The output signals are 180 degrees out of phase, allowing for the construction of two complementary buck switching stages. These two stages share the dc output current to reduce overall output voltage ripple. An active current bal­ancing function ensures that both phases carry equal portions of the total load current, even under large transient loads, to minimize the size of the inductors.
ADOPT is a trademark of Analog Devices Inc. Pentium is a registered trademark of Intel Corporation
VID
DAC
VID3 VID2 VID1 VID0
The ADP3161 also uses a unique supplemental regulation tech­nique called active voltage positioning to enhance load transient performance. Active voltage positioning results in a dc/dc con­verter that meets the stringent output voltage specifications for high-performance processors, with the minimum number of output capacitors and smallest footprint. Unlike voltage-mode and standard current-mode architectures, active voltage positioning adjusts the output voltage as a function of the load current so that it is always optimally positioned for a system transient. The ADP3161 also provides accurate and reliable short circuit protec­tion and adjustable current limiting.
The ADP3161 is specified over the commercial temperature range of 0°C to 70°C and is available in a 16-lead narrow body SOIC package.
REV. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
1
ADP3161–SPECIFICATIONS
(VCC = 12 V, I
Parameter Symbol Conditions Min Typ Max Unit
FEEDBACK INPUT
Accuracy V
FB
1.3 V Output TPC 1 1.290 1.3 1.310 V
1.6 V Output TPC 1 1.587 1.6 1.613 V
2.05 V Output TPC 1 2.034 2.05 2.066 V
Line Regulation ∆V Input Bias Current I
FB
Crowbar Trip Point V
FB
CROWBAR
VCC = 10 V to 14 V 0.05 %
Percent of Nominal Output 114 124 134 % Crowbar Reset Point Percent of Nominal Output 50 60 70 % Crowbar Response Time t FB Low Comparator Threshold V
CROWBAR
FB(LOW)
Overvoltage to PWM Going Low 300 ns
REFERENCE
Output Voltage V Output Current I
REF
REF
VID INPUTS
Input Low Voltage V Input High Voltage V Input Current I Pull-Up Resistance R
IL(VID)
IH(VID)
VID
VID
VID(X) = 0 V 180 250 µA
Internal Pull-Up Voltage 4.5 5.0 5.5 V
OSCILLATOR
Maximum Frequency Frequency Variation ∆f CT Charge Current I
2
f
CT(MAX)
CT
CT
TA = 25°C, CT = 91 pF 430 500 570 kHz
TA = 25°C, VFB in Regulation 130 150 170 µA
TA = 25°C, VFB = 0 V 263646 µA
ERROR AMPLIFIER
Output Resistance R Transconductance g Output Current I Maximum Output Voltage V Output Disable Threshold V –3 dB Bandwidth BW
O(ERR)
m(ERR)
O(ERR)
COMP(MAX)
COMP(OFF)
ERR
VFB = 0 V 1 mA
FB Forced to V
COMP = Open 500 kHz
CURRENT SENSE
Threshold Voltage V
CS(TH)
CS+ = VCC, 69 79 89 mV
FB Forced to V
0.8 V COMP 1 V 0 15 mV
FB 375 mV 37 47 58 mV
1 V ≤ V
COMP
CS+ = CS– = VCC 0.5 5 µA
CS+ – (CS–) 89 mV 50 ns
V
COMP
/V
CS
Input Bias Current I Response Time t
V
CS(FOLD)
n
i
, I
CS+
CS
CS–
to PWM Going Low
POWER GOOD COMPARATOR
Undervoltage Threshold V Overvoltage Threshold V Output Voltage Low V
PWRGD(UV)
PWRGD(OV)
OL(PWRGD)IPWRGD(SINK)
Percent of Nominal Output 76 82 88 %
Percent of Nominal Output 114 124 134 %
Response Time FB Going High 2 µs
FB Going Low 200 ns
PWM OUTPUTS
Output Voltage Low V Output Voltage High V Output Current I Duty Cycle Limit
2
OL(PWM)
OH(PWM)
PWM
DC Per Phase, Relative to f
I
PWM(SINK)
I
PWM(SOURCE)
= 150 A, TA = 0C to 70C, unless otherwise noted.)
REF
550 nA
375 425 500 mV
2.952 3.0 3.048 V 300 µA
0.6 V
2.2 V
20 28 k
2000 kHz
200 k
2.0 2.2 2.45 mmho
– 3% 3.0 V
OUT
560 720 800 mV
– 3%
OUT
3 V 25 V/V
= 100 µA 30 200 mV
= 400 µA 100 500 mV
= 400 µA 4.5 5.0 5.5 V
0.4 1 mA
CT
50 %
–2– REV. 0
ADP3161
WARNING!
ESD SENSITIVE DEVICE
Parameter Symbol Conditions Min Typ Max Unit
SUPPLY
DC Supply Current
Normal Mode I UVLO Mode I
UVLO Threshold Voltage V
CC
CC(UVLO)
UVLO
VCC V
, VCC Rising 220 400 µA
UVLO
UVLO Hysteresis 0.1 0.4 0.6 V
NOTES
1
All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.
2
Guaranteed by design, not tested in production.
Specifications subject to change without notice.
3.8 5.5 mA
5.9 6.4 6.9 V
ABSOLUTE MAXIMUM RATINGS*
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +15 V
CS+, CS– . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V
All Other Inputs and Outputs . . . . . . . . . . . . –0.3 V to +10 V
Operating Ambient Temperature Range . . . . . . . 0°C to 70°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . 125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
θ
JA
Two-Layer Board . . . . . . . . . . . . . . . . . . . . . . . . . . 125°C/W
Four-Layer Board . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
*This is a stress rating only; operation beyond these limits can cause the device to
be permanently damaged. Unless otherwise specified, all voltages are referenced to GND.
ORDERING GUIDE
Temperature Package Package
Model Range Description Option
ADP3161JR 0°C to 70°C Narrow Body SOIC R-16A (SO-16)
PIN CONFIGURATION
R-16A
1
NC
VID3
2
3
VID2
4
VID1
VID0
5
COMP
6
7
FB
8
CT
NC = NO CONNECT
ADP3161
TOP VIEW
(Not to Scale)
16
15
14
13
12
11
10
9
VCC
REF
CS–
PWM1
PWM2
CS+
PWRGD
GND
PIN FUNCTION DESCRIPTIONS
Pin No. Name Function
1 NC No Connect. 2–5 VID3– Voltage Identification DAC Inputs.
VID0 These pins are pulled up to an internal refer-
ence, providing a Logic 1 if left open. The DAC output programs the FB regulation voltage from 1.3 V to 2.05 V.
6 COMP Error Amplifier Output and Compensation
Point. The voltage at this output programs the output current control level between CS+ and CS–.
7 FB Feedback Input. Error amplifier input for
remote sensing of the output voltage.
8 CT External capacitor CT connection to ground
sets the frequency of the device.
9 GND Ground. All internal signals of the ADP3161
are referenced to this ground.
10 PWRGD Open drain output that signals when the output
voltage is in the proper operating range.
11 CS+ Current Sense Positive Node. Positive input
for the current comparator. The output current is sensed as a voltage at this pin with
respect to CS–. 12 PWM2 Logic-level output for the phase 2 driver. 13 PWM1 Logic-level output for the phase 1 driver. 14 CS– Current Sense Negative Node. Negative
input for the current comparator. 15 REF 3.0 V Reference Output. 16 VCC Supply Voltage for the ADP3161.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3161 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
–3–REV. 0
ADP3161
4-BIT CODE
100
100nF
Typical Performance Characteristics
ADP3161
16
1
2
3
4
5
6
7
8
NC
VID3
VID2
VID1
VID0
COMP
FB
CT
VCC
REF
CS–
PWM1
PWM2
CS+
PWRGD
GND
15
14
13
12
11
10
9
+
1 F
100nF
NC = NO CONNECT
12V
4.10
4.05
4.00
3.95
V
FB
AD820
1.2V
TPC 1. Closed-Loop Output Voltage Accuracy Test Circuit
10000
1000
OSCILLATOR FREQUENCY – kHz
100
0
100
200 300 400 500
CT CAPACITOR – pF
TPC 2. Oscillator Frequency vs. Timing Capacitor
SUPPLY CURRENT – mA
3.90
3.85 250 500 750 1250 1500 1750
0 2000
OSCILLATOR FREQUENCY – kHz
1000
TPC 3. Supply Current vs. Oscillator Frequency
30
25
20
15
10
NUMBER OF PARTS – %
5
0 –0.5 0.5
OUTPUT ACCURACY – % OF NOMINAL
0
TA = 25⬚C
V
OUT
= 1.6V
TPC 4. Output Accuracy Distribution
5V
OR
12V
VID INPUTS
12V
ADP3161
2-PHASE
SYNCHRONOUS
BUCK
CONTROLLER
5V
I
L1
PWM1
PWM2
ADP3412
SYNCHRONOUS
DRIVER
5V
ADP3412
SYNCHRONOUS
DRIVER
5V OR 12V
OUT
+
I
L2
TPC 5. 2-Phase CPU Supply System Level Block Diagram
–4– REV. 0
I
OUT
I
L2
PWM2
PWM1
I
L1
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