Analog Devices ADP3155 Datasheet

5-Bit Programmable Triple Power Supply

a

Controller for Pentium® III Processors

FEATURES
Active Voltage Positioning with Gain and Offset

Adjustment

Optimal Compensation for Superior Load Transient

Response
VRM 8.2, VRM 8.3 and VRM 8.4-Compliant
5-Bit Digitally Programmable 1.3 V to 3.5 V Output
Dual N-Channel Synchronous Driver
Two Onboard Linear Regulator Controllers
Total Output Accuracy ⴞ1% Over Temperature
High Efficiency, Current-Mode Operation
Short Circuit Protection
Overvoltage Protection Crowbar Protects Micro-

processors, with No Additional External Components
Power Good Output
TSSOP-20 Package

APPLICATIONS
Desktop PC Power Supplies for:

Pentium II and Pentium III Processor Families

AMD-K6 Processors

VRM Modules

GENERAL DESCRIPTION

The ADP3155 is a highly efficient synchronous buck switching
regulator controller optimized for converting the 5 V main sup­ply into the core supply voltage required by the Pentium III and
other high performance processors. The ADP3155 uses an
internal 5-bit DAC to read a voltage identification (VID) code
directly from the processor, which is used to set the output
voltage between 1.3 V and 3.5 V. The ADP3155 uses a current­mode, constant off-time architecture to drive two external N­channel MOSFETs at a programmable switching frequency that
can be optimized for size and efficiency. It also uses a unique
supplemental regulation technique called active voltage position-
ing to enhance load transient performance.

Active voltage positioning results in a dc/dc converter that meets
the stringent output voltage specifications for Pentium II and
Pentium III processors, with the minimum number of output
capacitors and the smallest footprint. Unlike voltage-mode and
standard current-mode architectures, active voltage positioning
adjusts the output voltage as a function of the load current so
that it is always optimally positioned for a system transient.

The ADP3155 provides accurate and reliable short circuit pro­tection and adjustable current limiting. It also includes an inte­grated overvoltage crowbar function to protect the microprocessor
from destruction in case the core supply exceeds the nominal
programmed voltage by more than 15%.

Pentium is a registered trademark of Intel Corporation.
All other trademarks are the property of their respective holders.

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

ADP3155

FUNCTIONAL BLOCK DIAGRAM

DRIVE1 DRIVE2 PGND

V

CC

NONOVERLAP

SD

CMP

C

T

DRIVE

CROWBAR

IN

S

Q

R

V

T2

CMPT

OFF-TIME
CONTROL

ADP3155

OFF

CMPI

V

IN

SENSE–

DAC

VID4

The ADP3155 contains two linear regulator controllers that are
designed to drive external N-channel MOSFETs. These linear
regulators are used to generate the auxiliary voltages (AGP,
GTL, etc.) required in most motherboard designs, and have
been designed to provide a high bandwidth load-transient re­sponse. A pair of external feedback resistors sets each linear
regulator output voltage.

V

22mF

COMP

1mF

INLDO2

Q

LDO1

R5

R6
20kV

V

INLDO1

1mF

R3
R4

20kV

SD
CMP

CMP

ADP3155

V

LDO1

FB1

V

LDO2

FB2

VID0–VID4

5-BIT CODE

R1

R2

V

OLDO2

V

OLDO1

1mF

Q

C

V

LDO2

Figure 1. Typical Application

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1999

AGND

V

REF

+15%

CC

V

CC

SENSE+
SENSE–

V

+5%

V

+12V

DRIVE1

DRIVE2

PGND

AGND

PWRGD SENSE+

DELAY

V

REF

REF

–5%

T1

V

REF

g

m

VID1

VID2VID3

V

+5V

IN

C

+

Q1

Q2

150pF

C

T

REFERENCE

VID0

IN

L

R

1nF

SENSE–

1.20V

SENSE

2R

R

+

C

VLDO2
FB2

VLDO1
FB1

V

O

1.3V TO

3.5V

O

ADP3155–SPECIFICATIONS

(0ⴗC ≤ TA ≤ +70ⴗC, V

= 12 V, VIN = 5 V, unless otherwise noted)

CC

1

Parameter Symbol Conditions Min Typ Max Units

OUTPUT ACCURACY

1.3 V Output Voltage V

O

(Figure 13) 1.283 1.3 1.317 V

2.0 V Output Voltage 1.980 2.0 2.020 V

3.5 V Output Voltage 3.465 3.5 3.535 V

OUTPUT VOLTAGE LINE ∆V

O

I

= 10 A (Figure 2)

LOAD

REGULATION VIN = 4.75 V to 5.25 V 0.05 %

INPUT DC SUPPLY CURRENT

Normal Mode I
Shutdown T

2

Q

VSD = 0.6 V 4.1 5.5 mA

= +25°C, VID Pins Floating 140 250 µA

A

CURRENT SENSE THRESHOLD

VOLTAGE V

SENSE(TH)VSENSE–

VID0–VID4 THRESHOLD VID

(TH)

Forced to V

– 3% 125 145 165 mV

OUT

Low 0.6 V
High 2.0 V

VID0–VID4 INPUT CURRENT I

VID0–VID4 PULL-UP RESISTANCE R

PIN DISCHARGE CURRENT I

C

T

OFF-TIME t

DRIVER OUTPUT TRANSITION t

VID

VID

11

OFF

, t

R

F

TIME T

POSITIVE POWER GOOD TRIP POINT3V

NEGATIVE POWER GOOD TRIP POINT3V

POWER GOOD RESPONSE TIME t

CROWBAR TRIP POINT V

PWRGD

PWRGD

PWRGD

CROWBAR

VID = 0 V 110 220 µA

20 30 kΩ

T

= +25°C

A

V

in Regulation 65 µA

OUT

V

= 0 V 2 10 µA

OUT

C

= 150 pF 1.8 2.45 3.2 µs

T

CL = 7000 pF (Pins 17, 18)

= +25°C 120 200 ns

A

% Above Output Voltage 5 8 %

% Below Output Voltage –8 –5 %

500 µs

% Above Output Voltage 9 15 24 %

ERROR AMPLIFIER

OUTPUT IMPEDANCE RO

ERR

275 kΩ

ERROR AMPLIFIER

TRANSCONDUCTANCE g

m(ERR)

2.2 mmho

ERROR AMPLIFIER MINIMUM

OUTPUT VOLTAGE V

CMPMINVSENSE+

Forced to V

+ 3% 0.8 V

OUT

ERROR AMPLIFIER MAXIMUM

OUTPUT VOLTAGE V

CMPMAXVSENSE+

ERROR AMPLIFIER BANDWIDTH –3 dB BW

ERR

CMP = Open 500 kHz

Forced to V

– 3% 2.4 V

OUT

LINEAR REGULATOR FEEDBACK

CURRENT I

LINEAR REGULATOR V

OUTPUT VOLTAGE V

FB

, Figure 2, R3 = R5 = 20 kΩ

OLDO1

OLDO2

R4 = R6 = 35 kΩ, I

= 1 A 3.24 3.30 3.38 V

O

0.35 1 µA

SHUTDOWN (SD) PIN

Low Threshold SD
High Threshold SD
Input Current SD

NOTES

1

All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.

2

Dynamic supply current is higher due to the gate charge being delivered to the external MOSFETs.

3

The trip point is for the output voltage coming into regulation.

Specifications subject to change without notice.

L

H

IC

Part Active 0.6 V
Part in Shutdown 2.0 V

10 µA

–2–

REV. A

ADP3155

WARNING!

ESD SENSITIVE DEVICE

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Function

1–4, 20 VID1–VID4, Voltage Identification DAC Inputs. These pins are pulled up to an internal reference, providing a

VID0 Logic 1 if left open. The DAC output programs the SENSE– regulation voltage from 1.3 V to 3.5 V.

Leaving all five DAC inputs open results in placing the ADP3155 into shutdown.
5 AGND Analog Ground. All internal signals of the ADP3155 are referenced to this ground.
6 SD Shutdown. A logic high will place the ADP3155 in shutdown and disable both outputs. This pin is

internally pulled down.
7, 14 FB1, FB2 These pin are the feedback connections for the linear controllers. Connect each pin to the resistor

divider from each respective linear regulator output to set its output voltage.
8, 13 V
9 SENSE– Connects to the internal resistor divider that senses the output voltage. This pin is also the reference

10 SENSE+ The (+) input for the current comparator. The output current is sensed as a voltage at this pin with

11 C
12 CMP Error Amplifier output and compensation point. The voltage at this output programs the output cur-

15 PWRGD Power Good. An open drain signal indicates that the output voltage is within a ±5% regulation band.

16 V
17 DRIVE2 Gate Drive for the (bottom) synchronous rectifier N-channel MOSFET. The voltage at DRIVE2

18 DRIVE1 Gate Drive for the buck switch N-channel MOSFET. The voltage at DRIVE1 swings from ground to

19 PGND Power Ground. The drivers turn off the buck and synchronous MOSFETs by discharging their gate

LDO1

T

CC

, V

LDO2

Gate drives for the respective linear regulator N-channel MOSFETs.

input for the current comparator.

respect to SENSE–.

External capacitor CT connection to ground sets the off time of the device.

rent control level between the SENSE pins.

Supply Voltage to ADP3155.

swings from ground to V

V

.

CC

CC

.

capacitances to this pin. PGND should have a low impedance path to the source of the synchronous

MOSFET.

ABSOLUTE MAXIMUM RATINGS*

PIN CONFIGURATION

Input Supply Voltage (VCC) . . . . . . . . . . . . . . –0.3 V to +16 V

Shutdown Input Voltage . . . . . . . . . . . . . . . . –0.3 V to +16 V

Operating Ambient Temperature Range . . . . . 0°C to +70°C

Junction Temperature Range . . . . . . . . . . . . . 0°C to +150°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110°C/W

θ

JA

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . +300°C

*This is a stress rating only; operation beyond these limits can cause the device to

be permanently damaged.

ORDERING GUIDE

Temperature Package Package

VID1
VID2
VID3
VID4

AGND

SD

FB1

V

LDO1

SENSE–
SENSE+

1

2

3

4

5

ADP3155

TOP VIEW

6

(Not to Scale)

7

8

9

10

Model Range Description Option

ADP3155JRU 0°C to +70°C Thin Shrink Small RU-20

Outline (TSSOP)

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADP3155 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

20

19

18

17

16

15

14

13

12

11

VID0

PGND
DRIVE1
DRIVE2
V

CC

PWRGD
FB2
V

LDO2

CMP

C

T

REV. A

–3–

ADP3155

V

LDO1

+1.5V

RTN

SYSTEM

4A

mP

1mF

IRF3103

1000mF

22V

ESR = 25mV EACH

2200mF 33

L1

1.7mH

10BQ015

R

SENSE

5mV

ESR = 25mV EACH

470pF

R4
5kV

R3
20kV

2kV

1

2

3

4

5

6

7

8

9

10

VID1
VID2
VID3
VID4

AGND
SD
FB1

V
SENSE–

SENSE+

ADP3155

PGND
DRIVE1
DRIVE2

PWRGD

V

LDO1

VID0

V

FB2

LDO2

CMP

100kV

20

19

18

17

16

CC

15

14

13

12

11

C

T

200pF

1nF

22mF

1mF

Q1
IRL3803

Q2

IRL3803

R1
150kV

2kV

470pF

R2
39kV

C

T

C
2nF

COMP

220V

220V

Figure 2. Typical VRM8.2/8.3/8.4 Compliant Core DC/DC Converter Circuit

V

DRIVE1 DRIVE2 PGND

CC

18 17

AGND PWRGD

5

SENSE+

SENSE–

1516

910

REFERENCE

1mF

2200mF 3 6

Q4
IRLR3703

R6

21.7kV
R5

20kV

L2

1mH

1mF

1000mF

VIN +1.8V
VIN +12V

VIN +5V

+5V RTN

+12V RTN

V

O

2V
0–19A

RTN

V

INLDO2

+3.3V

V

LDO2

+2.5V

0–2A
RTN

SD

+ 5% V

DELAY

REF

– 5%

2R

1.20V

V

+ 15%

OFF

REF

V

REF

NONOVERLAP

6

DRIVE

CROWBAR

IN

CMPI

S

Q

R

V

T2

V

T1

g

m

V

REF

R

CMPT

OFF-TIME

CONTROL

11

C

T

V

IN

SENSE–

12

CMP

ADP3155

DAC

13

V

LDO2

14

FB2

8

V

LDO1

FB1

VID0

1

VID1

2

VID2

3

VID3

4

VID4

Figure 3. Functional Block Diagram

–4–

REV. A

Typical Performance Characteristics–

ADP3155

100

V

= 3.5V

95

90

85

80

EFFICIENCY – %

75

70

65

1.4 2.8 144.2 5.6 7 9.8 11.2 12.68.4

OUT

V

= 1.3V

OUT

OUTPUT CURRENT – Amps

V

OUT

V

= 2.8V

OUT

= 2.0V

SEE FIGURE 2

Figure 4. Efficiency vs. Output
Current

I

OUT

PRIMARY

N-DRIVE

1

2

DRIVER OUTPUT

SECONDARY

N-DRIVE

DRIVER OUTPUT

SEE FIGURE 2

= 10A

450
400
350

300
250
200
150

FREQUENCY – kHz

100

50

0

50 100 800

200 300 400 500 600 700
TIMING CAPACITOR – pF

Figure 5. Frequency vs. Timing
Capacitor

SEE FIGURE 2

VCC = +12V
V

= +5V

IN

I

= 10A

OUT

45

40
35
30
25
20
15

SUPPLY CURRENT – mA

10

5
0

45 397

Q

GATE(TOTAL)

58 83 134

OPERATING FREQUENCY – kHz

= 100nC

Figure 6. Supply Current vs.
Operating Frequency

OUTPUT VOLTAGE
20mV/DIV

OUTPUT CURRENT
19A TO 1A

DRIVE 1 AND 2 = 5V/DIV

500ns/DIV

Figure 7. Gate Switching Waveforms

OUTPUT VOLTAGE
20mV/DIV

OUTPUT CURRENT
1A TO 19A

10ms/DIV

Figure 10. Transient Response,
1 A–19 A of Figure 2 Circuit

100ns/DIV

Figure 8. Driver Transition
Waveforms

VCC VOLTAGE

5V/DIV

3

REGULATOR

OUTPUT VOLTAGE

1V/DIV

4

10ms/DIV

Figure 11. Power-On Start-Up
Waveform

10ms/DIV

Figure 9. Transient Response,
19 A–1 A of Figure 2 Circuit

25

TA = +258C
SEE FIGURE 13

20

15

10

NUMBER OF PARTS

5

0

–0.4

–0.5

–0.3

–0.45

–0.55

–0.35

OUTPUT ACCURACY – %

–0.2

–0.25

–0.1

–0.15

0

–0.05

0.05

0.1

0.2

0.3

0.4

0.15

0.25

0.35

Figure 12. Output Accuracy
Distribution, V

OUT

= 2.0 V

0.45

0.5

REV. A

–5–