Analog Devices ADP3154 Datasheet

a

CMPI

V

T1

V

REF

+5% V

REF

–5%

DELAY

V

REF

+15%

PWRGD

SENSE+

CROWBAR

OFF

IN

NONOVERLAP

DRIVE

Q

S

R

DRIVE1 DRIVE2 PGND

2R

SENSE–

V

REF

V

CC

SD

VLDO

V

T2

CMPT

C

T

g

m

R

REFERENCE

DAC

OFF-TIME
CONTROL

V

IN

SENSE–

1.20V

CMP

FB

VID0

VID2

VID3

VID4

ADP3154

AGND

VID1

V

CC

+12V

1mF

22mF

V

IN

+5V

+

C

IN

L

+

C

O

V

O

1.3V TO

3.5V

R

SENSE

1nF

C

COMP

35kV

20kV

V

O2

1000mF

R1

200pF

V

CC

SD

DRIVE1

SENSE+
SENSE–

DRIVE2

PGNDAGND

C

T

CMP

ADP3154

FB

VLDO

R2

VID0–VID4

5-BIT CODE

5-Bit Programmable Dual Power Supply

®

Controller for Pentium

III Processors

ADP3154

GENERAL DESCRIPTION

The ADP3154 is a highly efficient synchronous buck switching
regulator controller optimized for converting the 5 V main sup­ply into the core supply voltage required by the Pentium III and
other high performance processors. The ADP3154 uses an
internal 5-bit DAC to read a voltage identification (VID) code
directly from the processor, which is used to set the output
voltage between 1.3 V and 3.5 V. The ADP3154 uses a current
mode, constant off-time architecture to drive two external N­channel MOSFETs at a programmable switching frequency that

supplemental regulation technique called active voltage position-

can be optimized for size and efficiency. It also uses a unique

ing to enhance load transient performance.

Active voltage positioning results in a dc/dc converter that meets
the stringent output voltage specifications for Pentium II and
Pentium III processors, with the minimum number of output
capacitors and smallest footprint. Unlike voltage-mode and
standard current-mode architectures, active voltage positioning
adjusts the output voltage as a function of the load current so
that it is always optimally positioned for a system transient.

The ADP3154 provides accurate and reliable short circuit pro­tection and adjustable current limiting. It also includes an
integrated overvoltage crowbar function to protect the micro­processor from destruction in case the core supply exceeds the
nominal programmed voltage by more than 15%.

Pentium is a registered trademark of Intel Corporation.
All other trademarks are the property of their respective holders.

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

FEATURES
Active Voltage Positioning with Gain and Offset

Adjustment

Optimal Compensation for Superior Load Transient

Response
VRM 8.2, VRM 8.3 and VRM 8.4 Compliant
5-Bit Digitally Programmable 1.3 V to 3.5 V Output
Dual N-Channel Synchronous Driver
Onboard Linear Regulator Controller
Total Output Accuracy ⴞ1% Over Temperature
High Efficiency, Current-Mode Operation
Short Circuit Protection
Overvoltage Protection Crowbar Protects

Microprocessors with No Additional External

Components
Power Good Output
TSSOP-20 Package

APPLICATIONS
Desktop PC Power Supplies for:

Pentium II and Pentium III Processor Families
AMD-K6 Processors
VRM Modules

FUNCTIONAL BLOCK DIAGRAM

The ADP3154 contains a linear regulator controller that is
designed to drive an external N-channel MOSFET. This linear
regulator is used to generate the auxiliary voltages (AGP, GTL,
etc.) required in most motherboard designs, and has been de­signed to provide a high bandwidth load-transient response. A
pair of external feedback resistors sets the linear regulator out­put voltage.

Figure 1. Typical Application

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1999

ADP3154–SPECIFICATIONS

(0ⴗC ≤ TA ≤ +70ⴗC, V

=12 V, VIN = 5 V, unless otherwise noted)

CC

1

Parameter Symbol Conditions Min Typ Max Units

OUTPUT ACCURACY

1.3 V Output Voltage V

O

(Figure 13) 1.283 1.3 1.317 V

2.0 V Output Voltage 1.980 2.0 2.020 V

3.5 V Output Voltage 3.465 3.5 3.535 V

OUTPUT VOLTAGE LINE ∆V

O

I

= 10 A (Figure 2)

LOAD

REGULATION VIN = 4.75 V to 5.25 V 0.05 %

INPUT DC SUPPLY CURRENT

Normal Mode I
Shutdown T

2

Q

VSD = 0.6 V 4.1 5.5 mA

= +25°C, VID Pins Floating 140 250 µA

A

CURRENT SENSE THRESHOLD

VOLTAGE V

SENSE(TH)VSENSE–

VID0–VID4 PINS THRESHOLD VID

(TH)

Forced to V

– 3% 125 145 165 mV

OUT

Low 0.6 V
High 2.0 V

VID0–VID4 PINS INPUT CURRENT I

VID0–VID4 PULL-UP RESISTANCE R

C

PIN DISCHARGE CURRENT I

T

OFF-TIME t

DRIVER OUTPUT TRANSITION t

VID

VID

12

OFF

, t

R

F

TIME T

POSITIVE POWER GOOD TRIP POINT3V

NEGATIVE POWER GOOD TRIP POINT3V

POWER GOOD RESPONSE TIME t

CROWBAR TRIP POINT V

PWRGD

PWRGD

PWRGD

CROWBAR

VID = 0 V 110 220 µA

20 30 kΩ

T

= +25°C

A

in Regulation 65 µA

V

OUT

V

= 0 V 2 10 µA

OUT

C

= 150 pF 1.8 2.45 3.2 µs

T

CL = 7000 pF (Drive 1, 2)

= +25°C 120 200 ns

A

% Above Output Voltage 5 8 %

% Below Output Voltage –8 –5 %

500 µs

% Above Output Voltage 9 15 24 %

ERROR AMPLIFIER

OUTPUT IMPEDANCE RO

ERR

275 kΩ

ERROR AMPLIFIER

TRANSCONDUCTANCE g

m(ERR)

2.2 mmho

ERROR AMPLIFIER MINIMUM

OUTPUT VOLTAGE V

CMPMINVSENSE+

Forced to V

+ 3% 0.8 V

OUT

ERROR AMPLIFIER MAXIMUM

OUTPUT VOLTAGE V

CMPMAXVSENSE+

ERROR AMPLIFIER BANDWIDTH –3 dB BW

ERR

CMP = Open 500 kHz

Forced to V

– 3% 2.4 V

OUT

LINEAR REGULATOR FEEDBACK

CURRENT I

FB

0.35 1 µA

LINEAR REGULATOR Figure 2,

OUTPUT VOLTAGE V

O2

R

= 35 kΩ, R3 = 20 kΩ, I

PROG

= 0.5 A 3.24 3.30 3.38 V

O2

SHUTDOWN (SD) PIN

Low Threshold SD
High Threshold SD
Input Current SD

NOTES

1

All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.

2

Dynamic supply current is higher due to the gate charge being delivered to the external MOSFETs.

3

The trip point is for the output voltage coming into regulation.

Specifications subject to change without notice.

L

H

IC

Part Active 0.6 V
Part in Shutdown 2.0 V

10 µA

REV. A–2–

ADP3154

WARNING!

ESD SENSITIVE DEVICE

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Function

1–4, 20 VID1–VID4, Voltage Identification DAC Inputs. These pins are pulled up to an internal reference, providing a

VID0 logic one if left open. The DAC output programs the SENSE–regulation voltage from 1.3 V to 3.5 V.

Leaving all five DAC inputs open results in placing the ADP3154 into shutdown.
5 AGND Analog Ground. All internal signals of the ADP3154 are referenced to this ground.
6 SD Shutdown. A logic high will place the ADP3154 in shutdown and disable both outputs. This pin is

internally pulled down.
7 FB This pin is the feedback connection for the linear controller. Connect to the resistor divider network to

set its output voltage.
8, 18 NC No Connect.
9 VLDO Gate Drive for the Linear Regulator N-channel MOSFET.
10 SENSE– Connects to the internal resistor divider that senses the output voltage. This pin is also the reference

input for the current comparator.
11 SENSE+ The (+) input for the current comparator. The output current is sensed as a voltage at this pin with

respect to SENSE–.
12 C

T

13 CMP Error Amplifier output and compensation point. The voltage at this output programs the output cur-

14 PWRGD Power Good. An open drain signal indicates that the output voltage is within a ±5% regulation band.

15 V

CC

16 DRIVE2 Gate Drive for the (bottom) synchronous rectifier N-channel MOSFET. The voltage at DRIVE2

17 DRIVE1 Gate Drive for the buck switch N-channel MOSFET. The voltage at DRIVE1 swings from ground to

19 PGND Power Ground. The drivers turn off the buck and synchronous MOSFETs by discharging their gate

External capacitor CT connection to ground sets the off time of the device.

rent control level between the SENSE pins.

Supply Voltage to ADP3154.

swings from ground to V

V

.

CC

CC

.

capacitances to this pin. PGND should have a low impedance path to the source of the synchronous

MOSFET.

ABSOLUTE MAXIMUM RATINGS*

PIN CONFIGURATION

Input Supply Voltage (VCC) . . . . . . . . . . . . . . –0.3 V to +16 V

Shutdown Input Voltage . . . . . . . . . . . . . . . . –0.3 V to +16 V

Operating Ambient Temperature Range . . . . . 0°C to +70°C

Junction Temperature Range . . . . . . . . . . . . . 0°C to +150°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110°C/W

θ

JA

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . +300°C

*This is a stress rating only; operation beyond these limits can cause the device to

be permanently damaged.

ORDERING GUIDE

Temperature Package Package

VID1
VID2
VID3
VID4

AGND

SD
FB
NC

VLDO

SENSE–

1

2

3

4

5

ADP3154

TOP VIEW

6

(Not to Scale)

7

8

9

10

NC = NO CONNECT

Model Range Description Option

ADP3154JRU 0°C to +70°C Thin Shrink Small RU-20

Outline (TSSOP)

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADP3154 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

20

19

18

17

16

15

14

13

12

11

VID0
PGND
NC
DRIVE1
DRIVE2
V

CC

PWRGD
CMP
C

T

SENSE+

REV. A

–3–

ADP3154

V

O2

+3.3V

0.5A

1000mF
RTN

mP

SYSTEM

100kV

IRLR2703

1.1V

22V

ESR = 25mV EACH

2200mF 33

(25V)

22mF

1mF

IRL3803

L1

1.7mH

IRL3803

10BQ015

R1
105kV

R2

18.2kV

C

T

C

COMP

3600pF

220V

220V

R

PROG

35kV
R3

20kV

2N2222

2kV

470pF

ADP3154

1

VID1

2

VID2

3

VID3

4

VID4

5

AGND

6

SD

7

FB

8

NC

9

VLDO

10

SENSE–

SENSE+

NC = NO CONNECT

VID0

PGND

NC
DRIVE1
DRIVE2

V

PWRGD

CMP

20

19

18

17

16

15

CC

14

13

C

12

T

11

200pF

1nF

Figure 2. Typical VRM8.2/8.3/8.4 Compliant Core DC/DC Converter Circuit

SD

V

DRIVE1 DRIVE2 PGND

CC

NONOVERLAP

IN

DRIVE

CROWBAR

OFF

6

AGND PWRGD

5

V

+15%

REF

V

REF

+5% V

CMPI

S

Q

R

V

T2

CMPT

OFF-TIME

CONTROL

12

C

T

V

IN

SENSE–

1415

V

13

CMP

REF

T1

DELAY

–5%

SENSE+

11

g

m

V

REF

SENSE–

10

2R

R

ADP3154

REFERENCE

1.20V

DAC

R

5mV

SENSE

L2

1mH

1mF

ESR = 25mV EACH

2200mF 3 6

(25V)

9

VLDO

FB

VID0

1

VID1

2

VID2

3

VID3

4

VID4

VIN +12V

VCC +5V
+5V RTN

+12V RTN

V

O

2V
0-19A

RTN

Figure 3. Functional Block Diagram

–4–

REV. A