ANALOG DEVICES ADP3118 Service Manual

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Dual Bootstrapped 12 V MOSFET

FEATURES

Optimized for low gate charge MOSFETs
All-in-one synchronous buck driver
Bootstrapped high-side drive
One PWM signal generates both drives
Anticross-conduction protection circuitry
Output disable control turns off both MOSFETs

to float output per Intel® VRM 10 specification

APPLICATIONS

Multiphase desktop CPU supplies
Single-supply synchronous buck converters

SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM

Driver with Output Disable

ADP3118

GENERAL DESCRIPTION

The ADP3118 is a dual high voltage MOSFET driver optimized
for driving two N-channel MOSFETs, which are the two switches
in a nonisolated synchronous buck power converter. Each of the
drivers is capable of driving a 3000 pF load with a 25 ns
propagation delay and a 25 ns transition time. One of the drivers
can be bootstrapped and is designed to handle the high voltage
slew rate associated with floating high-side gate drivers. The
ADP3118 includes overlapping drive protection to prevent
shoot-through current in the external MOSFETs.

OD

The
MOSFETs to prevent rapid output capacitor discharge during
system shutdown.

The ADP3118 is specified over the commercial temperature
range of 0°C to 85°C and is available in 8-lead SOIC package.

pin shuts off both the high-side and the low-side

VIN12V

ADP3118

2

IN

DELAY

CMP

1V

3

OD

Flex-Mode™ is Protected by U.S. Patent 6683441

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

DELAY

CONTROL

LOGIC

CMP

Figure 1.

BST1

D1

R

BST

C

BST2

R

G

Q1

TO

INDUCTOR

Q2

05452-001

VCC

4

BST

1

C

DRVH

8

SW

7

VCC

6

DRVL

5

PGND

6

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] ©2005 Analog Devices, Inc. All rights reserved.

www.analog.com

ADP3118

TABLE OF CONTENTS

Specifications..................................................................................... 3

Application Information................................................................ 10

Absolute Maximum Ratings............................................................ 4

ESD Caution.................................................................................. 4

Pin Configuration and Function Descriptions............................. 5

Timing Characteristics..................................................................... 6

Typical Performance Characteristics ............................................. 7

Theory of Operation ........................................................................ 9

Low-Side Driver............................................................................ 9

High-Side Driver .......................................................................... 9

Overlap Protection Circuit.......................................................... 9

REVISION HISTORY

4/05—Revision 0: Initial Version

Supply Capacitor Selection ....................................................... 10

Bootstrap Circuit........................................................................ 10

MOSFET Selection..................................................................... 10

High-Side (Control) MOSFETs................................................ 10

Low-Side (Synchronous) MOSFETs ........................................ 11

PC Board Layout Considerations............................................. 11

Outline Dimensions ....................................................................... 13

Ordering Guide .......................................................................... 13

Rev. 0 | Page 2 of 16

ADP3118

SPECIFICATIONS

VCC = 12 V, BST = 4 V to 26 V, TA = 0°C to 85°C, unless otherwise noted.

Table

1.

Parameter Symbol Conditions Min Typ Max Unit

PWM INPUT

Input Voltage High 2.0 V
Input Voltage Low 0.8 V
Input Current −1 +1 µA
Hysteresis 90 250 mV

OD INPUT

Input Voltage High 2.0 V
Input Voltage Low 0.8 V
Input Current −1 +1 µA
Hysteresis 90 250 mV
Propagation Delay Times
t

HIGH-SIDE DRIVER

Output Resistance, Sourcing Current BST − SW = 12 V 2.2 3.5 Ω
Output Resistance, Sinking Current BST − SW = 12 V 1.0 2.5 Ω
Output Resistance, Unbiased BST − SW = 0 V 10 kΩ
Transition Times
t
Propagation Delay Times2 t
t
SW Pull-Down Resistance SW to PGND 10 kΩ

LOW-SIDE DRIVER

Output Resistance, Sourcing Current 2.0 3.2 Ω
Output Resistance, Sinking Current 1.0 2.5 Ω
Output Resistance, Unbiased VCC = PGND 10 kΩ
Transition Times
t
Propagation Delay Times2 t
t
Timeout Delay SW = 5 V 110 190 ns
SW = PGND 95 150 ns

SUPPLY

Supply Voltage Range V
Supply Current I
UVLO Voltage VCC rising 1.5 3.0 V
Hysteresis 350 mV

1

All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods.

2

For propagation delays, t

1

2

refers to the specified signal going high, and t

pdh

t

pdlOD

pdhOD

t

rDRVH

fDRVH

pdhDRVH

pdlDRVH

t

rDRVL

fDRVL

pdhDRVL

pdlDRVL

CC

SYS

See Figure 3 20 35 ns
See Figure 3 40 55 ns

BST − SW = 12 V, C
BST − SW = 12 V, C
BST − SW = 12 V, C
BST − SW = 12 V, C

C

= 3 nF, see Figure 4 20 35 ns

LOAD

C

= 3 nF, see Figure 4 16 30 ns

LOAD

C

= 3 nF, see Figure 4 12 35 ns

LOAD

C

= 3 nF, see Figure 4 30 45 ns

LOAD

= 3 nF, see Figure 4 25 40 ns

LOAD

= 3 nF, see Figure 4 20 30 ns

LOAD

= 3 nF, see Figure 4 25 40 ns

LOAD

= 3 nF, see Figure 4 25 35 ns

LOAD

4.15 13.2 V
BST = 12 V, IN = 0 V 2 5 mA

refers to it going low.

pdl

Rev. 0 | Page 3 of 16

ADP3118

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

VCC −0.3 V to +15 V
BST −0.3 V to VCC +15 V
BST to SW −0.3 V to +15 V
SW

DC −5 V to +15 V
<200 ns −10 V to +25 V

DRVH

DC SW − 0.3 V to BST + 0.3 V
<200 ns SW − 2 V to BST + 0.3 V

DRVL

DC −0.3 V to VCC + 0.3 V
<200 ns −2 V to VCC + 0.3 V

OD

IN,
θJA, SOIC

2-Layer Board
4-Layer Board

Operating Ambient Temperature

Range
Junction Temperature Range 0°C to 150°C
Storage Temperature Range −65°C to +150°C
Lead Temperature Range

Soldering (10 sec)

Vapor Phase (60 sec)

Infrared (15 sec)

−0.3 V to 6.5 V

123°C/W
90°C/W
0°C to 85°C

300°C
215°C
260°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Unless otherwise specified, all voltages are referenced to PGND.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degrada­tion or loss of functionality.

Rev. 0 | Page 4 of 16

ADP3118

V

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

BST

OD
CC

IN

1

ADP3118

2
3

TOP VIEW

(Not to Scale)

4

8
7
6
5

DRVH
SW
PGND
DRVL

05452-002

Figure 2. 8-Lead SOIC Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

1 BST

Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins holds this
bootstrapped voltage for the high-side MOSFET as it is switched.

2 IN

Logic Level PWM Input. This pin has primary control of the driver outputs. In normal operation, pulling this pin
low turns on the low-side driver; pulling it high turns on the high-side driver.

3

OD

Output Disable. When low, this pin disables normal operation, forcing DRVH and DRVL low.
4 VCC Input Supply. This pin should be bypassed to PGND with ~1 µF ceramic capacitor.
5 DRVL Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET.
6 PGND Power Ground. Should be closely connected to the source of the lower MOSFET.
7 SW

This pin is connected to the buck-switching node, close to the upper MOSFET’s source. It is the floating return

for the upper MOSFET drive signal. It is also used to monitor the switched voltage to prevent turn-on of the

lower MOSFET until the voltage is below ~1 V.
8 DRVH Buck Drive. Output drive for the upper (buck) MOSFET.

Rev. 0 | Page 5 of 16