Input voltage: 2.3 V to 5.5 V
Peak efficiency: 95%
3 MHz fixed frequency operation
Low quiescent current: 23 μA
Ultralow shutdown current: 0.2 μA (typical)
VSEL pin for simple dynamic voltage scaling (DVS)
100% duty cycle low dropout mode
Internal synchronous rectifier, compensation, and soft start
Current overload and thermal shutdown protection
Small, 6-ball, 1 mm × 1.5 mm WLCSP package
APPLICATIONS
PDAs and palmtop computers
Wireless handsets
Digital audio portable media players
Digital cameras, GPS navigation units
Low power portable medical equipment
Simple DVS, Buck Regulator
ADP2147
GENERAL DESCRIPTION
The ADP2147 is a high efficiency, low quiescent current, stepdown (buck) dc-to-dc regulator with an output voltage that can
be switched between two different settings under the control of
a select pin. The total solution requires only three tiny external
components.
The buck regulator automatically switches operating modes,
depending on the load current level, to maximize efficiency. At
high output loads, the buck regulator operates in PWM mode.
When the load current falls below a predefined threshold, the
regulator operates in power save mode (PSM), improving the
light-load efficiency.
The ADP2147 runs on input voltages of 2.3 V to 5.5 V, which
allows for single lithium or lithium polymer cells, multiple
alkaline or NiMH cells, PCMCIA, USB, and other standard
power sources. The maximum load current of 800 mA is
achievable across the input voltage range.
The ADP2147 is available with fixed output voltages from 0.8 V
to 3.3 V. All versions include an internal power switch and
synchronous rectifier for minimal external part count and high
efficiency. The ADP2147 has an internal soft start and is
internally compensated. During logic controlled shutdown, the
input is disconnected from the output, and the ADP2147 draws
less than 0.2 A (typical) from the power source.
Other key features include undervoltage lockout to prevent deep
battery discharge and soft start to prevent input current overshoot at startup. The ADP2147 is available in a 6-ball WLCSP.
TYPICAL APPLICATIONS CIRCUIT
2.3V TO 5.5V
4.7µF4.7µF
OFF
V
OUT
_L
OUT
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
VIN = 3.6 V, V
unless otherwise noted. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
INPUT CHARACTERISTICS
Input Voltage Range 2.3 5.5 V
Undervoltage Lockout Threshold VIN rising 2.3 V
V
OUTPUT CHARACTERISTICS
Output Voltage Accuracy PWM mode, VSEL = Low −2 +2 %
PWM mode, VSEL = High −2.5 +2.5 %
Line Regulation VIN = 2.3 V to 5.5 V, PWM mode 0.25 %/V
Load Regulation I
PWM TO POWER SAVE MODE CURRENT THRESHOLD 100 mA
INPUT CURRENT CHARACTERISTICS
DC Operating Current I
Shutdown Current EN = 0 V, TA = TJ = −40°C to +85°C 0.2 1.0 A
SW CHARACTERISTICS
SW On Resistance pFET 155 240 mΩ
nFET 115 200 mΩ
Current Limit pFET switch peak current limit 1100 1500 1650 mA
ENABLE/VSEL CHARACTERISTICS
Input High Threshold 1.2 V
Input Low Threshold 0.4 V
Input Leakage Current EN = VSEL = 0 V to 3.6 V −1 0 +1 A
OSCILLATOR FREQUENCY 2.6 3.0 3.4 MHz
START-UP TIME 250 s
THERMAL CHARACTERISTICS
Thermal Shutdown Threshold 150 °C
Thermal Shutdown Hysteresis 20 °C
= 0.8 V to 3.3 V, TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications,
OUT
falling 2.00 2.15 2.25 V
IN
= 0 mA to 800 mA −0.95 %/A
LOAD
= 0 mA, device not switching 23 30 A
LOAD
INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS
TA = −40°C to +125°C, unless otherwise specified. All limits at temperature extremes are guaranteed via correlation using standard
statistical quality control (SQC).
Table 2.
Parameter Symbol Min Typ Max Unit
MINIMUM INPUT AND OUTPUT CAPACITANCE C
CAPACITOR ESR R
Rev. 0 | Page 3 of 16
4.7 µF
MIN
0.001 1 Ω
ESR
ADP2147
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
VIN, EN, VSEL −0.4 V to +6.5 V
VOUT, SW to GND −1.0 V to (VIN + 0.2 V)
Temperature Range
Operating Ambient −40°C to +85°C
Operating Junction −40°C to +125°C
Storage Temperature −65°C to +150°C
Human Body ±1500 V
Charged Device ±500 V
Machine ±100 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. These are stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
Junction-to-ambient thermal resistance (θ
based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent on
the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θ
PCB material, layout, and environmental conditions. The specified
values of θ
to JEDEC JESD 51-9 for detailed information pertaining to board
construction. For additional information, see the AN-617
Application Note, MicroCSP™ Wafer Level Chip Scale Package.
Ψ
is the junction-to-board thermal characterization parameter
JB
measured in units of °C/W. The package Ψ
and calculation using a 4-layer board. The JESD51-12, Guidelines for Reporting and Using Package Thermal Information, states that
thermal characterization parameters are not the same as thermal
resistances. Ψ
multiple thermal paths rather than through a single path, which
is the procedure for measuring thermal resistance, θ
fore, Ψ
package as well as radiation from the package, factors that make
Ψ
more useful in real-world applications than θJB. Maximum
JB
junction temperature (T
(T
) and power dissipation (PD) using the formula:
B
T
J
Refer to JEDEC JESD51-8 and JESD51-12 for more detailed
information about Ψ
combination.
The ADP2147 can be damaged if the junction temperature limit is
exceeded. Monitoring ambient temperature does not guarantee
that the junction temperature (T
) is within the specified
J
temperature limit. In applications with high power dissipation
and poor thermal resistance, the maximum ambient temperature
may need to be derated. In applications with moderate power
dissipation and low printed circuit board (PCB) thermal
resistance, the maximum ambient temperature can exceed the
maximum limit if the junction temperature is within specification
limits. The junction temperature (T
on the ambient temperature (T
device (P
package (θ
), and the junction-to-ambient thermal resistance of the
D
). Maximum junction temperature (TJ) is calculated
JA
from the ambient temperature (T
) of the device is dependent
J
), the power dissipation of the
A
) and power dissipation (PD)
A
THERMAL RESISTANCE
θJA and ΨJB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type θJA Ψ
6-Ball WLCSP 170 80 °C/W
ESD CAUTION
using the following formula:
T
= TA + (PD × θJA)
J
are based on a 4-layer, 4 in. × 3 in. circuit board. Refer
JA
measures the component power flowing through
JB
thermal paths include convection from the top of the
JB
) is calculated from the board temperature
J
= TB + (PD × ΨJB)
.
JB
) of the package is
JA
may vary, depending on
JA
is based on modeling
JB
. There-
JB
Unit
JB
Rev. 0 | Page 4 of 16
ADP2147
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
BALL A1
INDICA TOR
1
2
VINEN
A
SW
VSEL
B
GND VOUT
C
ADP2147
TOP VIEW
(BALL SIDE DOWN)
Not to Scale
Figure 2. Pin Configuration (Top View)
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
A1 VIN
Power Source Input. VIN is the source of the pFET high-side switch. Bypass VIN to GND with a 4.7 µF or greater
capacitor as close to the ADP2147 as possible.
B1 SW
Switch Node Output. SW is the drain of the P-channel MOSFET switch and N-channel synchronous rectifier.
Connect the output LC filter between SW and the output voltage.
C1 GND Ground. Connect the input and output capacitors to GND.
A2 EN Buck Activation. To turn on the buck, set EN to high. To turn off the buck, set EN to low.
B2 VSEL
Voltage Select Input for Simple Dynamic Voltage Scaling (DVS). Drive VSEL low to switch the VOUT pin to the
default voltage setting. Drive VSEL high to switch VOUT to the alternate voltage setting.
C2 VOUT Output Voltage Sensing Input.
09885-002
Rev. 0 | Page 5 of 16
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