Low RDSON of 105 mΩ at 1.8 V
Internal output discharge resistor (ADP191)
Turn-on slew rate limiting (ADP191)
Low input voltage range: 1.1 V to 3.6 V
500 mA continuous operating current
Built-in level shift for control logic that can be operated
by 1.2 V logic
Low 2 μA (maximum) ground current
Ultralow shutdown current: <1 μA
Ultrasmall 0.8 mm × 0.8 mm, 4-ball, 0.4 mm pitch WLCSP
APPLICATIONS
Mobile phones
Digital cameras and audio devices
Portable and battery-powered equipment
High-Side Power Switches
ADP190/ADP191
TYPICAL APPLICATIONS CIRCUIT
ADP190
VINVOUT
+
GND
–
ON
EN
OFF
ADP191
VINVOUT
+
GND
–
ON
EN
OFF
LEVEL SHIFT
AND SLEW
RATE CONTROL
Figure 1.
LEVEL SHIFT
AND SLEW
RATE CONTROL
AND LOAD
DISCHARGE
Figure 2.
LOAD
LOAD
07874-001
07874-102
GENERAL DESCRIPTION
The ADP190/ADP191 are high-side load switches designed for
operation from 1.1 V to 3.6 V. These load switchs provide power
domain isolation for extended power battery life. The devices
contain a low on-resistance P-channel MOSFET that supports
more than 500 mA of continuous current and minimizes power
loss. The low 2 A (maximum) of ground current and ultralow
shutdown current make the ADP190/ADP191 ideal for batteryoperated portable equipment. The built-in level shifter for enable
logic makes the ADP190/ADP191 compatible with modern
processors and GPIO controllers.
The ADP191 controls the turn-on slew rate of the switch to
reduce the input inrush current. The ADP191 also incorporates
an internal output discharge resistor to discharge the output
capacitance when the ADP191 output is disabled.
Beyond operating performance, the ADP190/ADP191 occupy
minimal printed circuit board (PCB) space with an area less than
0.64 mm
2
and a height of 0.60 mm. It is available in an ultrasmall
0.8 mm × 0.8 mm, 4-ball, 0.4 mm pitch WLCSP.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
1.3 V < VIN < 1.8 V, TJ = −40°C to +85°C 0.4 1.2 V
1.8 V ≤ VIN ≤ 3.6 V, TJ = −40°C to +85°C 0.45 1.2 V
Logic High Voltage VIH 1.1 V ≤ VIN ≤ 3.6 V 1.1 V
Logic Low Voltage VIL 1.1 V ≤ VIN ≤ 3.6 V 0.3 V
EN Input Pull-Down Resistance REN 4 MΩ
CURRENT
Ground Current1 I
Shutdown Current I
EN = GND, TJ = −40°C to +85°C 2 µA
VIN to VOUT RESISTANCE RDSON
V
V
V
V
V
VOUT TIME
Turn-On Delay Time t
Turn-On Delay Time t
1
Ground current includes EN pull-down current.
= 200 mA, TA = 25°C, unless otherwise noted.
LOAD
= −40°C to +85°C 1.1 3.6 V
J
1.1 V ≤ VIN ≤ 1.3 V, TJ = −40°C to +85°C 0.3 1.0 V
EN_TH
V
GND
EN = GND 0.1 µA
OFF
ON_DLY
ON_DLY
= 3.6 V, VOUT open, TJ = −40°C to +85°C 2 µA
IN
= 3.6 V, I
IN
= 2.5 V, I
IN
= 1.8 V, I
IN
= 1.5 V, I
IN
= 1.2 V, I
IN
I
= 200 mA, EN = 1.5 V, C
LOAD
VIN = 3.6 V, I
= 200 mA, EN = 1.5 V 80 mΩ
LOAD
= 200 mA, EN = 1.5 V 90 mΩ
LOAD
= 200 mA, EN = 1.5 V 105 130 mΩ
LOAD
= 200 mA, EN = 1.5 V 125 mΩ
LOAD
= 200 mA, EN = 1 V 160 mΩ
LOAD
= 200 mA, EN = 1.5 V, C
LOAD
= 1 F 5 s
LOAD
= 1 F 1.5 s
LOAD
Table 2. ADP191
Parameter Symbol Test Conditions Min Typ Max Unit
INPUT VOLTAGE RANGE VIN T
= −40°C to +85°C 1.1 3.6 V
J
EN INPUT
EN Input Threshold V
1.1 V ≤ VIN ≤ 1.3 V, TJ = −40°C to +85°C 0.3 1.0 V
EN_TH
1.3 V < VIN < 1.8 V, TJ = −40°C to +85°C 0.4 1.2 V
1.8 V ≤ VIN ≤ 3.6 V, TJ = −40°C to +85°C 0.45 1.2 V
Logic High Voltage VIH 1.1 V ≤ VIN ≤ 3.6 V 1.1 V
Logic Low Voltage VIL 1.1 V ≤ VIN ≤ 3.6 V 0.3 V
EN Input Pull-Down Resistance REN 4 MΩ
CURRENT
Ground Current1 I
Shutdown Current I
V
GND
EN = GND 0.1 µA
OFF
= 3.6 V, VOUT open, TJ = −40°C to +85°C 2 µA
IN
EN = GND, TJ = −40°C to +85°C 2 µA
VIN to VOUT RESISTANCE RDSON
V
V
V
V
V
VOUT DISCHARGE RESISTANCE R
215 Ω
DIS
= 3.6 V, I
IN
= 2.5 V, I
IN
= 1.8 V, I
IN
= 1.5 V, I
IN
= 1.2 V, I
IN
= 200 mA, EN = 1.5 V 80 mΩ
LOAD
= 200 mA, EN = 1.5 V 90 mΩ
LOAD
= 200 mA, EN = 1.5 V 105 130 mΩ
LOAD
= 200 mA, EN = 1.5 V 125 mΩ
LOAD
= 200 mA, EN = 1 V 160 mΩ
LOAD
VOUT TIME
Turn-On Delay Time t
Turn-On Delay Time t
1
Ground current includes EN pull-down current.
I
ON_DLY
VIN = 3.6 V, I
ON_DLY
= 200 mA, EN = 1.5 V, C
LOAD
= 200 mA, EN = 1.5 V, C
LOAD
= 1 F 80 s
LOAD
= 1 F 50 s
LOAD
Rev. D | Page 3 of 16
ADP190/ADP191
V
TIMING DIAGRAM
TURN-ON
DELAY
90%
10%
EN
TURN-OFF
DELAY
V
OUT
TURN-ON
RISE
TURN-OFF
Figure 3. Timing Diagram
FALL
07874-003
Rev. D | Page 4 of 16
ADP190/ADP191
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
VIN to GND Pins −0.3 V to +4.0 V
VOUT to GND Pins −0.3 V to VIN
EN to GND Pins −0.3 V to +4.0 V
Continuous Drain Current
TA = 25°C ±1 A
TA = 85°C ±500 mA
Continuous Diode Current −50 mA
Storage Temperature Range −65°C to +150°C
Operating Junction Temperature Range −40°C to +125°C
Soldering Conditions JEDEC J-STD-020
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination. The ADP190/ADP191can be damaged when the
junction temperature limits are exceeded. Monitoring ambient
temperature does not guarantee that T
temperature limits. In applications with high power dissipation
and poor PCB thermal resistance, the maximum ambient
is within the specified
J
Junction-to-ambient thermal resistance (θ
based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent on
the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θ
PCB material, layout, and environmental conditions. The specified values of θ
See JESD51-7 and JESD51-9 for detailed information regarding
board construction. For additional information, see the AN-617
application note, MicroCSP
Ψ
is the junction-to-board thermal characterization parameter
JB
with units of °C/W. Ψ
calculation using a 4-layer board. The JESD51-12 document,
Guidelines for Reporting and Using Electronic Package Thermal
Information, states that thermal characterization parameters are
not the same as thermal resistances. Ψ
power flowing through multiple thermal paths rather than through
a single path, as in thermal resistance (θ
paths include convection from the top of the package as well as
radiation from the package, factors that make Ψ
in real-world applications. Maximum junction temperature (T
is calculated from the board temperature (T
dissipation (P
T
= TB + (PD × ΨJB)
J
See JESD51-8, JESD51-9, and JESD51-12 for more detailed
information about Ψ
temperature may need to be derated.
In applications with moderate power dissipation and low PCB
thermal resistance, the maximum ambient temperature can
exceed the maximum limit as long as the junction temperature
is within specification limits. The junction temperature (T
the device is dependent on the ambient temperature (T
power dissipation of the device (P
thermal resistance of the package (θ
Maximum junction temperature (T
ambient temperature (T
) and power dissipation (PD) using the
A
), and the junction-to-ambient
D
).
JA
) is calculated from the
J
), the
A
) of
J
THERMAL RESISTANCE
and ΨJB are specified for the worst-case conditions, that is, a
θ
JA
device soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type θJA ΨJB Unit
4-Ball, 0.4 mm Pitch WLCSP 260 58.4 °C/W
ESD CAUTION
formula
= TA + (PD × θJA)
T
J
are based on a 4-layer, 4 inch × 3 inch PCB.
JA
TM
Waf er L e vel Ch i p Scal e Pa ckage.
of the package is based on modeling and
JB
) using the formula
D
.
JB
) of the package is
JA
may vary, depending on
JA
measures the component
JB
). Therefore, ΨJB thermal
JB
more useful
JB
) and the power
B
)
J
Rev. D | Page 5 of 16
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