Datasheet ADP1882 Datasheet (ANALOG DEVICES)

Synchronous Current-Mode with

V

Constant On-Time, PWM Buck Controller

FEATURES

Power input voltage as low as 2.75 V to 20 V Bias supply voltage range: 2.75 V to 5.5 V Minimum output voltage: 0.8 V

0.8 V reference voltage with ±1.0% accuracy Supports all N-channel MOSFET power stages Available in 300 kHz, 600 kHz, and 1.0 MHz options No current-sense resistor required Power saving mode (PSM) for light loads (ADP1883 only) Resistor-programmable current-sense gain Thermal overload protection Short-circuit protection Precision enable input Integrated bootstrap diode for high-side drive 140 μA shutdown supply current Starts into a precharged load Small, 10-lead MSOP package

APPLICATIONS

Telecom and networking systems Mid to high end servers Set-top boxes DSP core power supplies

R

TOP

OUT

VDD= 2.75V TO 5.5V

100

95 90 85 80 75 70 65 60 55

EFFICIENCY (%)

50 45 40 35 30 25

100 1k 10k 100k

Figure 2. ADP1882/ADP1883 Efficiency vs. Load Current

ADP1882/ADP1883

TYPICAL APPLICATIONS CIRCUIT

= 2.75V TO 2 0

IN

C

C2

R

C

R

BOT

C

VDD2

C

VDD

VIN

ADP1882/

ADP1883

COMP/EN BST

FB DRVH

GND SW

VDD DRVL

PGND

C

BST

R

RES

Figure 1.

VDD = 5.5V, VIN = 13.0V V

= 5.5V, VIN = 16.5V

DD

VDD = 5.5V, VIN = 5.5V (PSM) V

= 5.5V, VIN = 5.5V

DD

V

= 3.6V, VIN = 5.5V

DD

TA = 25°C V

= 1.8V

OUT

f

= 300kHz

SW

WURTH INDUCTO R: 744325120, L = 1. 2µH, DCR = 1.8m

INFINEON MOSFETs: BSC042N03MS G (UPPER/LOWER)

LOAD CURRENT (mA)

= 1.8 V, 300 kHz)

(V

OUT

C

IN

Q1

L

C

OUT

Q2

V

LOAD

OUT

08901-001

08901-002

GENERAL DESCRIPTION

The ADP1882/ADP1883 are versatile current-mode, synchronous step-down controllers that provide superior transient response, optimal stability, and current-limit protection by using a constant on-time, pseudo-fixed frequency with a programmable currentlimit, current-control scheme. In addition, these devices offer optimum performance at low duty cycles by using valley currentmode control architecture. This allows the ADP1882/ADP1883 to drive all N-channel power stages to regulate output voltages as low as 0.8 V.

The ADP1883 is the power saving mode (PSM) version of the device and is capable of pulse skipping to maintain output regulation while achieving improved system efficiency at light loads (see the Power Saving Mode (PSM) Version (ADP1883) section for more information).

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

Available in three frequency options (300 kHz, 600 kHz, and

1.0 MHz, plus the PSM option), the ADP1882/ADP1883 are well suited for a wide range of applications. These ICs not only operate from a 2.75 V to 5.5 V bias supply, but they also can accept a power input as high as 20 V.

In addition, an internally fixed soft start period is included to limit input in-rush current from the input supply during startup and to provide reverse current protection during soft start for a precharged output. The low-side current-sense, current-gain scheme and integration of a boost diode, along with the PSM/forced pulse-width modulation (PWM) option, reduce the external part count and improve efficiency.

The ADP1882/ADP1883 operate over the −40°C to +125°C junction temperature range and are available in a 10-lead MSOP.

ADP1882/ADP1883

REVISION HISTORY

4/10—Revision 0: Initial Version

Rev. 0 | Page 2 of 40

ADP1882/ADP1883

SPECIFICATIONS

All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). VDD = 5 V, BST − SW = 5 V, V

= 13 V. The specifications are valid for TJ = −40°C to +125°C, unless otherwise specified.

IN

Table 1.

Parameter Symbol Conditions Min Typ Max Unit

POWER SUPPLY CHARACTERISTICS

High Input Voltage Range VIN ADP1882ARMZ-0.3/ADP1883ARMZ-0.3 (300 kHz) 2.75 12 20 V ADP1882ARMZ-0.6/ADP1883ARMZ-0.6 (600 kHz) 2.75 12 20 V ADP1882ARMZ-1.0/ADP1883ARMZ-1.0 (1.0 MHz) 3.0 12 20 V Low Input Voltage Range VDD C ADP1882ARMZ-0.3/ADP1883ARMZ-0.3 (300 kHz) 2.75 5 5.5 V ADP1882ARMZ-0.6/ADP1883ARMZ-0.6 (600 kHz) 2.75 5 5.5 V ADP1882ARMZ-1.0/ADP1883ARMZ-1.0 (1.0 MHz) 3.0 5 5.5 V Quiescent Current I Shutdown Current I

Q_DD

DD, SD

+ I

Q_BST

BST, SD

Undervoltage Lockout UVLO Rising VDD (see Figure 35 for temperature variation) 2.65 V UVLO Hysteresis Falling VDD from operational state 190 mV

SOFT START

Soft Start Period See Figure 58 3.0 ms

ERROR AMPLIFIER

FB Regulation Voltage VFB T T T Transconductance GM 300 520 730 μs FB Input Leakage Current I

FB = 0.8 V, COMP/EN = released 1 50 nA

FB, LEAK

CURRENT-SENSE AMPLIFIER GAIN

Programming Resistor (RES)

RES = 47 kΩ ± 1% 2.98 3.4 3.7 V/V

Value from DRVL to PGND RES = 22 kΩ ± 1% 6 6.6 7.4 V/V RES = none 24.1 26.7 29.3 V/V RES = 100 kΩ ± 1% 12.1 13.4 14.7 V/V

SWITCHING FREQUENCY

ADP1882ARMZ-0.3/

300 kHz

ADP1883ARMZ-0.3 (300 kHz)

On Time VIN = 5 V, V

Minimum On Time VIN = 20 V 145 190 ns

Minimum Off Time 84% duty cycle (maximum) 340 400 ns ADP1882ARMZ-0.6/

600 kHz

ADP1883ARMZ-0.6 (600 kHz)

On Time VIN = 5 V, V Minimum On Time VIN = 20 V, V Minimum Off Time 65% duty cycle (maximum) 340 400 ns

ADP1882ARMZ-1.0/

1.0 MHz

ADP1883ARMZ-1.0 (1.0 MHz)

On Time VIN = 5 V, V Minimum On Time VIN = 20 V 60 85 ns Minimum Off Time 45% duty cycle (maximum) 340 400 ns

= 1 μF to PGND, CIN = 0.22 μF to GND

IN

FB = 1.5 V, no switching 1.1 mA

COMP/EN < 285 mV 140 215 μA

= 25°C 800 mV

J

= −40°C to +85°C 795.3 800 805.5 mV

J

= −40°C to +125°C 792.8 800 808.0 mV

J

Typical values measured at 50% time points with 0 nF at DRVH and DRVL; maximum values are guaranteed by bench evaluation

= 2 V, TJ = 25°C 1115 1200 1285 ns

OUT

= 2 V, TJ = 25°C 490 540 585 ns

OUT

= 0.8 V 82 110 ns

OUT

= 2 V, TJ = 25°C 280 312 340 ns

OUT

1

Rev. 0 | Page 3 of 40

ADP1882/ADP1883

Parameter Symbol Conditions Min Typ Max Unit

OUTPUT DRIVER CHARACTERISTICS

High-Side Driver

Output Source Resistance I Output Sink Resistance I Rise Time Fall Time

2

t

2

t

BST − SW = 4.4 V, CIN = 4.3 nF (see Figure 60) 25 ns

R, DRVH

BST − SW = 4.4 V, CIN = 4.3 nF (see Figure 61) 11 ns

F, D RV H

Low-Side Driver

Output Source Resistance I Output Sink Resistance I

2

Rise Time Fall Time

2

t

V

R, DRVL

V

F, D RV L

Propagation Delays

DRVL Fall to DRVH Rise DRVH Fall to DRVL Rise

SW Leakage Current I

2

t t

BST − SW = 4.4 V (see Figure 60) 22 ns

TPDH, DRVH

BST − SW = 4.4 V (see Figure 61) 24 ns

TPDH, DRVL

BST = 25 V, SW = 20 V, VDD = 5.5 V 110 μA

SW, LEAK

Integrated Rectifier

Channel Impedance I

PRECISION ENABLE THRESHOLD

Logic High Level VIN = 2.75 V to 20 V, VDD = 2.75 V to 5.5 V 235 285 330 mV Enable Hysteresis VIN = 2.75 V to 20 V, VDD = 2.75 V to 5.5 V 35 mV

COMP VOLTAGE

COMP Clamp Low Voltage V

COMP Clamp High Voltage V COMP Zero Current Threshold V

THERMAL SHUTDOWN T

COMP(LOW )

2.75 V ≤ VDD ≤ 5.5 V 2.55 V

COMP(H IGH)

2.75 V ≤ VDD ≤ 5.5 V 0.95 V

COMP_ZC T

TMSD

Thermal Shutdown Threshold Rising temperature 155 °C Thermal Shutdown Hysteresis 15 °C Hiccup Current Limit Timing 6 ms

1

The maximum specified values are with the closed loop measured at 10% to 90% time points (see and , C

MOSFETs specified as Infineon BSC042N030MSG.

2

Not automatic test equipment (ATE) tested.

= 1.5 A, 100 ns, positive pulse (0 V to 5 V) 2 3.5 Ω

SOURCE

= 1.5 A, 100 ns, negative pulse (5 V to 0 V) 0.8 2 Ω

SINK

= 1.5 A, 100 ns, positive pulse (0 V to 5 V) 1.7 3 Ω

SOURCE

= 1.5 A, 100 ns, negative pulse (5 V to 0 V) 0.75 2 Ω

SINK

= 5.0 V, CIN = 4.3 nF (see Figure 61) 18 ns

DD

= 5.0 V, CIN = 4.3 nF (see Figure 60) 16 ns

DD

= 10 mA 22 Ω

SINK

From disable state, release COMP/EN pin to enable device; 2.75 V ≤ V

≤ 5.5 V

DD

Figure 60 Figure 61)

0.47 V

= 4.3 nF, and the upper-side and lower-si

GATE

de

Rev. 0 | Page 4 of 40

ADP1882/ADP1883

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

VDD to GND −0.3 V to +6 V VIN to PGND −0.3 V to +28 V FB, COMP/EN to GND −0.3 V to (VDD + 0.3 V) DRVL to PGND −0.3 V to (VDD + 0.3 V) SW to PGND −2.0 V to +28 V BST to SW −0.8 V to (VDD + 0.3 V) BST to PGND −0.3 V to 28 V DRVH to SW −0.3 V to VDD PGND to GND

θJA (10-Lead MSOP)

2-Layer Board 213.1°C/W

4-Layer Board 171.7°C/W Operating Junction Temperature Range −40°C to +125°C Storage Temperature Range −65°C to +150°C Soldering Conditions JEDEC J-STD-020 Maximum Soldering Lead Temperature

(10 sec)

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified, all other voltages are referenced to PGND.

±0.3 V

300°C

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.

Table 3. Thermal Resistance

Package Type θ

θJA (10-Lead MSOP)

2-Layer Board 213.1 °C/W 4-Layer Board 171.7 °C/W

1

θJA is specified for the worst-case conditions; that is, θJA is specified for device

soldered in a circuit board for surface-mount packages.

1

Unit

JA

BOUNDARY CONDITION

In determining the values given in Ta b le 2 and Tabl e 3, natural convection was used to transfer heat to a 4-layer evaluation board.

ESD CAUTION

Rev. 0 | Page 5 of 40

ADP1882/ADP1883

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VIN

1

ADP1882/

FB GND VDD

2

ADP1883

3

TOP VIEW

4

(Not to S cale)

5

COMP/EN

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 VIN High Input Voltage. Connect VIN to the drain of the upper-side MOSFET. 2 COMP/EN Output of the Internal Error Amplifier/IC Enable. When this pin functions as EN, applying 0 V to this pin disables the IC. 3 FB Noninverting Input of the Internal Error Amplifier. This is the node where the feedback resistor is connected. 4 GND

Analog Ground Reference Pin of the IC. All sensitive analog components should be connected to this ground plane (see the Layout Considerations section).

5 VDD

Bias Voltage Supply for the ADP1882/ADP1883 Controller, Including the Output Gate Drivers. A bypass capacitor of 1 μF directly from this pin to PGND and a 0.1 μF across VDD and GND are recommended.

6 DRVL

Drive Output for the External Lower-Side N-Channel MOSFET. This pin also serves as the current-sense gain

setting pin (see Figure 69). 7 PGND Power GND. Ground for the lower-side gate driver and lower-side N-channel MOSFET. 8 DRVH Drive Output for the External Upper-Side, N-Channel MOSFET. 9 SW Switch Node Connection. 10 BST

Bootstrap for the Upper-Side MOSFET Gate Drive Circuitry. An internal boot rectifier (diode) is connected

between VDD and BST. A capacitor from BST to SW is required. An external Schottky diode can also be

connected between VDD and BST for increased gate drive capability.

BST

10

9

SW

8

DRVH PGND

7

DRVL

6

08901-003

Rev. 0 | Page 6 of 40

ADP1882/ADP1883

TYPICAL PERFORMANCE CHARACTERISTICS

100

VDD = 5.5V, VIN = 5.5V (PSM)

95

V

= 5.5V, VIN = 13V (PSM )

DD

90

VDD = 5.5V, VIN = 5.5V

85 80 75 70 65 60 55

EFFICIENCY (%)

50 45 40 35 30

100 1k 10k 100k

V

DD

VDD = 3.6V, VIN = 5.5V (PSM)

WURTH IND: 744355147, L = 0.47 µH, DCR: 0.80M INFENION FETs: BSC042N03MS G ( UPPER/LOWER) TA = 25°C

= 5.5V,

V

DD

V

= 13V

IN

(PSM)

= 5.5V, VIN = 16.5V ( PSM)

DD

= 3.6V, VIN = 16.5V (PSM)

VDD = 3.6V, V

= 13V

IN

(PSM)

LOAD CURRENT (mA)

Figure 4. Efficiency—300 kHz, V

OUT

= 0.8 V

08901-004

100

95

VDD = 5.5V, V

= 13V (PSM)

90

IN

85 80 75 70 65 60 55 50

EFFICIE NCY ( %)

45 40 35

VDD = 3.6V, VIN = 5.5V

30 25 20 15

100 100k10k1k

Figure 7. Efficiency—600 kHz, V

VDD = 5.5V, VIN = 5.5V (PSM)

VDD = 5.5V, VIN = 13V

VDD = 5.5V, VIN = 16.5V

WURTH INDUCTOR: 744355072, L = 0.72µH, DCR: 1.65m INFINEON FETS: BSC042N03MS G (UPPER/LOWER) R

: 5.4m

ON

T

= 25°C

A

VDD = 5.5V, VIN = 5.5V

= 5.5V, VIN = 16.5V ( PSM)

V

DD

LOAD CURRENT (mA)

= 0.8 V

OUT

08901-007

100

95

VDD = 5.5V, VIN = 5.5V

VDD = 5.5V, VIN = 5.5V (PSM)

90 85 80 75

VDD = 5.5V, V

= 13V

IN

VDD = 5.5V, VIN = 16.5V

VDD = 5.5V, VIN = 13V (PSM)

VDD = 5.5V, VIN = 16.5V (PSM)

70 65

VDD = 3.6V, VIN = 5.5V

60 55

EFFICIENCY (%)

50 45 40 35 30 25

100 1k 10k 100k

WURTH INDUCTOR: 7443252100, L = 1.0µH, DCR: 3.3m INFINEON M OSFETS: BSC042N03MS G (UPPER/ LOWER) R

: 5.4m

ON

T

= 25°C

A

LOAD CURRENT (mA)

Figure 5. Efficiency—300 kHz, V

100

VDD = 5.5V, VIN = 16.5V (PSM)

95

OUT

= 1.8 V

90 85

VDD = 2.7V, VIN = 16.5V (PSM)

80 75 70 65 60 55

EFFICIENCY (%)

50 45 40 35 30

100 1k 10k 100k

VDD = 2.7V, VIN = 13V

VDD = 5.5V, VIN = 13V

VDD = 3.6V, VIN = 13V

VDD = 5.5V, VIN = 16.5V VDD = 3.6V, VIN = 16.5V

TA = 25°C V

OUT

F

SW

WURTH INDUCTOR: 744355200, L = 2µH, DCR: 2.5m INFINEON M OSFETS: BSC042N03MS G (UPPER/LOWER)

= 1.8V

= 300kHz

LOAD CURRENT (mA)

Figure 6. Efficiency—300 kHz, V

OUT

= 7 V

100

VDD = 5.5V, VIN = 5.5V

95 90 85 80 75 70 65 60 55

EFFICIENCY (%)

50 45 40 35 30 25

100 1k 10k 100k

8901-005

VDD = 5.5V, VIN = 13V

WURTH INDUCTOR: 744325072, L = 0.72µH, DCR: 1.65m INFINEON FETS: BSC042N03MS G ( UPPER/LO W ER) R T

VDD = 5.5V, VIN = 16.5V (PSM)

VDD = 5.5V, VIN = 13V (PSM)

VDD = 5.5V, VIN = 16.5V

: 5.4m

ON

= 25°C

A

LOAD CURRENT (mA)

Figure 8. Efficiency—600 kHz, V

100

VDD = 5.5V/VIN = 13V (PSM)

VDD = 3.6V, VIN = 5.5V

VDD = 5.5V, VIN = 5.5V (PSM)

= 1.8 V

OUT

8901-008

95

90

VDD = 3.6V/VIN = 13V

85

80

VDD = 5.5V/VIN = 16.5V

75

= 5.5V/VIN = 13V

V

70

EFFICIENCY (%)

65

60

55

50

100 1k 10k 100k

8901-006

DD

TA = 25°C V

= 5V, VIN = 13V

OUT

F

= 600kHz

SW

WURTH INDUCT OR: 7443552100, L = 1.0µH, DCR: 3.3m INFINEON MOSFETS: BSC042N03MS G (UPPER/LOWER)

LOAD CURRENT (mA)

Figure 9. Efficiency—600 kHz, V

OUT

= 5 V

901-009 08

Rev. 0 | Page 7 of 40

ADP1882/ADP1883

T

100

VDD = 5.5V/VIN = 5.5V (PSM)

95 90

VDD = 3.6V/VIN = 3.6V

V

= 5.5V/VIN = 5.5V

DD

85 80 75 70 65 60 55 50

EFFICIENCY (%)

45 40 35 30 25 20

100 1k 10k 100k

VDD = 5.5V/VIN = 16.5V

VDD = 5.5V/VIN = 13V

TA = 25°C V

OUT

F

SW

WURTH INDUCTOR: 744303022, L = 0.22µH, DCR: 0.33m INFINEON M OSFETS: BSC042N03MS G ( UPPER/LOWER)

VDD = 3.6V/VIN = 13V

= 0.8V, VIN = 5.5V

= 1MHz

LOAD CURRENT (mA)

100

VDD = 5.5V/VIN = 5.5V (PSM)

95 90

Figure 10. Efficiency—1.0 MHz, V

VDD = 5.5V/VIN = 5.5V

= 0.8 V

OUT

VDD = 5.5V/VIN = 13V

85 80 75 70 65 60

VDD = 3.6V/VIN = 13V

VDD = 3.6V/VIN = 16.5V

VDD = 5.5V/VIN = 16.5V

55 50

EFFICIENCY (%)

45 40 35 30 25 20

100

1k 10k 100k

TA = 25°C V

= 1.8V, VIN = 5.5V

OUT

F

= 1MHz

SW

WURTH INDUCTOR: 744303022, L = 0.22µH, DCR: 0.33m INFINEON M OSFETS: BSC042N03MS G (UPPER/LOWER)

LOAD CURRENT (mA)

Figure 11. Efficiency—1.0 MHz, V

OUT

= 1.8 V

100

95

VDD = 5.5V/VIN = 16.5V (PSM)

90 85 80 75 70 65 60 55

EFFICIENCY (%)

50 45 40 35 30

100 1k 10k

VDD = 5.5V/VIN = 16.5V

VDD = 5.5V/VIN = 13V

= 25°C

T

A

V

= 4V, VIN = 16.5V

OUT

F

= 1MHz

SW

WURTH INDUCTOR: 744318180, L = 1.4µH, DCR: 3.2m INFINEON M OSFETS: BSC042N03MS G ( UPPER/LOWER)

LOAD CURRENT (mA)

Figure 12. Efficiency—1.0 MHz, V

OUT

= 4 V

08901-010

08901-011

08901-012

0.820

0.818

0.816

0.814

0.812

0.810

0.808

0.806

0.804

0.802

0.800

OUTPUT VOLTAGE (V)

0.798

0.796

0.794

0.792

0.790 0 2k 4k 6k 8k 10k 12k 14k 16k

V

= 5.5V VIN = 13V

IN

+125°C +25°C –40°C

VIN = 16.5V

LOAD CURRENT (mA)

Figure 13. Output Voltage Accuracy—300 kHz, V

OUT

1.809

1.804

AGE (V)

1.799

1.794

OUTPUT VOL

= 5.5V VIN = 13V

1.789

1.784

0 1.5k 3.0k 4.5k 6.0k 7.5k 9.0k 10.5k 12.0k 13.5k 15.0k

V

IN

+125°C +25°C –40°C

VIN = 16.5V

LOAD CURRENT (mA)

Figure 14. Output Voltage Accuracy—300 kHz, V

6.970

6.965

6.960

6.955

V

DD

V

IN

= 3.6V,

= 16.5V

+125°C +25°C –40°C

V V

DD

= 13V

IN

OUT

= 5.5V,

6.950

6.945

6.940

6.935

6.930

6.925

OUTPUT VOLTAGE (V)

6.920

V

= 5.5V,

DD

V

= 16.5V

6.915

6.910

6.905

IN

+125°C +25°C –40°C

0 1k2k3k4k5k6k7k8k9k10k

V V

DD IN

= 3.6V,

= 13V

+125°C +25°C –40°C

LOAD CURRENT (mA)

Figure 15. Output Voltage Accuracy—300 kHz, V

+125°C +25°C –40°C

= 0.8 V

+125°C +25°C –40°C

= 1.8 V

+125°C +25°C –40°C

= 7 V

OUT

08901-013

08901-014

08901-015

Rev. 0 | Page 8 of 40

ADP1882/ADP1883

0.829

0.827

0.825

0.823

0.821

0.819

0.817

0.815

0.813

0.811

0.809

0.807

0.805

OUTPUT VOLTAGE (V)

0.803

0.801

0.799

0.797

0.795

0 2k 4k0 6k 8k 10k 12k 14k

+125°C +25°C –40°C

= 16.5V VIN = 13VVIN = 16.5V

V

IN

+125°C +25°C –40°C

LOAD CURRENT (mA)

+125°C +25°C –40°C

Figure 16. Output Voltage Accuracy—600 kHz, V

= 0.8 V

OUT

115

08901-

0.820

0.818

0.816

0.814

0.812

0.810

0.808

0.806

0.804

0.802

0.800

OUTPUT VOLTAGE (V)

0.798

0.796

0.794

0.792

0.790 0 2k4k6k8k10k12k

Figure 19. Output Voltage Accuracy—1.0 MHz, V

V

= 5.5V VIN = 13V

IN

+125°C +25°C –40°C

LOAD CURRENT (mA)

+125°C +25°C –40°C

VIN = 16.5V

+125°C +25°C –40°C

= 0.8 V

OUT

08901-018

1.806

1.804

1.802

1.800

1.798

1.796

1.794

1.792

OUTPUT VOLTAGE (V)

1.790

1.788

1.786 0 1.5k 3.0k 4.5k 6.0k 7.5k 9.0k 10.5k 12.0k 13.5k 15.0k

V

= 5.5V VIN = 13V VIN = 16V

IN

+125°C +25°C –40°C

LOAD CURRENT (mA)

+125°C +25°C –40°C

Figure 17. Output Voltage Accuracy—600 kHz, V

5.015

5.010

5.005

5.000

4.995

4.990

4.985

OUTPUT VOLTAGE (V)

4.980

4.975

4.970 01k2k3k4k5k6k7k

= 5.5V, VIN = 13V VDD = 5.5V, VIN = 16.5V

V

DD

+125°C +25°C –40°C

LOAD CURRENT (mA)

Figure 18. Output Voltage Accuracy—600 kHz, V

+125°C +25°C –40°C

= 1.8 V

OUT

+125°C +25°C –40°C

8k 9k 10k

= 5 V

OUT

1.808

1.806

1.804

1.802

1.800

1.798

1.796

1.794

1.792

1.790

OUTPUT VOLTAGE (V)

1.788

1.786

1.784

1.782

1.780 0 1.5k 3.0k 4.5k 6.0k 7.5k 9.0k 10.5k 12.0k 13.5k 15.0k

8901-016

Figure 20. Output Voltage Accuracy—1.0 MHz, V

4.060

4.055

4.050

4.045

4.040

4.035

4.030

4.025

4.020

OUTPUT VOLTAGE (V)

4.015

4.010

4.005

4.000 0 8.0k1.6k2.4k3.2k4.0k4.8k5.6k6.4k7.2k8.0k

08901-017

Figure 21. Output Voltage Accuracy—1.0 MHz, V

V

= 5.5V VIN = 13V

IN

+125°C +25°C –40°C

LOAD CURRENT (mA)

V

LOAD CURRENT (mA)

IN

= 13V

+125°C +25°C –40°C

VIN = 16.5V

+125°C +25°C –40°C

= 1.8 V

OUT

VIN = 16.5V

+125°C +25°C –40°C

= 4 V

OUT

08901-019

08901-020

Rev. 0 | Page 9 of 4

0

ADP1882/ADP1883

T

0.804

0.803

0.802

0.801

AGE (V)

0.800

0.799

FEEDBACK VOL

0.798

0.797

0.796

VDD = 2.7V, VIN = 2.7/3.6V V

= 3.6V, VIN = 3.6V TO 16.5V

DD

V

= 5.5V, VIN = 5.5/13V/ 16. 5V

DD

–40.0 –7.5 25.0 57.5 90.0 122.5

TEMPERATURE (°C)

Figure 22. Feedback Voltage vs. Temperature

108901-02

1000

950

900

850

800

750

700

FREQUENCY (kHz )

650

V

= 3.6V

IN

600

550

10.8 11.0 11.2 11.4 11.6 11.8 12.0 12.2 12.4 12.6 12.8 13.0 13.2

+125°C +25°C –40°C

VIN = 5.5V

+125°C +25°C –40°C

VIN (V)

08901-024

Figure 25. Switching Frequency vs. High Input Voltage, 1.0 MHz, ±10% of 12 V

335 325 315 305 295 285 275 265

FREQUENCY (kHz )

255

V

= 3.6V

245 235 225

DD

+125°C +25°C –40°C

10.8 11.0 11.2 11.4 11.6 11.8 12.0 12.2 12.4 12.6 12.8 13.0 13.2

VDD = 5.5V

+125°C +25°C –40°C

VIN (V)

08901-022

Figure 23. Switching Frequency vs. High Input Voltage, 300 kHz, ±10% of 12 V

650

600

550

500

FREQUENCY ( kHz)

450

400

10.8 11.0 11.2 11.4 11.6 11.8 12.0 12.2 12.4 12.6 12.8 13.0 13.2

= 1.8V

V

OUT

+125°C +125°C +25°C –40°C

Figure 24. Switching Frequency vs. High Input Voltage, 600 kHz, V

VDD = 5.5V

+25°C –40°C

V

IN

(V)

OUT

08901-023

= 1.8 V,

±10% of 12 V

355 340 325 310 295 280 265 250

FREQUENCY ( kHz)

235

V

220 205 190

0 2k 4k 6k 8k 10k 12k 14k 16k

= 5.5V VIN = 13V

IN

+125°C +25°C –40°C

LOAD CURRENT (mA)

+125°C +25°C –40°C

VIN = 16.5V

Figure 26. Frequency vs. Load Current, 300 kHz, V

380

V

= 5.5V

IN

370 360 350 340 330 320 310 300

FREQUENCY (kHz)

290 280 270 260

0

+125°C +25°C –40°C

V

2k 4k 6k 8k

LOAD CURRENT (mA)

= 13V

IN

+125°C +25°C –40°C

10k 12k

V

IN

= 16.5V

+125°C +25°C –40°C

14k

16k 18k

Figure 27. Frequency vs. Load Current, 300 kHz, V

OUT

+125°C +25°C –40°C

= 0.8 V

= 1.8 V

8901-025

20k

08901-026

Rev. 0 | Page 10 of 40

ADP1882/ADP1883

C

358 354 350 346 342 338 334 330

Y (kHz)

326 322 318 314

FREQUEN

310 306 302 298 294 290

0 0.8k1.6k2.4k3.2k4.0k4.8k5.6k6.4k7.2k8.0k8.8k9.6k

Figure 28. Frequency vs. Load Current, 300 kHz, V

700 670 640 610 580 550 520 490

Y (kHz)

460 430 400 370

FREQUEN

340 310 280 250 220 190

0 2k4k6k8k10k12k14k

V

= 5.5V VIN = 13V

IN

+125°C +25°C –40°C

Figure 29. Frequency vs. Load Current, 600 kHz, V

V

= 13V

IN

+125°C +25°C –40°C

LOAD CURRENT (mA)

+125°C +25°C –40°C

LOAD CURRENT (mA)

VIN = 16.5V

+125°C +25°C –40°C

= 7 V

OUT

VIN = 16.5V

+125°C +25°C –40°C

= 0.8 V

OUT

708901-02

08901-028

750 742 734 726 718 710 702 694 686 678 670

FREQUENCY (kHz )

662 654 646 638 630

0 0.8k 1.6k 2.4k 3.2k 4.0k 4.8k 5.6k 6.4k 7.2k 8.0k 8.8k 9.6k

V

= 13V VIN = 16.5V

IN

+125°C +25°C –40°C

LOAD CURRENT (mA)

Figure 31. Frequency vs. Load Current, 600 kHz, V

1300 1225 1150 1075 1000

925 850 775 700

FREQUENCY ( kHz)

625 550 475 400

0 2k4k6k8k10k12k

Figure 32. Frequency vs. Load Current, V

V

= 5.5V VIN = 13V

IN

+125°C +25°C –40°C

LOAD CURRENT (mA)

+125°C +25°C –40°C

= 1.0 MHz, 0.8 V

OUT

VIN = 16.5V

+125°C +25°C –40°C

OUT

=5 V

+125°C +25°C –40°C

08901-030

08901-031

835 815 795 775 755 735 715 695 675 655 635 615

FREQUENCY (kHz )

595 575 555 535 515 495

V

= 5.5V

IN

+125°C +25°C –40°C

= 13V

V

IN

+125°C +25°C –40°C

VIN = 16.5V

+125°C +25°C –40°C

0 2k 4k 6k 8k 10k 12k 14k 16k 18k

LOAD CURRENT (mA)

Figure 30. Frequency vs. Load Current, 600 kHz, V

= 1.8 V

OUT

8901-029

1450 1375 1300 1225 1150

Y (kHz)

1075 1000

925

FREQUEN

850 775 700 625 550

0 2k 4k 6k 8k 10k 12k 14k 16k

V

= 5.5V VIN = 13V

IN

+125°C +25°C –40°C

LOAD CURRENT (mA)

+125°C +25°C –40°C

Figure 33. Frequency vs. Load Current, 1.0 MHz, V

VIN = 16.5V

+125°C +25°C –40°C

= 1.8 V

OUT

08901-032

Rev. 0 | Page 11 of 40

ADP1882/ADP1883

1350

1300

1250

1200

1150

1100

1050

FREQUENCY (kHz )

1000

950

900

0 0.8k 1.6k 2.4k 3.2k 4.0k 4.8k 5.6k 6.4k 7.2k 8.0k

V

= 13V

IN

+125°C +25°C –40°C

LOAD CURRENT (mA)

VIN = 16.5V

Figure 34. Frequency vs. Load Current, 1.0 MHz, V

+125°C +25°C –40°C

OUT

08901-033

= 4 V

84 82 80 78 76 74 72 70 68 66 64 62 60 58 56 54 52

MAXIMUM DUTY CY CLE (%)

50 48 46 44 42 40

3.6 4.8 6.0 7.2 8.4 9.6 10.8 12.0 13.2 14.4 15.6

= 3.6V +125°C

V

DD

VDD = 5.5V

+25°C –40°C

VIN (V)

Figure 37. Maximum Duty Cycle vs. High Voltage Input (V

08297-036

)

IN

2.658

2.657

2.656

2.655

2.654

2.653

UVLO (V)

2.652

2.651

2.650

2.649 –40 120100806040200–20

TEMPERATURE ( °C)

Figure 35. UVLO vs. Temperature

100

95 90 85 80 75 70 65 60 55

MAXIMUM DUTY CY CLE (%)

50 45 40

300 400 500 600 700 800 900 1000

FREQUENCY (kHz)

VDD=2.7V VDD=3.6V VDD=5.5V

Figure 36. Maximum Duty Cycle vs. Frequency

+125°C +25°C –40°C

680

630

580

530

480

430

380

330

MINUMUM OFF TIME (ns)

280

230

180

–40 120100806040200–20

08901-034

V

= 2.7V

REG

= 3.6V

V

REG

V

= 5.5V

REG

TEMPERATURE (°C)

08901-037

Figure 38. Minimum Off Time vs. Temperature

680

630

580

530

480

430

380

330

MINUMUM OFF TIME (ns)

280

230

180

2.7 5.55.14.74.33.93.53.1

08901-035

VREG (V)

+125°C +25°C –40°C

08901-038

Figure 39. Minimum Off Time vs. VDD (Low Input Voltage)

Rev. 0 | Page 12 of 40

ADP1882/ADP1883

800

720

640

560

480

400

320

RECTIFI ER DROP (mV)

240

160

80

300 400 500 600 700 800 900 1000

V

= 2.7V

REG

V

= 3.6V

REG

V

= 5.5V

REG

+125°C +25°C –40°C

FREQUENCY (kHz)

Figure 40. Internal Rectifier Drop vs. Frequency

08901-039

80

72

64

56

48

40

32

24

BODY DIODE CO NDUCTION TIME (ns)

16

8

2.73.13.53.94.34.75.15.5

300kHz +125°C 1MHz

VREG (V)

+25°C –40°C

08901-042

Figure 43. Lower-Side MOSFET Body Conduction Time vs. VDD (Low Input Voltage)

1280 1200 1120 1040

960 880 800 720 640 560 480

RECTIFI ER DROP (mV)

400 320 240 160

80

2.73.13.53.94.34.75.15.5

VIN = 5.5V VIN = 13V VIN = 16.5V

1MHz 300kHz

VREG (V)

TA = 25°C

Figure 41. Internal Boost Rectifier Drop vs. VDD (Low Input Voltage)

Variation

over V

IN

720

640

560

480

400

300kHz +125°C 1MHz

+25°C –40°C

OUTPUT VOLTAGE

1

2

3

4

CH1 50mV

08901-040

CH3 10V

B

CH2 5A 

W

B

CH4 5V

W

INDUCTOR CURRENT

SW NODE

LOW SIDE

M400ns A CH2 3.90A

T 35.8%

08901-043

Figure 44. Power Saving Mode (PSM) Operational Waveform, 100 mA

OUTPUT VOLTAGE

1

INDUCTOR CURRENT

2

320

RECTIFI ER DROP (mV)

240

160

80

2.73.13.53.94.34.75.15.5 VREG (V)

Figure 42. Internal Boost Rectifier Drop vs. VDD

08901-041

Rev. 0 | Page 13 of 40

3

4

CH1 50mV CH3 10V

B

CH2 5A 

W

B

CH4 5V

W

M4.0µs A CH2 3.90A

T 35.8%

Figure 45. PSM Waveform at Light Load, 500 mA

SW NODE

LOW SIDE

08901-044

ADP1882/ADP1883

OUTPUT VOLTAGE

4

INDUCTOR CURRENT

2

OUTPUT VO LTAGE

1

SW NODE

3

CH1 5A  M400ns A CH3 2.20V CH3 10V CH4 100m V

B

W

T 30.6%

Figure 46. CCM Operation at Heavy Load, 18 A

(See Figure 92 for Applications Circuit)

OUTPUT VOLTAGE

2

12A STEP

1

SW NODE

3

4

CH1 10A  CH2 200mV CH3 20V CH4 5V

B

M2ms A CH1 3.40A

W

T 75.6%

LOW SIDE

Figure 47. Load Transient Step—PSM Enabled, 20 A

(See Figure 92 for Applications Circuit)

1

3

SW NODE

LOW SIDE

12A NEGATIVE STEP

4

04508901-

CH1 10A  CH2 200mV CH3 20V CH4 5V

B

M20µs A CH1 3.40A

W

T 48.2%

08901-048

Figure 49. Negative Step During Heavy Load Transient Behavior—PSM Enabled,

20 A (See Figure 92 for Applications Circuit)

4

OUTPUT VO LTAGE

12A STEP

1

2

3

CH1 10A  CH2 5V

08901-046

CH3 20V CH4 200m V

LOW SIDE

SW NODE

M2ms A CH1 6.20A

B

T 15.6%

W

08901-049

Figure 50. Load Transient Step—Forced PWM at Light Load, 20 A

(See Figure 92 for Applications Circuit)

2

12A POSITIVE ST EP

OUTPUT VOLTAGE

1

3

SW NODE

LOW SIDE

4

CH1 10A  CH2 200mV CH3 20V CH4 5V

B

M20µs A CH1 3.40A

W

T 30.6%

08901-047

Figure 48. Positiv e Step During Heavy Load Trans ient Behavior—PSM Enabled,

20 A, V

= 1.8 V (See Figure 92 for Applications Circuit)

OUT

Rev. 0 | Page 14 of 40

OUTPUT VOLTAGE

4

12A POSITIVE STEP

1

2

3

SW NODE

CH1 10A  CH2 5V CH3 20V CH4 200mV

M20µs A CH1 6.20A

B

T 43.8%

W

LOW SIDE

08901-050

Figure 51. Positive Step During Heavy Load Transient Behavior—Forced PWM

at Light Load, 20 A, V

= 1.8 V (See Figure 92 for Applications Circuit)

OUT

ADP1882/ADP1883

2

OUTPUT VO LTAGE

12A NEGATIVE STEP

1

SW NODE

3

LOW

4

CH1 10A  CH2 200mV CH3 20V CH4 5V

SIDE

B

M10µs A CH1 5.60A

W

T 23.8%

5108901-0

Figure 52. Negative Step During Heavy Load Transient Behavior—Forced PWM

at Light Load, 20 A (See Figure 92 for Applications Circuit)

1

2

4

OUTPUT VOLTAGE

INDUCTOR CURRENT

LOW SIDE

OUTPUT VOLTAGE

1

INDUCTOR CURRENT

2

LOW SIDE

4

SW NODE

3

B

CH1 2V CH3 10V CH4 5V

CH2 5A 

W

M2ms A CH1 720mV

T 32.8%

Figure 55. Start-Up Behavior at Heavy Load, 18 A, 300 kHz

(See Figure 92 for Applications Circuit)

1

2

4

OUTPUT VOLTAGE

INDUCTOR CURRENT

LOW SIDE

08901-054

SW NODE

3

B

CH1 2V CH3 10V CH4 5V

CH2 5A 

W

M4ms A CH1 920mV

T 49.4%

Figure 53. Output Short-Circuit Behavior Leading to Hiccup Mode

1

OUTPUT VOLTAGE

INDUCTOR CURRENT

2

SW NODE

3

LOW SIDE

4

B

CH1 5V CH3 10V CH4 5V

CH2 10A 

W

M10µs A CH2 8.20A

T 36.2%

Figure 54. Magnified Waveform During Hiccup Mode

SW NODE

3

08901-052

B

CH1 2V CH3 10V CH4 5V

CH2 5A 

W

M4ms A CH1 720mV

T 41.6%

08901-055

Figure 56. Power-Down Waveform During Heavy Load

OUTPUT VOLTAGE

1

INDUCTOR CURRENT

2

SW NODE

3

LOW SIDE

4

CH1 50mV

08901-053

CH3 10V

B

W

B

W

CH2 5A  CH4 5V

M2µs A CH2 3.90A

T 35.8%

08901-056

Figure 57. Output Voltage Ripple Waveform During PSM Operation

at Light Load, 2 A

Rev. 0 | Page 15 of 40

ADP1882/ADP1883

18ns (

t

OUTPUT VO LTAGE

1

LOW SIDE

4

SW NODE

3

INDUCTOR CURRENT

2

CH1 1V CH3 10V

B

W B

W

CH2 5A  CH4 2V

M1ms A CH1 1.56V

T 63.2%

Figure 58. Soft Start and RES Detect Waveform

LOW SIDE

TA = 25°C

)

r

,DRVL

4

HIGH SIDE

HS MINUS SW

3

2

M

TA = 25°C

08901-057

CH3 5V MATH 2V 20ns

CH2 5V CH4 2V

24ns (

t

pdh

11ns (

t

f

,DRVH

M20ns A CH2 4.20V

T 39.2%

Figure 61. Upper-Side Driver Falling and Lower-Side Rising Edge Waveforms

= 4.3 nF (Upper-Side/Lower-Side MOSFET),

(C

IN

Q

= 27 nC (VGS = 4.4 V (Q1), VGS = 5 V (Q3))

TOTAL

570

550

,DRVL

)

LOW SIDE

)

SW NODE

V V V

REG REG REG

= 5.5V = 3.6V = 2.7V

08901-060

4

HIGH SIDE

SW NODE

3

2 M

HS MINUS SW

CH3 5V MATH 2V 40ns

CH2 5V CH4 2V

M40ns A CH2 4.20V

T 29.0%

08901-058

Figure 59. Output Drivers and SW Node Waveforms

HIGH SIDE

t

r

,DRVH

TA = 25°C

)

08901-059

LOW SIDE

4

22ns (

SW NODE

3

2

HS MINUS

M

SW

CH3 5V MATH 2V 40ns

t

pdh

DRVH

CH2 5V CH4 2V

16ns (

t

)

f

,DRVL

)

25ns (

M40ns A CH2 4.20V

T 29.0%

Figure 60. Upper-Side Driver Rising and Lower-Side Falling Edge Waveforms

= 4.3 nF (Upper-Side/Lower-Side MOSFET),

(C

IN

Q

= 27 nC (VGS = 4.4 V (Q1), VGS = 5 V (Q3))

TOTAL

530

510

490

470

TRANSCONDUCTANCE (µS)

450

430

–40 –20 120100806040200

Figure 62. Transconductance (G

680

630

580

530

480

430

TRANSCONDUCTANCE (µS)

380

330

2.7 3.0 5.44.8 5.14.54.23.93.63.3

Figure 63. Transconductance (G

TEMPERATURE ( °C)

) vs. Temperature

M

VREG (V)

) vs. VDD

M

+125°C +25°C –40°C

08901-061

08901-062

Rev. 0 | Page 16 of 40

ADP1882/ADP1883

1.30

1.25

1.20

1.15

1.10

1.05

1.00

0.95

0.90

0.85

QUIESCENT CURRENT (mA)

0.80

0.75

0.70

2.7 5.55.14.74.33.93.53.1

Figure 64. Quiescent Current vs. VDD (VIN = 13 V)

+125°C

+25°C

–40°C

VREG (V)

08901-063

Rev. 0 | Page 17 of 40

ADP1882/ADP1883

ADP1882/ADP1883 BLOCK DIAGRAM

ADP1882/ADP1883

V

DD

R (TRIMMED)

SW-FILTER

LEVEL SHIFT

t

HS

LS

= 2RC (V

ON

VREG

OUT/VIN

8k

VIN

)

BST

DRVH

300k

SW

DRVL

PGND

VDD

COMP/EN

FB

PRECISION

ENABLE BLOCK

I

SS

C

SS

SS_REF

BIAS BLOCK

AND REF

REF_ZERO

SS COMP

ERROR AMP

0.8V

TO ENABLE ALL BLOCKS

PFM

PWM

t

-TIMER

ON

STAT E

MACHINE

t

ON

BG_REF PSM IN_SS

PWM I

REV

VDD

DH_LO

DRVH

DRVL

DL_LO

C

SW INFORMATION

SW

I

REV

COMP

LOWER

COMP

CLAMP

REF_ZERO

GND

CS

AMP

CS GAIN SET

ADC

RES DETECT

AND

GAIN SET

0.4V

800k

64

08901-0

Figure 65. Block Diagram

Rev. 0 | Page 18 of 40

ADP1882/ADP1883

THEORY OF OPERATION

The ADP1882/ADP1883 are versatile current-mode, synchronous step-down controllers that provide superior transient response, optimal stability, and current limit protection by using a constant on-time, pseudo-fixed frequency with a programmable currentsense gain, current-control scheme. In addition, these devices offer optimum performance at low duty cycles by using valley currentmode control architecture. This allows the ADP1882/ADP1883 to drive all N-channel power stages to regulate output voltages as low as 0.8 V.

STARTUP

The ADP1882/ADP1883 have an input low voltage pin (VDD) for biasing and supplying power for the integrated MOSFET drivers. A bypass capacitor should be located directly across the VDD (Pin 5) and PGND (Pin 7) pins. Included in the power-up sequence is the biasing of the current-sense amplifier, the current-sense gain circuit (see the Programming Resistor (RES) Detect Circuit section), the soft start circuit, and the error amplifier.

The current-sense blocks provide valley current information (see the Programming Resistor (RES) Detect Circuit section) and are a variable of the compensation equation for loop stability (see the Compensation Network section). The valley current information is extracted by forcing 0.4 V across the DRVL output and the PGND pin, which generates a current depending on the resistor across DRVL and PGND in a process performed by the RES detect circuit. The current through the resistor is used to set the current-sense amplifier gain. This process takes approximately 800 µs, after which the drive signal pulses appear at the DRVL and DRVH pins synchronously and the output voltage begins to rise in a controlled manner through the soft start sequence.

The rise time of the output voltage is determined by the soft start and error amplifier blocks (see the Soft Start section). At the beginning of a soft start, the error amplifier charges the external compensation capacitor, causing the COMP/EN pin to rise above the enable threshold of 285 mV, thus enabling the ADP1882/ADP1883.

SOFT START

The ADP1882/ADP1883 have digital soft start circuitry, which involves a counter that initiates an incremental increase in current, by 1 µA, via a current source on every cycle through a fixed internal capacitor. The output tracks the ramping voltage by producing PWM output pulses to the upper-side MOSFET. The purpose is to limit the in-rush current from the high voltage input supply (VIN) to the output (V

OUT

).

PRECISION ENABLE CIRCUITRY

The ADP1882/ADP1883 employ precision enable circuitry. The enable threshold is 285 mV typical with 35 mV of hysteresis. The devices are enabled when the COMP/EN pin is released, allowing the error amplifier output to rise above the enable threshold (see Figure 66). Grounding this pin disables the

ADP1882/ADP1883, reducing the supply current of the devices to approximately 140 µA. For more information, see Figure 67.

ADP1882/ADP1883

FB

VDD

SS

ERROR

COMP/EN

C

C2

R

C

Figure 66. Release COMP/EN Pin to Enable the ADP1882/ADP1883

COMP/EN

>2.4V

2.4V

0.9V

500mV

285mV

0V

Figure 67. COMP/EN Voltage Range

AMPLIFIER

PRECISION ENABLE

250mV

HICCUP MODE INITIALIZED MAXIMUM CURRENT (UPPE R CL AMP )

ZERO CURRENT

USABLE RANGE ONLY AFTER SOFT START PERIOD IF CONTUNUOUS CONDUCTION MODE OF OPERATION IS SELECTED.

LOWER CLAM P

PRECISION ENABL E T HRES HOLD

35mV HYSTERESIS

0.8V

TO ENABLE ALL BLOCKS

08901-065

08901-066

UNDERVOLTAGE LOCKOUT

The undervoltage lockout (UVLO) feature prevents the part from operating both the upper-side and lower-side MOSFETs at extremely low or undefined input voltage (V

) ranges.

DD

Operation at an undefined bias voltage may result in the incorrect propagation of signals to the high-side power switches. This, in turn, results in invalid output behavior that can cause damage to the output devices, ultimately destroying the device tied at the output. The UVLO level has been set at

2.65 V (nominal).

THERMAL SHUTDOWN

The thermal shutdown is a self-protection feature to prevent the IC from damage due to a very high operating junction temperature. If the junction temperature of the device exceeds 155°C, the part enters the thermal shutdown state. In this state, the device shuts off both the upper-side and lower-side MOSFETs and disables the entire controller immediately, thus reducing the power consumption of the IC. The part resumes operation after the junction temperature of the part cools to less than 140°C.

Rev. 0 | Page 19 of 40

ADP1882/ADP1883

PROGRAMMING RESISTOR (RES) DETECT CIRCUIT

Upon startup, one of the first blocks to become active is the RES detect circuit. This block powers up before a soft start begins. It forces a 0.4 V reference value at the DRVL output (see Figure 68) and is programmed to identify four possible resistor values: 47 kΩ, 22 kΩ, open, and 100 kΩ.

ADP1882

DRVH

SW

DRVL

CS GAIN

PROGRAMMING

Figure 68. Programming Resistor Location

The RES detect circuit digitizes the value of the resistor at the DRVL pin (Pin 6). An internal ADC outputs a 2-bit digital code that is used to program four separate gain configurations in the current-sense amplifier (see Figure 69). Each configuration corresponds to a current-sense gain (A and 24 V/V, respectively (see Table 5 and Table 6 ). This variable is used for the valley current-limit setting, which sets up the appropriate current-sense signal gain for a given application and sets the compensation necessary to achieve loop stability (see the Valley Current-Limit Setting and Compensation Network sections).

CS

AMP

CS GAIN SET

DRVL

Figure 69. RES Detect Circuit for Current-Sense Gain Programming

ADC

RES

Table 5. Current-Sense Gain Programming

Resistor (kΩ) ACS (V/V)

47 3.25 22 6.5 Open 26 100 13

Q1

Q2

RES

08901-067

) of 3 V/V, 6 V/V, 12 V/V,

CS

SW

PGND

0.4V

08901-068

VALLEY CURRENT-LIMIT SETTING

The architecture of the ADP1882/ADP1883 is based on valley current-mode control. The current limit is determined by three components: the R fier output voltage swing (COMP), and the current-sense gain. The COMP range is internally fixed at 1.5 V. The current-sense gain is programmable via an external resistor at the DRVL pin (see the Programming Resistor (RES) Detect Circuit section). The R

of the lower-side MOSFET can vary over temperature

ON

and usually has a positive T temperature); therefore, it is recommended that the currentsense gain resistor be programmed based on the rated R the MOSFET at 125°C.

Because the ADP1882/ADP1883 are based on valley current control, the relationship between I

= I

I

CLIM

where:

is the desired valley current limit.

I

CLIM

I

is the current load.

LOAD

is the ratio between the inductor ripple current and the

K

I

desired average load current (see Figure 10).

Establishing K Inductor Selection section), but in most cases, K

Figure 70. Valley Current Limit to Average Current Relation

When the desired valley current limit (I the current-sense gain can be calculated by using the following expression:

=

I

CLIM

where:

ACS is the current-sense gain multiplier (see Tab le 5 and Tab l e 6 ). R

is the channel impedance of the lower-side MOSFET.

ON

of the lower-side MOSFET, the error ampli-

ON

(meaning that it increases with

C

and I

CLIM

K

⎞

⎛

×

LOAD

helps to determine the inductor value (see the

I

LOAD CURRENT

I

−21

⎟

⎜

⎠

⎝

RIPPLE CURRENT =

VALLEY CURRENT L I M I T

V5.1

RA ×

ONCS

CLIM

is as follows:

LOAD

= 0.33.

I

LOAD

3

) has been determined,

ON

of

8901-069

Rev. 0 | Page 20 of 40

ADP1882/ADP1883

A

Although the ADP1882/ADP1883 have only four discrete currentsense gain settings for a given R

variable, Tab le 6 and Figure 71

ON

outline several available options for the valley current setpoint based on various R

Table 6. Valley Current Limit Program

values.

ON

1

Valley Current Level

RON (mΩ)

47 kΩ 22 kΩ Open 100 kΩ

ACS = 3.4 V/V ACS = 6.6 V/V ACS = 26.7 V/V ACS = 13.4 V/V

1.5 38.5 2 28.8

2.5 23.1 3 38.46 19.2

3.5 32.97 16.5

4.5 25.64 12.8 5 23.08 11.5

5.5 20.98 10.5 10 23.08 11.54 5.77 15 30.769 15.38 7.692 3.85 18 25.641 12.82 6.41 3.21

1

Refer to Figure 71 for more information and a graphical representation.

39 37 35 33 31 29 27 25 23 21 19 17 15 13

VALLEY CURRENT L IMIT (A)

11

RES = OPEN

9

= 26.7V/V

A

CS

7 5 3

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

Figure 71. Valley Current-Limit Value vs. R

RES = 100k

= 13.4V/V

A

CS

RON (m)

of the Lower-Side MOSFET

ON

for Each Programming Resistor (RES)

RES = 47k

= 6.6V/V

A

CS

RES = 22k

= 3.4V/V

A

CS

08901-070

The valley current limit is programmed as outlined in Tabl e 6 and Figure 71. The inductor chosen must be rated to handle the peak current, which is equal to the valley current from Tabl e 6 plus the peak-to-peak inductor ripple current (see the Inductor Selection section). In addition, the peak current value must be used to compute the worst-case power dissipation in the MOSFETs (see Figure 72).

49

MAXIMUM DC LOAD

CURRENT

INDUCTOR

CURRENT

I = 33%

OF 30A

39.5A

35A

I = 45%

30A

VALLEY CURRENT - LIMIT THRESHOLD (SET FOR 25A)

OF 32.25A

32.25A

I = 65%

OF 37A

37A

COMP

OUTPUT

SWING

COMP

OUTPUT

2.4V

0.9V0A

Figu re 72. Valley Current-Limit Threshold in Relation to Inductor Ripple Current

HICCUP MODE DURING SHORT CIRCUIT

A current-limit violation occurs when the current across the source and drain of the lower-side MOSFET exceeds the current-limit setpoint. When 32 current-limit violations are detected, the controller enters the idle mode and turns off the MOSFETs for 6 ms, allowing the converter to cool down. Then, the controller reestablishes soft start and begins to cause the output to ramp up again (see Figure 73). While the output ramps up, COMP is monitored to determine if the violation is still present. If it is still present, the idle event occurs again, followed by the full-chip power-down sequence. This cycle continues until the violation no longer exists. If the violation disappears, the converter is allowed to switch normally, maintaining regulation.

08901-071

REPEATED CURRENT-L I M I T

VIOLAT ION DETECTED

HS

TERMINED NUMBER

CLIM

ZERO

CURRENT

A PREDE

OF PULS

ALLO

TO

ES IS COUNTED TO W THE CONVERTER COOL DOWN

SOFT START IS

REINITIALIZED TO

MONITO R IF THE

VIOLATION

STILL EXISTS

08901-072

Figure 73. Idle Mode Entry Sequence Due to Current-Limit Violations

Rev. 0 | Page 21

of 40

ADP1882/ADP1883

SYNCHRONOUS RECTIFIER

The ADP1882/ADP1883 employ an internal lower-side MOSFET driver to drive the external upper-side and lower-side MOSFETs. The synchronous rectifier not only improves overall conduction efficiency but also ensures proper charging to the bootstrap capacitor located at the upper-side driver input. This is beneficial during startup to provide a sufficient drive signal to the external upper-side MOSFET and attain a fast turn on response, which is essential for minimizing switching losses. The integrated upperside and lower-side MOSFET drivers operate in complementary fashion with built-in anticross conduction circuitry to prevent unwanted shoot-through current that may potentially damage the MOSFETs or reduce efficiency as a result of excessive power loss.

POWER SAVING MODE (PSM) VERSION (ADP1883)

The ADP1883 is the power saving mode version of the ADP1882. The ADP1883 operates in the discontinuous conduction mode (DCM) and pulse skips at light load to midload currents. It outputs pulses, as necessary, to maintain output regulation. Unlike the continuous conduction mode (CCM), DCM operation prevents negative current, thus allowing improved system efficiency at light loads. Current in the reverse direction through this pathway, however, results in power dissipation and, therefore, a decrease in efficiency.

HS

LS

I

LOAD

0A

To minimize the chance of negative inductor current buildup, an on-board, zero-cross comparator turns off all upper-side and lower-side switching activities when the inductor current approaches the zero current line, causing the system to enter idle mode, where the upper-side and lower-side MOSFETs are turned off. To ensure idle mode entry, a 10 mV offset, connected in series at the SW node, is implemented (see Figure 75).

t

ON

HS AND LS ARE OFF

t

OFF

OR IN IDLE MODE

AS THE INDUCTOR CURRENT APPROACHES ZERO CURRENT, THE STATE MACHINE TURNS OFF THE LOWER-SIDE MOSFET.

Figure 74. Discontinuous Mode of Operation (DCM)

ZERO-CROSS

COMPARATOR

10mV

SW

I

Q2

08901-073

As soon as the forward current through the lower-side MOSFET decreases to a level where

10 mV = I

the zero-cross comparator (or I

Q2

× R

ON(Q2)

comparator) emits a signal to

REV

turn off the lower-side MOSFET. From this point, the slope of the inductor current ramping down becomes steeper (see Figure 76) as the body diode of the lower-side MOSFET begins to conduct current and continues conducting current until the remaining energy stored in the inductor has been depleted.

ANOTHER TRIGGERE D WHEN V FALLS BELOW REGULATION

SW

LS

I

LOAD

0A

Figure 76. 10 mV Offset to Ensure Prevention of Negative Inductor Current

t

EDGE IS

ON

OUT

HS AND LS

IN IDLE MODE

ZERO-CROSS COMPARATOR DETECTS 10mV OFFSET AND TURNS OFF L S

10mV = R

× I

ON

LOAD

t

ON

08901-075

The system remains in idle mode until the output voltage drops from within regulation. A PWM pulse is then produced, turning on the upper-side MOSFET to maintain system regulation. The ADP1883 does not have an internal clock; therefore, it switches purely as a hysteretic controller as described in this section.

TIMER OPERATION

The ADP1882/ADP1883 employ a constant on-time architecture that provides a variety of benefits, including improved load and line transient responses when compared with a constant (fixed) frequency current-mode control loop of a comparable loop design. The constant on-time timer, or t voltage (V

) and the output voltage (V

IN

information to produce an adjustable one-shot PWM pulse that varies the on time of the upper-side MOSFET in response to dynamic changes in input voltage, output voltage, and load current conditions to maintain regulation. It then generates an on-time (t

) pulse that is inversely proportional to VIN.

ON

V

= K ×

t

ON

where

K is a constant that is trimmed using an RC timer product

V

OUT

IN

for the 300 kHz, 600 kHz, and 1.0 MHz frequency options.

timer, senses the high input

ON

) using SW waveform

OUT

LS

Q2

08901-074

Figure 75. Zero-Cross Comparator with 10 mV of Offset

Rev. 0 | Page 22 of 40

ADP1882/ADP1883

K

t

ON

INFORMATION

Figure 77. Constant On-Time Timer

VREG

C

I

SW

R (TRIMMED)

V

IN

08901-076

The constant on time (tON) is not strictly constant because it varies with V

and V

IN

. However, this variation occurs in such

OUT

a way as to keep the switching frequency virtually independent of V

and V

IN

The t

timer uses a feedforward technique, applied to the constant

ON

OUT

.

on-time control loop, making it pseudo-fixed frequency to a first order. Second-order effects, such as dc losses in the external power MOSFETs (see the Efficiency Consideration section), cause some variation in frequency vs. load current and line voltage. These effects are shown in Figure 23 to Figure 34. The variations in frequency are much reduced, compared with the variations generated when the feedforward technique is not used.

The feedforward technique establishes the following relationship:

f

= 1

SW

where f

is the controller switching frequency (300 kHz,

SW

600 kHz, and 1.0 MHz).

The t

timer senses VIN and V

ON

variation with V

and V

IN

OUT

to minimize frequency

OUT

as previously explained. This provides a pseudo fixed frequency that is explained in the Pseudo-Fixed Frequency section. To allow headroom for V and V

For typical applications where V not relevant; however, for lower V

sensing, adhere to the following two equations:

OUT

V

≥ VIN/8 + 1.5

DD

V

≥ V

OUT

/4

= 5 V, these equations are

DD

inputs, care may be

DD

IN

required.

To illustrate this feature more clearly, this section describes one such load transient event—a positive load step—in detail. During load transient events, the high-side driver output pulse width stays relatively consistent from cycle to cycle; however, the off time (DRVL on time) dynamically adjusts according to the instantaneous changes in the external conditions mentioned.

When a positive load step occurs, the error amplifier (out of phase of the output, V

) produces new voltage information

OUT

at its output (COMP). In addition, the current-sense amplifier senses new inductor current information during this positive load transient event. The error amplifier’s output voltage reaction is compared to the new inductor current information that sets the start of the next switching cycle. Because current information is produced from valley current sensing, it is sensed at the down ramp of the inductor current, whereas the voltage loop information is sensed through the counter action upswing of the error amplifier’s output (COMP).

The result is a convergence of these two signals (see Figure 78), which allows an instantaneous increase in switching frequency during the positive load transient event. In summary, a positive load step causes V

to transient down, which causes COMP to

OUT

transient up and, therefore, shortens the off time. This resultant increase in frequency during a positive load transient helps to quickly bring V

back up in value and within the regulation

OUT

window.

Similarly, a negative load step causes the off time to lengthen in response to V demagnetizing phase, helping to bring V

rising. This effectively increases the inductor

OUT

within regulation.

OUT

In this case, the switching frequency decreases, or experiences a foldback, to help facilitate output voltage recovery.

Because the ADP1882/ADP1883 can respond rapidly to sudden changes in load demand, the recovery period in which the output voltage settles back to its original steady state operating point is much quicker than it would be for a fixed-frequency equivalent Therefore, using a pseudo-fixed frequency results in significantly better load transient performance than using a fixed frequency.

.

PSEUDO-FIXED FREQUENCY

The ADP1882/ADP1883 employ a constant on-time control scheme. During steady state operation, the switching frequency stays relatively constant, or pseudo-fixed. This is due to the oneshot t

timer, which produces a high-side PWM pulse with

ON

a fixed duration, given that external conditions such as input voltage, output voltage, and load current are also at steady state. During load transients, the frequency momentarily changes for the duration of the transient event so that the output comes back within regulation more quickly than if the frequency were fixed

PWM OUTPUT

or if it were to remain unchanged. After the transient event is complete, the frequency returns to a pseudo-fixed value to a first-order.

Rev. 0 | Page 23 of 40

LOAD CURRENT

DEMAND

CS AMP OUTPUT

ERROR AMP

OUTPUT

f

SW

Figure 78. Load Transient Response Operation

VALLEY TRIP POINTS

>

f

SW

08901-077

ADP1882/ADP1883

I

Δ

APPLICATIONS INFORMATION

FEEDBACK RESISTOR DIVIDER

The required resistor divider network can be determined for a given V is fixed at 0.8 V. Selecting values for R

value because the internal band gap reference (V

OUT

and RB determines the

T

REF

minimum output load current of the converter. Therefore, for a given value of R

, the RT value can be determined using the

B

following expression:

R

= RB ×

T

V

OUT

V)8.0( −

V8.0

INDUCTOR SELECTION

The inductor value is inversely proportional to the inductor ripple current. The peak-to-peak ripple current is given by

LOAD

IKI ≈×=Δ

IL

LOAD

where K

is typically 0.33.

I

The equation for the inductor value is given by

IN

L ×

=

×Δ

L

SW

where:

is the high voltage input.

V

IN

is the desired output voltage.

V

OUT

is the controller switching frequency (300 kHz, 600 kHz, and

f

SW

1.0 MHz).

When selecting the inductor, choose an inductor saturation rating that is above the peak current level, and then calculate the inductor current ripple (see the Valley Current-Limit Setting section and Figure 79).

52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18

PEAK INDUCTOR CURRENT (A)

16 14 12 10

8

6 8 10 12 14 16 18 20 22 24 26 28 30

Figure 79. Peak Current vs. Valley Current Threshold for 33%, 40%, and 50%

VALLEY CURRENT LIMIT (A)

of Inductor Ripple Current

3

VVV − )(

OUTOUT

VfI

IN

I = 50%

I = 40%

I = 33%

08901-078

)

Table 7. Recommended Inductors

L

DCR

(μH)

(mΩ)

0.12 0.33 55 10.2 × 7 Wurth Electronics 744303012

0.22 0.33 30 10.2 × 7 Wurth Electronics 744303022

0.47 0.8 50 14.2 × 12.8 Wurth Electronics 744355147

0.72 1.65 35 10.5 × 10.2 Wurth Electronics 744325072

0.9 1.6 28 13 × 12.8 Wurth Electronics 744355090

1.2 1.8 25 10.5 × 10.2 Wurth Electronics 744325120

1.0 3.3 20 10.5 × 10.2 Wurth Electronics 7443552100

1.4 3.2 24 14 × 12.8 Wurth Electronics 744318180

2.0 2.6 22 13.2 × 12.8 Wurth Electronics 7443551200

0.8 27.5 Sumida CEP125U-0R8

I

SAT

(A)

Dimensions (mm)

Manufacturer

Model Number

OUTPUT RIPPLE VOLTAGE (ΔVRR)

The output ripple voltage is the ac component of the dc output voltage during steady state. For a ripple error of 1.0%, the output capacitor value needed to achieve this tolerance can be determined using the following equation. Note that an accuracy of

1.0% is possible only during steady state conditions, not during load transients.

= (0.01) × V

V

RR

OUT

OUTPUT CAPACITOR SELECTION

The primary objective of the output capacitor is to facilitate the reduction of the output voltage ripple; however, the output capacitor also assists in the output voltage recovery during load transient events. For a given load current step, the output voltage ripple generated during this step event is inversely proportional to the value chosen for the output capacitor. The speed at which the output voltage settles during this recovery period depends on where the crossover frequency (loop bandwidth) is set. This crossover frequency is determined by the output capacitor, the equivalent series resistance (ESR) of the capacitor, and the compensation network.

To calculate the small-signal voltage ripple (output ripple voltage) at the steady state operating point, use the following equation:

OUT

⎛ ⎜

IC

×Δ=

L

⎜

SW

⎝

1

[]

LRIPPLE

where ESR is the equivalent series resistance of the output capacitors.

To calculate the output load step, use the following equation:

C

where 

×=

2

OUT

V

is the amount that V

DROOP

a given positive load current step (I

LOAD

ESRIVf

×Δ−Δ×

LOADDROOPSW

is allowed to deviate for

OUT

).

LOAD

⎞ ⎟ ⎟

)(8

ESRIVF

×Δ−Δ××

⎠

))((

Rev. 0 | Page 24 of 40

ADP1882/ADP1883

Ceramic capacitors are known to have low ESR. However, the trade-off of using X5R technology is that up to 80% of its capacitance may be lost due to derating as the voltage applied across the capacitor is increased (see Figure 80). Although X7R series capacitors can also be used, the available selection is limited to only up to 22 µF.

20 10

0 –10 –20 –30 –40 –50 –60 –70

CAPACITANCE CHARGE ( %)

–80

10µF TDK 25V, X7R, 1210 C3225X7R1E106M 22µF MURATA 25V , X7R, 1210 GRM 32 E R71E 226 KE 15L

–90

47µF MURATA 16V, X5R, 1210 G R M 32E R61C47 6KE15 L

–100

0 5 10 15 20 25 30

Figure 80. Capacitance vs. DC Voltage Characteristics for Ceramic Capacitors

X5R (16V)

X7R (50V)

X5R (25V)

DC VOLTAGE (V

)

DC

08901-079

Electrolytic capacitors satisfy the bulk capacitance requirements for most high current applications. Because the ESR of electrolytic capacitors is much higher than that of ceramic capacitors, when using electrolytic capacitors, several MLCCs should be mounted in parallel to reduce the overall series resistance.

COMPENSATION NETWORK

Due to its current-mode architecture, the ADP1882/ADP1883 require Type II compensation. To determine the component values needed for compensation (resistance and capacitance values), it is necessary to examine the overall loop gain (H) of the converter at the unity gain frequency (f as follows:

H = 1 V/V = G

× ACS ×

M

Examining each variable at high frequency enables the unitygain transfer function to be simplified to provide expressions for the R

COMP

and C

component values.

COMP

Output Filter Impedance (Z

Examining the transfer function of the filter at high frequencies simplifies to

=

sC

1

OUT

Z

FILT

at the crossover frequency (s = 2πf

/10) when H = 1 V/V,

SW

V

OUT

× Z

)

CROSS

COMP

).

V

REF

FILT

× Z

FILT

Error Amplifier Output Impedance (Z

Assuming CC2 is significantly smaller than C

COMP

)

, CC2 can be

COMP

omitted from the output impedance equation of the error amplifier. The transfer function simplifies to

ffR

Z

COMP

=

CROSSCOMP

f

CROSS

ZERO

)( +

and

1

ff ×=

SWCROSS

12

where f

, the zero frequency, is set to be 1/4 of the crossover

ZERO

frequency for the ADP1882.

Error Amplifier Gain (GM)

The error amplifier gain (transconductance) is

= 500 µA/V

G

M

Current-Sense Loop Gain (GCS)

The current-sense loop gain is

1

=

CS

(A/V)

RAG×

ONCS

where:

(V/V) is programmable for 3 V/V, 6 V/V, 12 V/V, and 24 V/V

A

CS

(see the Programming Resistor (RES) Detect Circuit and Val l e y Current-Limit Setting sections).

is the channel impedance of the lower-side MOSFET.

R

ON

Crossover Frequency

The crossover frequency is the frequency at which the overall loop (system) gain is 0 dB (H = 1 V/V). For current-mode converters such as the ADP1882, it is recommended that the user set the crossover frequency between 1/10 and 1/15 of the switching frequency.

1

ff

=

SWCROSS

12

The relationship between C

COMP

and f

(zero frequency) is as

ZERO

follows:

ZERO

1

)

CRf××π=2

COMPCOMP

The zero frequency is set to 1/4 of the crossover frequency.

Combining all of the above parameters results in

R

COMP

π

ff

1

ZERO

×

fRC××π×=2

ZERO

2

CROSS

AG

M

f

CROSS

=

CROSS

+

COMP

V

Cf

CS

OUT

×

V

REF

Rev. 0 | Page 25 of 40

ADP1882/ADP1883

EFFICIENCY CONSIDERATIONS

One of the important criteria to consider in constructing a dc-to-dc converter is efficiency. By definition, efficiency is the ratio of the output power to the input power. For high power applications at load currents up to 20 A, the following are important MOSFET parameters that aid in the selection process:

• V

• R

• Q

• C

The following are the losses experienced through the external component during normal switching operation:

• Channel conduction loss (both MOSFETs)

• MOSFET driver loss

• MOSFET switching loss

• Body diode conduction loss (lower-side MOSFET)

• Inductor loss (copper and core loss)

Channel Conduction Loss

During normal operation, the bulk of the loss in efficiency is due to the power dissipated through MOSFET channel conduction. Power loss through the upper-side MOSFET is directly proportional to the duty cycle (D) for each switching period, and the power loss through the lower-side MOSFET is directly proportional to 1 − D for each switching period. The selection of MOSFETs is governed by the amount of maximum dc load current that the converter is expected to deliver. In particular, the selection of the lower-side MOSFET is dictated by the maximum load current because a typical high current application employs duty cycles of less than 50%. Therefore, the lower-side MOSFET is in the on state for most of the switching period.

MOSFET Driver Loss

Other dissipative elements are the MOSFET drivers. The contributing factors are the dc current flowing through the driver during operation and the Q

, the MOSFET support voltage applied between the

GS (TH)

gate and the source

, the MOSFET on resistance during channel

DS (ON)

conduction

, the total gate charge

G

, the input capacitance of the upper-side switch

N1

, the input capacitance of the lower-side switch

N2

[ ]

()

1

parameter of the external MOSFETs.

GATE

N2(ON)N1(ON)N1,N2(CL)

2

IRDRDP ××−+×=

LOAD

800

720

640

560

480

400

320

RECTIFI ER DROP (mV)

240

160

80

300 1000900800700600500400

Figure 81. Internal Rectifier Voltage Drop vs. Switching Frequency

VDD = 2.7V VDD = 3.6V VDD = 5.5V

SWITCHI NG FREQUENCY (kHz)

+125°C +25°C –40°C

08901-080

Switching Loss

The SW node transitions as a result of the switching activities of the upper-side and lower-side MOSFETs. This causes removal and replenishing of charge to and from the gate oxide layer of the MOSFET, as well as to and from the parasitic capacitance that is associated with the gate oxide edge overlap and the drain and source terminals. The current that enters and exits these charge paths presents additional loss during these transition times. This loss can be approximately quantified by using the following equation, which represents the time in which charge enters and exits these capacitive regions:

t

= R

SW-TRANS

GATE

× C

TOTAL

where:

R

is the gate input resistance of the MOSFET.

GATE

is the CGD + CGS of the external MOSFET used.

C

TOTAL

The ratio of this time constant to the period of one switching cycle is the multiplying factor to be used in the following expression:

t

TRANSSW

P

LOSSSW

-

)(

t

SW

LOAD

2

×××=

VI

IN

or

P

SW(LOSS)

= fSW × R

GATE

× C

TOTAL

× I

× VIN × 2

LOAD

( )

[ ]

DR

SW

)(

LOSSDR

()

[]

DD

SW

lowerFET

upperFET

+×+

DD

IVCfV

BIAS

DR

IVCfVP

+×=

BIAS

where:

V

is the driver bias voltage (that is, the low input voltage (VDD)

DR

minus the rectifier drop (see Figure 81)).

C

is the input gate capacitance of the upper-side MOSFET.

upperFET

is the input gate capacitance of the lower-side MOSFET.

C

lowerFET

I

is the dc current flowing into the upper and lower-side drivers.

BIAS

is the bias voltage.

V

DD

Rev. 0 | Page 26 of 40

ADP1882/ADP1883

t

I

Diode Conduction Loss

The ADP1882/ADP1883 employ anticross conduction circuitry that prevents the upper-side and lower-side MOSFETs from conducting current simultaneously. This overlap control is beneficial, avoiding large current flow that may lead to irreparable damage to the external components of the power stage. However, this blanking period comes with the trade-off of a diode conduction loss occurring immediately after the MOSFETs change states and continuing well into idle mode. The amount of loss through the body diode of the lower-side MOSFET during the antioverlap state is given by the following expression:

LOSSBODY

P

LOSSBODY

)(

t

SW

LOAD

2

×××=

VI

F

where:

t

is the body conduction time (refer to Figure 82 for

BODY(LOSS)

dead time periods).

t

is the period per switching cycle.

SW

is the forward drop of the body diode during conduction

V

F

(refer to the selected external MOSFET data sheet for more information about the V

80

72

64

56

48

40

32

24

BODY DIODE CO NDUCTION TI M E ( ns)

16

8

2.7 5.54.84.13.4

Figure 82. Body Diode Conduction Time vs. Low Voltage Input (V

parameter).

F

1MHz 300kHz

(V)

V

DD

+125°C +25°C –40°C

08901-081

)

DD

Inductor Loss

During normal conduction mode, further power loss is caused by the conduction of current through the inductor windings, which have dc resistance (DCR). Typically, larger sized inductors have smaller DCR values.

The inductor core loss is a result of the eddy currents generated within the core material. These eddy currents are induced by the changing flux, which is produced by the current flowing through the windings. The amount of inductor core loss depends on the core material, the flux swing, the frequency, and the core volume. Ferrite inductors have the lowest core losses, whereas powdered iron inductors have higher core losses. It is recommended to use shielded ferrite core material type inductors with the ADP1882/ ADP1883 for a high current, dc-to-dc switching application

to achieve minimal loss and negligible electromagnetic interference (EMI).

P

DCR(LOSS)

= DCR × I

2

+ Core Loss

LOAD

INPUT CAPACITOR SELECTION

The goal in selecting an input capacitor is to reduce or minimize input voltage ripple and to reduce the high frequency source impedance, which is essential for achieving predictable loop stability and transient performance.

The problem with using bulk capacitors, other than their physical geometries, is their large equivalent series resistance (ESR) and large equivalent series inductance (ESL). Aluminum electrolytic capacitors have such high ESR that they cause undesired input voltage ripple magnitudes and are generally not effective at high switching frequencies.

If bulk capacitors are to be used, it is recommended that multilayered ceramic capacitors (MLCC) be used in parallel, due to their low ESR values. This dramatically reduces the input voltage ripple amplitude as long as the MLCCs are mounted directly across the drain of the upper-side MOSFET and the source terminal of the lower-side MOSFET (see the Layout Considerations section). Improper placement and mounting of these MLCCs may cancel their effectiveness due to stray inductance and an increase in trace impedance.

()

VVV

−×

IN

OUT

II

,,

MAXLOADRMSCIN

OUT

×=

V

The maximum input voltage ripple and maximum input capacitor rms current occur at the end of the duration of 1 − D while the upper-side MOSFET is in the off state. The input capacitor rms current reaches its maximum at Time D. When calculating the maximum input voltage ripple, account for the ESR of the input capacitor as follows:

V

MAX,RIPPLE

RIPP

+ (I

LOAD,MAX

× ESR)

= V

where:

is usually 1% of the minimum voltage input.

V

RIPP

I

is the maximum load current.

LOAD,MAX

ESR is the equivalent series resistance rating of the input

capacitor used.

Inserting V

MAX,RIPPLE

into the charge balance equation to

calculate the minimum input capacitor requirement gives

C

IN,min

I

MAXLOAD

,

V

,

−

DD

)1(

×=

f

SWRIPPLEMAX

or

C

IN,min

=

4

,

Vf

RIPPLEMAXSW

,

MAXLOAD

where D = 50%.

Rev. 0 | Page 27 of 40

ADP1882/ADP1883

I

THERMAL CONSIDERATIONS

The ADP1882/ADP1883 are used for dc-to-dc, step down, high current applications that have an on-board controller and on-board MOSFET drivers. Because applications may require up to 20 A of load current delivery and be subjected to high ambient temperature surroundings, the selection of external upper-side and lower-side MOSFETs must be associated with careful thermal consideration to not exceed the maximum allowable junction temperature of 125°C. To avoid permanent or irreparable damage if the junction temperature reaches or exceeds 155°C, the part enters thermal shutdown, turning off both external MOSFETs, and does not reenable until the junction temperature cools to 140°C (see the Thermal Shutdown section).

The maximum junction temperature allowed for the ADP1882/ ADP1883 ICs is 125°C. This means that the sum of the ambient temperature (T is caused by the thermal impedance of the package and the internal power dissipation, should not exceed 125°C, as dictated by the following expression:

= TR × TA

T

J

where:

is the ambient temperature.

T

A

is the maximum junction temperature.

T

J

T

is the rise in package temperature due to the power

R

dissipated from within.

The rise in package temperature is directly proportional to its thermal impedance characteristics. The following equation represents this proportionality relationship:

= θJA × P

T

R

where:

is the thermal resistance of the package from the junction to

θ

JA

the outside surface of the die, where it meets the surrounding air.

P

is the overall power dissipated by the IC.

DR(LOSS)

The bulk of the power dissipated is due to the gate capacitance of the external MOSFETs. The power loss equation of the MOSFET drivers (see the MOSFET Driver Loss section in the Efficiency Consideration section) is

P

DR(LOSS)

+ [V

where:

is the input gate capacitance of the upper-side MOSFET.

C

upperFET

is the input gate capacitance of the lower-side MOSFET.

C

lowerFET

I

is the dc current (2 mA) flowing into the upper-side and

BIAS

lower-side drivers.

V

is the driver bias voltage (that is, the low input voltage (VDD)

DR

minus the rectifier drop (see Figure 81)).

is the bias voltage

V

DD

) and the rise in package temperature (TR), which

A

DR(LOSS)

= [VDR × (fSWC

× (fSWC

DD

upperFETVDR

lowerFETVDD

+ I

BIAS

)]

+ I

BIAS

)]

For example, if the external MOSFET characteristics are θ (10-lead MSOP) = 171.2°C/W, f C

upperFET

= 3.3 nF, C

= 3.3 nF, VDR = 5.12 V, and VDD = 5.5 V,

lowerFET

= 300 kHz, I

SW

= 2 mA,

BIAS

then the power loss is

= [VDR × (fSWC

P

DR(LOSS)

+ [V

× (fSWC

DD

lowerFETVDD

= [5.12 × (300 × 10 + [5.5 × (300 × 10

upperFETVDR

3

× 3.3 × 10−9 × 5.12 + 0.002)]

3

×3.3 × 10−9 × 5.5 + 0.002)]

+ I

BIAS

)]

+ I

BIAS

)]

= 77.13 mW

The rise in package temperature is

T

= θJA × P

R

DR(LOSS)

= 171.2°C × 77.13 mW = 13.2°C

Assuming a maximum ambient temperature environment of 85°C, the junction temperature is

= TR × TA = 13.2°C + 85°C = 98.2°C

T

J

which is below the maximum junction temperature of 125°C.

DESIGN EXAMPLE

The ADP1882/ADP1883 are easy to use, requiring only a few design criteria. For example, the example outlined in this section uses only four design criteria: V

= 12 V (typical), and fSW = 300 kHz.

V

IN

Input Capacitor

The maximum input voltage ripple is usually 1% of the minimum input voltage (11.8 V × 0.01 = 120 mV).

= 120 mV

V

RIPP

= V

V

MAX,RIPPLE

RIPP

− (I

= 120 mV − (15 A × 0.001) = 45 mV

MAXLOAD

C

IN,min

,

4

Vf

,

RIPPLEMAXSW

= 120 µF

Choose five 22 µF ceramic capacitors. The overall ESR of five 22 µF ceramic capacitors is less than 1 m.

I

= I

RMS

P

CIN

/2 = 7.5 A

LOAD

= (I

)2 × ESR = (7.5A)2 × 1 m = 56.25 mW

RMS

OUT

LOAD,MAX

==

= 1.8 V, I

× ESR)

= 15 A (pulsing),

LOAD

A15

3

mV105103004

×××

JA

Rev. 0 | Page 28 of 40

ADP1882/ADP1883

I

−

Inductor

Determine the inductor ripple current amplitude as follows:

LOAD

I ≈Δ

L

= 5 A

3

then calculate for the inductor value

−

VV

)(

,

MAXIN

=

L

=

OUT

×Δ

fI

L

SW

−

)V8.1V2.13(

3

××

10300V5

V

OUT

×

V

IN,MAX

V8.1

×

V2.13

= 1.03 µH

The inductor peak current is approximately

15 A + (5 A × 0.5) = 17.5 A

Therefore, an appropriate inductor selection is 1.0 µH with DCR = 3.3 m (7443552100) from Tabl e 8, with peak current handling of 20 A.

P

DCR(LOSS)

= DCR × = 0.003 × (15 A)2 = 675 mW

2

I

L

Current Limit Programming

The valley current is approximately

15 A − (5 A × 0.5) = 12.5 A

Assuming a lower-side MOSFET R

of 4.5 m, choosing 13 A

ON

as the valley current limit from Tabl e 7 and Figure 71 indicates that a programming resistor (RES) of 100 k corresponds to an

of 24 V/V.

A

CS

Choose a programmable resistor of R

= 100 kΩ for a current-

RES

sense gain of 24 V/V.

Output Capacitor

Assume a load step of 15 A occurs at the output, and no more than 5% is allowed for the output to deviate from the steady state operating point. Because the frequency is pseudo-fixed, the advantage of the ADP1882 is that the converter is able to respond quickly because of the immediate, though temporary, increase in switching frequency.

V

= 0.05 × 1.8 V = 90 mV

DROOP

Assuming the overall ESR of the output capacitor ranges from 5 m to 10 m,

Δ×=I

15

LOAD

Vf

Δ×

A

3

××

)(

DROOPSW

)mV90(10300

OUT

2

×=

C

= 1.11 mF

Therefore, an appropriate inductor selection is five 270 µF polymer capacitors with a combined ESR of 3.5 m.

Assuming an overshoot of 45 mV, determine if the output capacitor that was calculated previously is adequate.

2

IL

)(

×

C

=

OUT

()

−

=

××

LOAD

2

)(

26

)A15(101

22

)8.1()mV458.1(

−−

2

()

VVV

−Δ−

OUTOVSHTOUT

= 1.4 mF

Choose five 270 µF polymer capacitors.

The rms current through the output capacitor is

)(

−

RMS

1

2

×=

2

3

1

×=

3

−

I

1

VV

,

MAXIN

×

fL

SW

)V8.1V2.13(

3

10300F1

××

OUT

V

OUT

×

V

,

MAXIN

V8.1

=×

V2.13

A49.1

The power loss dissipated through the ESR of the output capacitor is

= (I

P

COUT

)2 × ESR = (1.5 A)2 × 1.4 m = 3.15 mW

RMS

Feedback Resistor Network Setup

It is recommended that RB = 15 k be used. Calculate RT as follows:

= 15 kΩ ×

R

T

V6.0

V)6.0V8.1(

= 30 kΩ

Compensation Network

To c al c ul ate R

COMP

, C

COMP

, and C

, the transconductance

PAR

parameter and the current-sense gain variable are required. The transconductance parameter (G

) is 500 µA/V, and the current-

M

sense loop gain is

G

where A

=

CS

RA

ONCS

and RON are taken from setting up the current limit

CS

11

=

005.026

×

A/V7.7

(see the Programming Resistor (RES) Detect Circuit and Val l e y Current-Limit Setting sections).

The crossover frequency is 1/12 of the switching frequency:

300 kHz/12 = 25 kHz

The zero frequency is 1/4 of the crossover frequency:

25 kHz/4 = 6.25 kHz

π

33

CROSS

M

Cf

AG

CS

OUT

×

V

REF

6

−

3.810500

××

33

−

1011.11025141.32

×××××

×

C

=

R

=

COMP

8.1

COMP

=

= 75 k

8.0

=

2

CROSS

1025

×

π

f

CROSS

3

COMP

1

2

×

ff

+

ZERO

×

33

1025.61025

×+×

1

fR

ZERO

1025.6107514.32

×××××

V

= 340 pF

Rev. 0 | Page 29 of 40

ADP1882/ADP1883

[

]

t

(

)

]

=×+

[

(

)

]

P

Loss Calculations

Duty cycle = 1.8/12 V = 0.15.

R

= 5.4 m.

ON (N2)

t

BODY(LOSS)

V

C

Q

R

= 20 ns (body conduction time).

= 0.84 V (MOSFET forward voltage).

F

= 3.3 nF (MOSFET gate input capacitance).

IN

= 17 nC (total MOSFET gate charge).

N1,N2

= 1.5  (MOSFET gate input resistance).

GATE

()

RDRDP ×−+×=

= (0.15 × 0.0054 + 0.85 × 0.0054) × (15 A) = 1.215 W

LOSSBODY

P

LOSSBODY

)(

= 20 ns × 300 × 10

)(

t

SW

3

× 15 A × 0.84 × 2

LOAD

VI

= 151.2 mW

= fSW × R

SW(LOSS)

= 300 × 103 × 1.5 Ω × 3.3 × 10 − 9 × 15 A × 12 × 2 = 534.6 mW

)(

LOSSDR

+

V

DD

f

SW

= (5.12 × (300 × 10 + (5.5 × (300 × 10 = 77.13 mW

= (I

P

2

I×1

N2(ON)N1(ON)N1,N2(CL)

F

LOAD

2

×××=

COUT

P

DCR(LOSS)

= (I

P

CIN

P

LOSS

= 1.215 W + 151.2 mW + 534.6 mW + 77.13 mW +

)2 × ESR = (1.5 A)2 × 1.4 m = 3.15 mW

RMS

= DCR × = 0.003 × (15 A)2 = 675 mW

)2 × ESR = (7.5 A)2 × 1 m = 56.25 mW

RMS

= P

+ P

N1,N2

3.15 mW + 675 mW + 56.25 mW = 2.62 W

× C

GATE

DR

upperFET

3

× 3.3 × 10−9 × 5.12 + 0.002))

3

× 3.3 × 10−9 × 5.5 + 0.002))

2

I

LOAD

BODY(LOSS)

TOTAL

SW

VC +×

DD

+ PSW + P

× I

LOAD

upperFET

I

BIAS

× VIN × 2

DR

+ PDR + P

DCR

IVCfVP

BIAS

COUT

+ P

CIN

Rev. 0 | Page 30 of 40

ADP1882/ADP1883

EXTERNAL COMPONENT RECOMMENDATIONS

The configurations that are listed in Table 8 are with f (BSC042N030MS G), V

= 5 V, and a maximum load current of 14 A. The ADP1883 models that are listed in Table 8 are the PSM

DD

versions of the device.

Table 8. External Component Values

Marking Code

SAP Model ADP1882 ADP1883

ADP1882ARMZ-0.3-R7/

ADP1883ARMZ-0.3-R7

LGF LGJ 0.8 13 5 × 22

LGF LGJ 1.2 13 5 × 225 4 × 5602 1.0 38.3 911 91 7.5 LGF LGJ 1.8 13 5 × 225 5 × 2703 1.2 38.3 703 70 18.75 LGF LGJ 2.5 13 5 × 225 3 × 2703 1.53 38.3 703 70 31.9 LGF LGJ 3.3 13 5 × 225 3 × 3304 2.0 38.3 703 70 46.9 LGF LGJ 5 13 4 × 225 3304 3.27 27.4 985 98 78.8 LGF LGJ 7 13 4 × 225 225+ (4 × 476) 3.44 27.4 985 98 116.3 LGF LGJ 1.2 16.5 5 × 225 4 × 5602 1.0 38.3 911 91 7.5 LGF LGJ 1.8 16.5 4 × 225 4 × 2703 1.0 38.3 729 73 18.8 LGF LGJ 2.5 16.5 4 × 225 4 × 2703 1.67 38.3 729 73 31.9 LGF LGJ 3.3 16.5 4 × 225 3 × 3304 2.00 38.3 729 73 46.9 LGF LGJ 5 16.5 3 × 225 2 × 1507 3.84 27.4 1020 102 78.8 LGF LGJ 7 16.5 3 × 225 225+ 4 × 476 4.44 27.4 1020 102 116.3 ADP1882ARMZ-0.6-R7/

ADP1883ARMZ-0.6-R7

LGG LGK 0.8 5.5 5 × 22

LGG LGK 1.2 5.5 5 × 225 4 × 2703 0.47 38.3 401 40 7.5 LGG LGK 1.8 5.5 5 × 225 3 × 2703 0.47 38.3 334 33 18.8 LGG LGK 2.5 5.5 5 × 225 3 × 1808 0.47 38.3 334 33 31.9 LGG LGK 1.2 13 5× 225 5 × 2703 0.47 38.3 501 50 7.5 LGG LGK 1.8 13 5 × 109 3 × 3304 0.72 38.3 378 38 18.8 LGG LGK 2.5 13 5 × 109 3 × 2703 0.90 38.3 378 38 31.9 LGG LGK 3.3 13 5 × 109 2 × 2703 1.00 38.3 378 38 46.9 LGG LGK 5 13 5 × 109 1507 1.76 27.4 529 53 78.8 LGG LGK 1.2 16.5 3 × 109 4 × 2703 0.47 38.3 445 45 7.5 LGG LGK 1.8 16.5 4 × 109 2 × 3304 0.72 38.3 401 40 18.8 LGG LGK 2.5 16.5 4 × 109 3 × 2703 0.90 38.3 401 40 31.9 LGG LGK 3.3 16.5 4 × 109 3304 1.0 38.3 364 36 46.9 LGG LGK 5 16.5 4 × 109 4 × 476 2.0 27.4 510 51 78.8 LGG LGK 7 16.5 4 × 109 3 × 476 2.0 27.4 468 47 116.3 ADP1882ARMZ-1.0-R7/

ADP1883ARMZ-1.0-R7

LGH LGL 0.8 5.5 5 × 22

LGH LGL 1.2 5.5 5 × 225 2 × 3304 0.22 38.3 275 27 7.5 LGH LGL 1.8 5.5 3 × 225 3 × 1808 0.22 38.3 200 20 18.8 LGH LGL 2.5 5.5 3 × 225 2703 0.22 38.3 200 20 31.9 LGH LGL 1.2 13 4 × 109 3 × 3304 0.22 38.3 286 29 7.5 LGH LGL 1.8 13 4 × 109 3 × 2703 0.47 38.3 259 26 18.8 LGH LGL 2.5 13 4 × 109 2 x 2703 0.47 38.3 259 26 31.9 LGH LGL 3.3 13 5 × 109 2703 0.72 38.3 259 26 46.9 LGH LGL 5 13 4 × 109 3 × 476 1.0 27.4 330 33 78.8 LGH LGL 1.2 16.5 4 × 109 4 × 2703 0.47 38.3 401 40 7.5 LGH LGL 1.8 16.5 4 × 109 3 × 2703 0.47 38.3 321 32 18.8 LGH LGL 2.5 16.5 4 × 109 3 × 1808 0.72 38.3 286 29 31.9 LGH LGL 3.3 16.5 4 × 109 2703 0.72 38.3 267 27 46.9

= 1/12 × fSW, f

CROSS

V

VIN

OUT

(V)

= ¼ × f

ZERO

CIN (μF)

5

5 × 5602 0.47 38.3 911 91 0.0

5

4 × 5602 0.22 38.3 418 42 0.0

5

4 × 2703 0.22 38.3 275 27 0.0

C

OUT

(μF)

CROSS

, R

= 100 k, R

RES

L1 (μH)

= 15 k, RON = 5.4 mΩ

BOT

RC (kΩ)

C

COMP

(pF)

C (pF)

PAR

R

TOP

(kΩ)

Rev. 0 | Page 31 of 40

ADP1882/ADP1883

Marking Code

V

VIN

SAP Model ADP1882 ADP1883

OUT

(V)

LGH LGL 5 16.5 3 × 10 LGH LGL 7 16.5 3 × 10

1

See the section (see ). Inductor Selection Table 9

2

560 μF Panasonic (SP-series) 2 V, 7 mΩ, 3.7 A EEFUE0D561LR (4.3 mm × 7.3 mm × 4.2 mm).

3

270 μF Panasonic (SP-series) 4 V, 7 mΩ, 3.7 A EEFUE0G271LR (4.3 mm × 7.3 mm × 4.2 mm).

4

330 μF Panasonic (SP-series) 4 V, 12 mΩ, 3.3 A EEFUE0G331R (4.3 mm × 7.3 mm × 4.2 mm).

5

22 μF Murata 25 V, X7R, 1210 GRM32ER71E226KE15L (3.2 mm × 2.5 mm × 2.5 mm).

6

47 μF Murata 16 V, X5R, 1210 GRM32ER61C476KE15L (3.2 mm × 2.5 mm × 2.5 mm).

7

150 μF Panasonic (SP-series) 6.3 V, 10 mΩ, 3.5 A EEFUE0J151XR (4.3 mm × 7.3 mm × 4.2 mm).

8

180 μF Panasonic (SP-series) 4 V, 10 mΩ, 3.5 A EEFUE0G181XR (4.3 mm × 7.3 mm × 4.2 mm).

9

10 μF TDK 25 V, X7R, 1210 C3225X7R1E106M.

Table 9. Recommended Inductors

L (μH) DCR (mΩ) I

(A) Dimension (mm) Manufacturer Model Number

SAT

0.12 0.33 55 10.2 × 7 Wurth Electronics 744303012

0.22 0.33 30 10.2 × 7 Wurth Electronics 744303022

0.47 0.8 50 14.2 × 12.8 Wurth Electronics 744355147

0.72 1.65 35 10.5 × 10.2 Wurth Electronics 744325072

0.9 1.6 28 13 × 12.8 Wurth Electronics 744355090

1.2 1.8 25 10.5 × 10.2 Wurth Electronics 744325120

1.0 3.3 20 10.5 × 10.2 Wurth Electronics 7443552100

1.4 3.2 24 14 × 12.8 Wurth Electronics 744318180

2.0 2.6 22 13.2 × 12.8 Wurth Electronics 7443551200

0.8 27.5 Sumida CEP125U-0R8

CIN (μF)

C

OUT

(μF)

9

3 × 47

9

225 + 47

L1 (μH)

6

1.4 27.4 330 33 78.8

6

1.4 27.4 281 28 116.3

RC (kΩ)

C

COMP

(pF)

C

R

TOP

(kΩ)

PAR

(pF)

Table 10. Recommended MOSFETs

R

VGS = 4.5 V

ON

(mΩ)

ID (A)

VDS (V)

CIN (nF)

Q

TOTAL

(nC) Package Manufacturer Model Number

Upper-Side MOSFET (Q1/Q2) 5.4 47 30 3.2 20 PG-TDSON8 Infineon BSC042N03MS G

10.2 53 30 1.6 10 PG-TDSON8 Infineon BSC080N03MS G

6.0 19 30 35 SO-8 Vishay Si4842DY 9 14 30 2.4 25 SO-8 International Rectifier IRF7811 Lower-Side MOSFET (Q3/Q4) 5.4 47 30 3.2 20 PG-TDSON8 Infineon BSC042N030MS G

10.2 82 30 1.6 10 PG-TDSON8 Infineon BSC080N030MS G

6.0 19 30 35 SO-8 Vishay Si4842DY

Rev. 0 | Page 32 of 40

ADP1882/ADP1883

LAYOUT CONSIDERATIONS

The performance of a dc-to-dc converter depends highly on how the voltage and current paths are configured on the printed circuit board (PCB). Optimizing the placement of sensitive analog and power components are essential to minimize output ripple, maintain tight regulation specifications, and reduce PWM jitter and electromagnetic interference.

HIGH VOLTAGE INPUT

V

= 5V

DD

JP1

HIGH VOLTAGE INPUT

V

IN

= 12V

Figure 83 shows the schematic of a typical ADP1882/ADP1883 used for a high power application. Blue traces denote high current pathways. VIN, PGND, and V

traces should be wide and

OUT

possibly replicated, descending down into the multiple layers. Vias should populate, mainly around the positive and negative terminals of the input and output capacitors, alongside the source of Q1/Q2, the drain of Q3/Q4, and the inductor.

C3

22µFC422µFC522µFC622µFC722µFC8N/A

1.0µH

R6 2

C13

1.5nF

MURATA: (HIGH VOLTAGE INPUT CAPACITORS)

22µF, 25V, X7R, 1210 GRM32ER71E226KE15 L

PANASONIC: (OUTPUT CAPACITORS)

270µF SP- S E R IES, 4V, 7m EEFUE0G271LR

INFINEON MOSFETs (NO CONNECTION FOR Q2/Q4:

BSC042N03MS G (LOWER SI DE) BSC080N03MS G (UPP E R S IDE)

WURTH INDUCTO RS:

1µH, 3.3m, 20A 7443552100

C20

270µF

+

C14 TO C19 N/A

+

270µF

C21

V

OUT

+

270µF

= 1.8V, 15A

+

C22

270µF

C23

+

C24

270µF

+

08901-082

70pF

V

C

OUT

F

R1 18.75k

15k

C2

0.1µF

C

700pF

R

C

38.1k

R2

C1

1µF

ADP1882/

ADP1883

1

VIN

2

COMP/EN9SW

3

FB

4

GND

5

VDD

BST

DRVH

PGND

DRVL

10

8

7

6

100k

C12 100nF

R4 0

R5

Q1 Q2

Q3 Q4

Figure 83. ADP1882 High Current Evaluation Board Schematic (Blue Traces Indicate High Current Paths)

Rev. 0 | Page 33 of 40

ADP1882/ADP1883

SENSITIVE ANALOG COMPONENTS LOCATED FAR FROM THE NOISY POWER S ECTION.

SEPARATE A NALOG GROUND PLANE FO R THE ANALOG COMPONE NTS (THAT I S , COMPENSATION AND FEEDBACK RES ISTORS ).

OUTPUT CAP ACITORS ARE MOUNTED ON THE

BYPASS POWER CAPACIT OR (C1) FOR VDD BIAS DE COUPLING AND HIGH FREQUENCY CAPACITOR (C2) AS CLOSE AS POSSIBLE TO THE IC.

INPUT CAPACITORS ARE MOUNTED CLOSE TO DRAIN O F Q1/Q 2 AND SOURCE OF Q3/ Q4.

RIGHTMOST AREA OF THE EVB, WRAPPING BACK AROUND TO THE MAIN POWER GROUND PLANE, WHERE IT MEETS WITH THE NEGATIVE TERMINALS OF T HE INPUT CAPACITORS.

08901-083

Figure 84. Overall Layout of the ADP1882 High Current Evaluation Board

Figure 85. Layer 2 of Evaluation Board

Rev. 0 | Page 34 of 40

08901-084

ADP1882/ADP1883

T

G

V

T

A

T

G

BOTTO M RE S I STOR

AP TO THE ANALO

GROUND PLANE.

OUT SENSE TAP LINE EXTENDING BACK TO THE TO P RESISTOR IN THE FEEDBACK DIVIDER NE T WORK (SEE F IGURE 82).

HIS OVERLAPS WITH PGND SENSE

AP LINE EX TENDING BACK TO THE

NALOG PLANE (SEE FIGURE 86, LAYER 4 FOR PGND TAP) .

Figure 86. Layer 3 of Evaluation Board

08901-085

BOTTO M RE S I STOR

AP TO THE ANALO

GROUND PLANE.

PGND SENSE TAP FROM NEGATI V E TERMINALS OF OUTPUT BULK CAPACITORS. THIS TRA CK P LACEMENT S HOULD BE DIRECTLY BELOW THE VOUT SENSE LINE FROM FIGURE 84.

8901-086

Figure 87. Layer 4 (Bottom Layer) of Evaluation Board

Rev. 0 | Page 35 of 40

ADP1882/ADP1883

IC SECTION (LEFT SIDE OF EVALUATION BOARD)

A dedicated plane for the analog ground plane (GND) should be separate from the main power ground plane (PGND). With the shortest path possible, connect the analog ground plane to the GND pin (Pin 4). This plane should be on only the top layer of the evaluation board. To avoid crosstalk interference, there should not be any other voltage or current pathway directly below this plane on Layer 2, Layer 3, or Layer 4. Connect the negative terminals of all sensitive analog components to the analog ground plane. Examples of such sensitive analog components include the bottom resistor of the resistor divider, the high frequency bypass capacitor for biasing (0.1 µF), and the compensation network.

Mount a 1 µF bypass capacitor directly across VDD (Pin 5) and PGND (Pin 7). In addition, a 0.1 µF should be tied across VDD (Pin 5) and GND (Pin 4).

POWER SECTION

As shown in Figure 84, an appropriate configuration to localize large current transfer from the high voltage input (V put (V

), and then back to the power ground, puts the VIN

OUT

plane on the left, the output plane on the right, and the main power ground plane in between the two. Current transfers from the input capacitors to the output capacitors, through Q1/Q2, during the on state (see Figure 88). The direction of this current (yellow arrow) is maintained as Q1/Q2 turns off and Q3/Q4 turns on. When Q3/Q4 turns on, the current direction continues to be maintained (red arrow) as it circles from the power ground terminal of the bulk capacitor to the output capacitors, through the Q3/Q4. Arranging the power planes in this manner minimizes the area in which changes in flux occur if the current through Q1/Q2 stops abruptly. Sudden changes in flux, usually at the source terminals of Q1/Q2 and the drain terminals of Q3/Q4, cause large dV/dt’s at the SW node.

) to the out-

IN

The SW node is near the top of the evaluation board. The SW node should use the least amount of area possible and be kept away from any sensitive analog circuitry and components because this is where most sudden changes in flux density occur. When possible, replicate this pad onto Layer 2 and Layer 3 for thermal relief and eliminate any other voltage and current pathways directly beneath the SW node plane. Populate the SW node plane with vias, mainly around the exposed pad of the inductor terminal and around the perimeter of the source of Q1/Q2 and the drain of Q3/Q4. The output voltage power plane (V

) is at the right-

OUT

most end of the evaluation board. This plane should be replicated, descending down to multiple layers with vias surrounding the inductor terminal and the positive terminals of the output bulk capacitors. Ensure that the negative terminals of the output capacitors are placed close to the main power ground (PGND), as previously mentioned. All of these points form a tight circle (component geometry permitting) that minimizes the area of flux change as the event switches between D and 1 − D.

DIFFERENTIAL SENSING

Because the ADP1882/ADP1883 operate in valley currentmode control, a differential voltage reading is taken across the drain and source of the lower-side MOSFET. The drain of the lower-side MOSFET should be connected as close as possible to Pin 9 (SW) of the IC. Likewise, connect the source as close as possible to Pin 7 (PGND) of the IC. When possible, both of these track lines should be narrow and away from any other active device or voltage/current paths.

SW

PGND

SW

VOUT

VIN PGND

Figure 88. Primary Current Pathways During the On State of the Upper-Side

MOSFET (Left Arrow) and the On State of the Lower-Side MOSFET (Right Arrow)

08901-087

Rev. 0 | Page 36 of 40

LAYER 1: SENSE LINE FOR S W (DRAIN OF LO W E R MO SF E T )

Figure 89. Drain/Source Tracking Tapping of the Lower-Side MOSFET for

CS Amp Differential Sensing (Yellow Sense Line on Layer 2)

LAYER 1: SENSE LINE FO R P GND (SOURCE OF L O W E R MO S F ET )

Differential sensing should also be applied between the outermost output capacitor to the feedback resistor divider (see Figure 86 and Figure 87). Connect the positive terminal of the output capacitor to the top resistor (R

). Connect the negative terminal

T

of the output capacitor to the negative terminal of the bottom resistor, which connects to the analog ground plane, as well. Both of these track lines, as previously mentioned, should be narrow and away from any other active device or voltage/ current paths.

08901-088

ADP1882/ADP1883

TYPICAL APPLICATIONS CIRCUITS

DUAL-INPUT, 300 kHz HIGH CURRENT APPLICATIONS CIRCUIT

HIGH VOLTAGE INPUT

V

= 5V

DD

JP1

HIGH VOLTAGE INPUT

= 12V

V

IN

70pF

V

C

OUT

F

R1 18.75k

15k

C2

0.1µF

C

700pF

R

C

38.1k

R2

C1

1µF

ADP1882/

ADP1883

1

VIN

2

COMP/EN9SW

3

FB

4

GND

5

VDD

BST

DRVH

PGND

DRVL

10

8

7

6

100k

C12 100nF

R4 0

R5

Figure 90. Applications Circuit for 12 V Input, 1.8 V Output, 15 A, 300 kHz (Q2/Q4 No Connect)

SINGLE-INPUT, 600 kHz APPLICATIONS CIRCUIT

HIGH VOLTAGE INPUT

JP1

C

F

R1 31.6k

C2

0.1µF

33.4pF

R

38.3k

R2

15k

C

1µF

C1

34pF

V

C

OUT

Figure 91. Applications Circuit for 5.5 V Input, 2.5 V Output, 15 A, 600 kHz (Q2/Q4 No Connect)

ADP1882/

ADP1883

1

VIN

2

COMP/EN9SW

3

FB

4

GND

5

VDD

BST

DRVH

PGND

DRVL

10

8

7

6

C12 100nF

R4

0

OPEN

R5

Q1 Q2

Q3 Q4

V

= 5.5V

IN

Q1 Q2

Q3 Q4

C3

22µFC422µFC522µFC622µFC722µFC8N/A

1.0µH

R6 2

C13

1.5nF

MURATA: (HIGH VOLTAGE INPUT CAPACITORS)

22µF, 25V, X7R, 1210 GRM32ER71E226KE15 L

PANASONIC: (OUTPUT CAPACITORS)

270µF SP- S E R IES, 4V, 7m EEFUE0G271LR

INFINEON MOSFETs (NO CONNECTION FOR Q2/Q4:

BSC042N03MS G (LO WER SIDE) BSC080N03MS G (UPPE R SI DE )

WURTH INDUCTO RS:

1µH, 3.3m, 20A 7443552100

C3

22µFC422µFC522µFC622µFC722µFC8N/A

0.47µH

R6 2

C13

1.5nF

MURATA: (HIGH VOLTAGE INPUT CAPACITORS)

22µF, 25V, X7R, 1210 GRM32ER71E226KE15 L

PANASONIC: (OUTPUT CAPACITORS)

180µF SP-S E R IES, 4V, 10m EEFUE0G181XR

INFINEO N M OSFETs ( NO CONNECTION FOR Q2/ Q4:

BSC042N03MS G (L OWER SIDE ) BSC080N03MS G (UPPER SIDE)

WURTH INDUCTO RS :

0.47µH, 0. 8m , 50A 74435514 7

C20

270µF

+

C14 TO C19 N/A

C20

180µF

+

C14 TO C1 9 N/A

+

270µF

+

180µF

C21

V

OUT

+

270µF

OUT

+

180µF

= 1.8V, 15A

+

C22

270µF

= 1.8V, 15A

+

C22

C23

C23 N/A

+

C24

270µF

C24

N/A

+

08901-089

+

08901-090

Rev. 0 | Page 37 of 40

ADP1882/ADP1883

DUAL-INPUT, 300 kHz HIGH CURRENT APPLICATIONS CIRCUIT

HIGH VOLTAGE INPUT

V

= 5V

DD

JP1

HIGH VOLTAGE INPUT

V

= 13V

IN

70pF

V

OUT

C

F

0.1µF

R1 7.5k

15k

C2

C

1000pF

R

C

24.9k

R2

C1

1µF

ADP1882/

ADP1883

1

VIN

2

COMP/EN9SW

3

FB

4

GND

5

VDD

BST

DRVH

PGND

DRVL

10

8

7

6

100k

C12 100nF

R5

Q1 Q2

Q3 Q4

C3

22µFC422µFC522µFC622µFC722µFC822µF

0.8µH

R6 2

C13

1.5nF

MURATA: (HIGH VOLTAGE INPUT CAPACITORS)

22µF, 25V, X7R, 1210 GRM32ER71E226KE15 L

PANASONIC: (OUTPUT CAPACITORS)

270µF SP- S E R IES, 4V, 7m EEFUE0G271LR

INFINEON MOSFETs (NO CONNECTION FOR Q2/Q4:

BSC042N03MS G (LOWER SI DE) BSC080N03MS G (UPP E R S IDE)

WURTH INDUCTO RS:

0.8µH, 27.5m, SUMIDA CEP 125U- 0 R8

C20

270µF

+

C14 TO C19 N/A

+

C21

270µF

V

OUT

+

Figure 92. Applications Circuit for 13 V Input, 1.8 V Output, 20 A, 300 kHz (Q2/Q4 No Connect)

= 1.8V, 20A

C22

270µF

+

C23

270µF

+

C24

270µF

+

08901-091

Rev. 0 | Page 38 of 40

ADP1882/ADP1883

OUTLINE DIMENSIONS

3.10

3.00

2.90

10

6

3.10

3.00

2.90

PIN 1

IDENTIFIER

0.95

0.85

0.75

0.15

0.05

COPLANARITY

1

0.50 BSC

0.10

COMPLIANT TO JEDEC STANDARDS MO-187-BA

Figure 93. 10-Lead Mini Small Outline Package [MSOP]

ORDERING GUIDE

1

Model

ADP1882ARMZ-0.3-R7 −40°C to +125°C 10-Lead Mini Small Outline Package [MSOP] RM-10 LGF ADP1882ARMZ-0.6-R7 −40°C to +125°C 10-Lead Mini Small Outline Package [MSOP] RM-10 LGG ADP1882ARMZ-1.0-R7 −40°C to +125°C 10-Lead Mini Small Outline Package [MSOP] RM-10 LGH ADP1882ARMZ-0.3-EVALZ Forced PWM, 300 kHz Evaluation Board ADP1882ARMZ-0.6-EVALZ Forced PWM, 600 kHz Evaluation Board ADP1882ARMZ-1.0-EVALZ Forced PWM, 1.0 MHz Evaluation Board ADP1883ARMZ-0.3-R7 −40°C to +125°C 10-Lead Mini Small Outline Package [MSOP] RM-10 LGJ ADP1883ARMZ-0.6-R7 −40°C to +125°C 10-Lead Mini Small Outline Package [MSOP] RM-10 LGK ADP1883ARMZ-1.0-R7 −40°C to +125°C 10-Lead Mini Small Outline Package [MSOP] RM-10 LGL ADP1883ARMZ-0.3-EVALZ Power Saving Mode, 300 kHz Evaluation Board ADP1883ARMZ-0.6-EVALZ Power Saving Mode, 600 kHz Evaluation Board ADP1883ARMZ-1.0-EVALZ Power Saving Mode, 1.0 MHz Evaluation Board

1

Z = RoHS Compliant Part.

Temperature Range Package Description

5.15

4.90

4.65

5

15° MAX

6° 0°

0.23

0.13

0.30

0.15

1.10 MAX

(RM-10)

Dimensions shown in millimeters

0.70

0.55

0.40

091709-A

Package Option

Branding

Rev. 0 | Page 39 of 40

ADP1882/ADP1883

NOTES

Rev. 0 | Page 40 of 40

Datasheet ADP1882 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

TYPICAL APPLICATIONS CIRCUIT

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

BOUNDARY CONDITION

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

ADP1882/ADP1883 BLOCK DIAGRAM

THEORY OF OPERATION

STARTUP

SOFT START

PRECISION ENABLE CIRCUITRY

UNDERVOLTAGE LOCKOUT

THERMAL SHUTDOWN

PROGRAMMING RESISTOR (RES) DETECT CIRCUIT

VALLEY CURRENT-LIMIT SETTING

HICCUP MODE DURING SHORT CIRCUIT

SYNCHRONOUS RECTIFIER

POWER SAVING MODE (PSM) VERSION (ADP1883)

TIMER OPERATION

PSEUDO-FIXED FREQUENCY

APPLICATIONS INFORMATION

FEEDBACK RESISTOR DIVIDER

INDUCTOR SELECTION

OUTPUT RIPPLE VOLTAGE (ΔVRR)

OUTPUT CAPACITOR SELECTION

COMPENSATION NETWORK

Error Amplifier Gain (GM)

Current-Sense Loop Gain (GCS)

Crossover Frequency

EFFICIENCY CONSIDERATIONS

Channel Conduction Loss

MOSFET Driver Loss

Switching Loss

Diode Conduction Loss

Inductor Loss

INPUT CAPACITOR SELECTION

THERMAL CONSIDERATIONS

DESIGN EXAMPLE

Input Capacitor

Inductor

Current Limit Programming

Output Capacitor

Feedback Resistor Network Setup

Compensation Network

Loss Calculations

EXTERNAL COMPONENT RECOMMENDATIONS

LAYOUT CONSIDERATIONS

IC SECTION (LEFT SIDE OF EVALUATION BOARD)

POWER SECTION

DIFFERENTIAL SENSING

TYPICAL APPLICATIONS CIRCUITS

DUAL-INPUT, 300 kHz HIGH CURRENT APPLICATIONS CIRCUIT

SINGLE-INPUT, 600 kHz APPLICATIONS CIRCUIT

DUAL-INPUT, 300 kHz HIGH CURRENT APPLICATIONS CIRCUIT

OUTLINE DIMENSIONS

ORDERING GUIDE