Power input voltage as low as 2.75 V to 20 V
Bias supply voltage range: 2.75 V to 5.5 V
Minimum output voltage: 0.8 V
0.8 V reference voltage with ±1.0% accuracy
Supports all N-channel MOSFET power stages
Available in 300 kHz, 600 kHz, and 1.0 MHz options
No current-sense resistor required
Power saving mode (PSM) for light loads (ADP1883 only)
Resistor-programmable current-sense gain
Thermal overload protection
Short-circuit protection
Precision enable input
Integrated bootstrap diode for high-side drive
140 μA shutdown supply current
Starts into a precharged load
Small, 10-lead MSOP package
APPLICATIONS
Telecom and networking systems
Mid to high end servers
Set-top boxes
DSP core power supplies
R
TOP
OUT
VDD= 2.75V TO 5.5V
100
95
90
85
80
75
70
65
60
55
EFFICIENCY (%)
50
45
40
35
30
25
1001k10k100k
Figure 2. ADP1882/ADP1883 Efficiency vs. Load Current
The ADP1882/ADP1883 are versatile current-mode, synchronous
step-down controllers that provide superior transient response,
optimal stability, and current-limit protection by using a constant
on-time, pseudo-fixed frequency with a programmable currentlimit, current-control scheme. In addition, these devices offer
optimum performance at low duty cycles by using valley currentmode control architecture. This allows the ADP1882/ADP1883
to drive all N-channel power stages to regulate output voltages
as low as 0.8 V.
The ADP1883 is the power saving mode (PSM) version of the
device and is capable of pulse skipping to maintain output
regulation while achieving improved system efficiency at light
loads (see the Power Saving Mode (PSM) Version (ADP1883)
section for more information).
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Available in three frequency options (300 kHz, 600 kHz, and
1.0 MHz, plus the PSM option), the ADP1882/ADP1883 are
well suited for a wide range of applications. These ICs not only
operate from a 2.75 V to 5.5 V bias supply, but they also can
accept a power input as high as 20 V.
In addition, an internally fixed soft start period is included to limit
input in-rush current from the input supply during startup and
to provide reverse current protection during soft start for a precharged output. The low-side current-sense, current-gain scheme
and integration of a boost diode, along with the PSM/forced
pulse-width modulation (PWM) option, reduce the external
part count and improve efficiency.
The ADP1882/ADP1883 operate over the −40°C to +125°C
junction temperature range and are available in a 10-lead MSOP.
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). VDD = 5 V, BST − SW = 5 V,
V
= 13 V. The specifications are valid for TJ = −40°C to +125°C, unless otherwise specified.
IN
Table 1.
Parameter Symbol Conditions Min Typ Max Unit
POWER SUPPLY CHARACTERISTICS
High Input Voltage Range VIN ADP1882ARMZ-0.3/ADP1883ARMZ-0.3 (300 kHz) 2.75 12 20 V
ADP1882ARMZ-0.6/ADP1883ARMZ-0.6 (600 kHz) 2.75 12 20 V
ADP1882ARMZ-1.0/ADP1883ARMZ-1.0 (1.0 MHz) 3.0 12 20 V
Low Input Voltage Range VDD C
ADP1882ARMZ-0.3/ADP1883ARMZ-0.3 (300 kHz) 2.75 5 5.5 V
ADP1882ARMZ-0.6/ADP1883ARMZ-0.6 (600 kHz) 2.75 5 5.5 V
ADP1882ARMZ-1.0/ADP1883ARMZ-1.0 (1.0 MHz) 3.0 5 5.5 V
Quiescent Current I
Shutdown Current I
Q_DD
DD, SD
+ I
+ I
Q_BST
BST, SD
Undervoltage Lockout UVLO Rising VDD (see Figure 35 for temperature variation) 2.65 V
UVLO Hysteresis Falling VDD from operational state 190 mV
SOFT START
Soft Start Period See Figure 58 3.0 ms
ERROR AMPLIFIER
FB Regulation Voltage VFB T
T
T
Transconductance GM 300 520 730 μs
FB Input Leakage Current I
FB = 0.8 V, COMP/EN = released 1 50 nA
FB, LEAK
CURRENT-SENSE AMPLIFIER GAIN
Programming Resistor (RES)
RES = 47 kΩ ± 1% 2.98 3.4 3.7 V/V
Value from DRVL to PGND
RES = 22 kΩ ± 1% 6 6.6 7.4 V/V
RES = none 24.1 26.7 29.3 V/V
RES = 100 kΩ ± 1% 12.1 13.4 14.7 V/V
SWITCHING FREQUENCY
ADP1882ARMZ-0.3/
300 kHz
ADP1883ARMZ-0.3 (300 kHz)
On Time VIN = 5 V, V
Minimum On Time VIN = 20 V 145 190 ns
Minimum Off Time 84% duty cycle (maximum) 340 400 ns
ADP1882ARMZ-0.6/
600 kHz
ADP1883ARMZ-0.6 (600 kHz)
On Time VIN = 5 V, V
Minimum On Time VIN = 20 V, V
Minimum Off Time 65% duty cycle (maximum) 340 400 ns
ADP1882ARMZ-1.0/
1.0 MHz
ADP1883ARMZ-1.0 (1.0 MHz)
On Time VIN = 5 V, V
Minimum On Time VIN = 20 V 60 85 ns
Minimum Off Time 45% duty cycle (maximum) 340 400 ns
= 1 μF to PGND, CIN = 0.22 μF to GND
IN
FB = 1.5 V, no switching 1.1 mA
COMP/EN < 285 mV 140 215 μA
= 25°C 800 mV
J
= −40°C to +85°C 795.3 800 805.5 mV
J
= −40°C to +125°C 792.8 800 808.0 mV
J
Typical values measured at 50% time points with
0 nF at DRVH and DRVL; maximum values are
guaranteed by bench evaluation
= 2 V, TJ = 25°C 1115 1200 1285 ns
OUT
= 2 V, TJ = 25°C 490 540 585 ns
OUT
= 0.8 V 82 110 ns
OUT
= 2 V, TJ = 25°C 280 312 340 ns
OUT
1
Rev. 0 | Page 3 of 40
ADP1882/ADP1883
Parameter Symbol Conditions Min Typ Max Unit
OUTPUT DRIVER CHARACTERISTICS
High-Side Driver
Output Source Resistance I
Output Sink Resistance I
Rise Time
Fall Time
Output Source Resistance I
Output Sink Resistance I
2
Rise Time
Fall Time
2
t
t
V
R, DRVL
V
F, D RV L
Propagation Delays
DRVL Fall to DRVH Rise
DRVH Fall to DRVL Rise
SW Leakage Current I
2
2
t
t
BST − SW = 4.4 V (see Figure 60) 22 ns
TPDH, DRVH
BST − SW = 4.4 V (see Figure 61) 24 ns
TPDH, DRVL
BST = 25 V, SW = 20 V, VDD = 5.5 V 110 μA
SW, LEAK
Integrated Rectifier
Channel Impedance I
PRECISION ENABLE THRESHOLD
Logic High Level VIN = 2.75 V to 20 V, VDD = 2.75 V to 5.5 V 235 285 330 mV
Enable Hysteresis VIN = 2.75 V to 20 V, VDD = 2.75 V to 5.5 V 35 mV
COMP VOLTAGE
COMP Clamp Low Voltage V
COMP Clamp High Voltage V
COMP Zero Current Threshold V
THERMAL SHUTDOWN T
COMP(LOW )
2.75 V ≤ VDD ≤ 5.5 V 2.55 V
COMP(H IGH)
2.75 V ≤ VDD ≤ 5.5 V 0.95 V
COMP_ZC T
TMSD
Thermal Shutdown Threshold Rising temperature 155 °C
Thermal Shutdown Hysteresis 15 °C
Hiccup Current Limit Timing 6 ms
1
The maximum specified values are with the closed loop measured at 10% to 90% time points (see and , C
MOSFETs specified as Infineon BSC042N030MSG.
2
Not automatic test equipment (ATE) tested.
= 1.5 A, 100 ns, positive pulse (0 V to 5 V) 2 3.5 Ω
SOURCE
= 1.5 A, 100 ns, negative pulse (5 V to 0 V) 0.8 2 Ω
SINK
= 1.5 A, 100 ns, positive pulse (0 V to 5 V) 1.7 3 Ω
SOURCE
= 1.5 A, 100 ns, negative pulse (5 V to 0 V) 0.75 2 Ω
SINK
= 5.0 V, CIN = 4.3 nF (see Figure 61) 18 ns
DD
= 5.0 V, CIN = 4.3 nF (see Figure 60) 16 ns
DD
= 10 mA 22 Ω
SINK
From disable state, release COMP/EN pin to enable
device; 2.75 V ≤ V
≤ 5.5 V
DD
Figure 60 Figure 61)
0.47 V
= 4.3 nF, and the upper-side and lower-si
GATE
de
Rev. 0 | Page 4 of 40
ADP1882/ADP1883
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
VDD to GND −0.3 V to +6 V
VIN to PGND −0.3 V to +28 V
FB, COMP/EN to GND −0.3 V to (VDD + 0.3 V)
DRVL to PGND −0.3 V to (VDD + 0.3 V)
SW to PGND −2.0 V to +28 V
BST to SW −0.8 V to (VDD + 0.3 V)
BST to PGND −0.3 V to 28 V
DRVH to SW −0.3 V to VDD
PGND to GND
θJA (10-Lead MSOP)
2-Layer Board 213.1°C/W
4-Layer Board 171.7°C/W
Operating Junction Temperature Range −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Soldering Conditions JEDEC J-STD-020
Maximum Soldering Lead Temperature
(10 sec)
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Absolute maximum ratings apply individually only, not in
combination. Unless otherwise specified, all other voltages are
referenced to PGND.
±0.3 V
300°C
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type θ
θJA (10-Lead MSOP)
2-Layer Board 213.1 °C/W
4-Layer Board 171.7 °C/W
1
θJA is specified for the worst-case conditions; that is, θJA is specified for device
soldered in a circuit board for surface-mount packages.
1
Unit
JA
BOUNDARY CONDITION
In determining the values given in Ta b le 2 and Tabl e 3, natural
convection was used to transfer heat to a 4-layer evaluation board.
ESD CAUTION
Rev. 0 | Page 5 of 40
ADP1882/ADP1883
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VIN
1
ADP1882/
FB
GND
VDD
2
ADP1883
3
TOP VIEW
4
(Not to S cale)
5
COMP/EN
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 VIN High Input Voltage. Connect VIN to the drain of the upper-side MOSFET.
2 COMP/EN Output of the Internal Error Amplifier/IC Enable. When this pin functions as EN, applying 0 V to this pin disables the IC.
3 FB Noninverting Input of the Internal Error Amplifier. This is the node where the feedback resistor is connected.
4 GND
Analog Ground Reference Pin of the IC. All sensitive analog components should be connected to this ground
plane (see the Layout Considerations section).
5 VDD
Bias Voltage Supply for the ADP1882/ADP1883 Controller, Including the Output Gate Drivers. A bypass capacitor
of 1 μF directly from this pin to PGND and a 0.1 μF across VDD and GND are recommended.
6 DRVL
Drive Output for the External Lower-Side N-Channel MOSFET. This pin also serves as the current-sense gain
setting pin (see Figure 69).
7 PGND Power GND. Ground for the lower-side gate driver and lower-side N-channel MOSFET.
8 DRVH Drive Output for the External Upper-Side, N-Channel MOSFET.
9 SW Switch Node Connection.
10 BST
Bootstrap for the Upper-Side MOSFET Gate Drive Circuitry. An internal boot rectifier (diode) is connected
between VDD and BST. A capacitor from BST to SW is required. An external Schottky diode can also be
connected between VDD and BST for increased gate drive capability.
BST
10
9
SW
8
DRVH
PGND
7
DRVL
6
08901-003
Rev. 0 | Page 6 of 40
ADP1882/ADP1883
TYPICAL PERFORMANCE CHARACTERISTICS
100
VDD = 5.5V, VIN = 5.5V (PSM)
95
V
= 5.5V, VIN = 13V (PSM )
DD
90
VDD = 5.5V, VIN = 5.5V
85
80
75
70
65
60
55
EFFICIENCY (%)
50
45
40
35
30
1001k10k100k
V
V
DD
VDD = 3.6V, VIN = 5.5V (PSM)
WURTH IND: 744355147, L = 0.47 µH, DCR: 0.80M
INFENION FETs: BSC042N03MS G ( UPPER/LOWER)
TA = 25°C
= 5.5V,
V
DD
V
= 13V
IN
(PSM)
= 5.5V, VIN = 16.5V ( PSM)
DD
= 3.6V, VIN = 16.5V (PSM)
VDD = 3.6V,
V
= 13V
IN
(PSM)
LOAD CURRENT (mA)
Figure 4. Efficiency—300 kHz, V
OUT
= 0.8 V
08901-004
100
95
VDD = 5.5V,
V
= 13V (PSM)
90
IN
85
80
75
70
65
60
55
50
EFFICIE NCY ( %)
45
40
35
VDD = 3.6V, VIN = 5.5V
30
25
20
15
100100k10k1k
Figure 7. Efficiency—600 kHz, V
VDD = 5.5V, VIN = 5.5V (PSM)
VDD = 5.5V, VIN = 13V
VDD = 5.5V, VIN = 16.5V
WURTH INDUCTOR: 744355072, L = 0.72µH, DCR: 1.65m
INFINEON FETS: BSC042N03MS G (UPPER/LOWER)
R
: 5.4m
ON
T
= 25°C
A
VDD = 5.5V, VIN = 5.5V
= 5.5V, VIN = 16.5V ( PSM)
V
DD
LOAD CURRENT (mA)
= 0.8 V
OUT
08901-007
100
95
VDD = 5.5V, VIN = 5.5V
VDD = 5.5V, VIN = 5.5V (PSM)
90
85
80
75
VDD = 5.5V,
V
= 13V
IN
VDD = 5.5V, VIN = 16.5V
VDD = 5.5V, VIN = 13V (PSM)
VDD = 5.5V, VIN = 16.5V (PSM)
70
65
VDD = 3.6V, VIN = 5.5V
60
55
EFFICIENCY (%)
50
45
40
35
30
25
1001k10k100k
WURTH INDUCTOR: 7443252100, L = 1.0µH, DCR: 3.3m
INFINEON M OSFETS: BSC042N03MS G (UPPER/ LOWER)
R
: 5.4m
ON
T
= 25°C
A
LOAD CURRENT (mA)
Figure 5. Efficiency—300 kHz, V
100
VDD = 5.5V, VIN = 16.5V (PSM)
95
OUT
= 1.8 V
90
85
VDD = 2.7V, VIN = 16.5V (PSM)
80
75
70
65
60
55
EFFICIENCY (%)
50
45
40
35
30
1001k10k100k
VDD = 2.7V, VIN = 13V
VDD = 5.5V, VIN = 13V
VDD = 3.6V, VIN = 13V
VDD = 5.5V, VIN = 16.5V
VDD = 3.6V, VIN = 16.5V
TA = 25°C
V
OUT
F
SW
WURTH INDUCTOR:
744355200, L = 2µH, DCR: 2.5m
INFINEON M OSFETS:
BSC042N03MS G (UPPER/LOWER)
= 1.8V
= 300kHz
LOAD CURRENT (mA)
Figure 6. Efficiency—300 kHz, V
OUT
= 7 V
100
VDD = 5.5V, VIN = 5.5V
95
90
85
80
75
70
65
60
55
EFFICIENCY (%)
50
45
40
35
30
25
1001k10k100k
8901-005
VDD = 5.5V, VIN = 13V
WURTH INDUCTOR: 744325072, L = 0.72µH, DCR: 1.65m
INFINEON FETS: BSC042N03MS G ( UPPER/LO W ER)
R
T
VDD = 5.5V, VIN = 16.5V (PSM)
VDD = 5.5V, VIN = 13V (PSM)
VDD = 5.5V, VIN = 16.5V
: 5.4m
ON
= 25°C
A
LOAD CURRENT (mA)
Figure 8. Efficiency—600 kHz, V
100
VDD = 5.5V/VIN = 13V (PSM)
VDD = 3.6V, VIN = 5.5V
VDD = 5.5V, VIN = 5.5V (PSM)
= 1.8 V
OUT
8901-008
95
90
VDD = 3.6V/VIN = 13V
85
80
VDD = 5.5V/VIN = 16.5V
75
= 5.5V/VIN = 13V
V
70
EFFICIENCY (%)
65
60
55
50
1001k10k100k
8901-006
DD
TA = 25°C
V
= 5V, VIN = 13V
OUT
F
= 600kHz
SW
WURTH INDUCT OR:
7443552100, L = 1.0µH, DCR: 3.3m
INFINEON MOSFETS:
BSC042N03MS G (UPPER/LOWER)
LOAD CURRENT (mA)
Figure 9. Efficiency—600 kHz, V
OUT
= 5 V
901-009
08
Rev. 0 | Page 7 of 40
ADP1882/ADP1883
T
100
VDD = 5.5V/VIN = 5.5V (PSM)
95
90
VDD = 3.6V/VIN = 3.6V
V
= 5.5V/VIN = 5.5V
DD
85
80
75
70
65
60
55
50
EFFICIENCY (%)
45
40
35
30
25
20
1001k10k100k
VDD = 5.5V/VIN = 16.5V
VDD = 5.5V/VIN = 13V
TA = 25°C
V
OUT
F
SW
WURTH INDUCTOR:
744303022, L = 0.22µH, DCR: 0.33m
INFINEON M OSFETS:
BSC042N03MS G ( UPPER/LOWER)
VDD = 3.6V/VIN = 13V
= 0.8V, VIN = 5.5V
= 1MHz
LOAD CURRENT (mA)
100
VDD = 5.5V/VIN = 5.5V (PSM)
95
90
Figure 10. Efficiency—1.0 MHz, V
VDD = 5.5V/VIN = 5.5V
= 0.8 V
OUT
VDD = 5.5V/VIN = 13V
85
80
75
70
65
60
VDD = 3.6V/VIN = 13V
VDD = 3.6V/VIN = 16.5V
VDD = 5.5V/VIN = 16.5V
55
50
EFFICIENCY (%)
45
40
35
30
25
20
100
1k10k100k
TA = 25°C
V
= 1.8V, VIN = 5.5V
OUT
F
= 1MHz
SW
WURTH INDUCTOR:
744303022, L = 0.22µH, DCR: 0.33m
INFINEON M OSFETS:
BSC042N03MS G (UPPER/LOWER)
LOAD CURRENT (mA)
Figure 11. Efficiency—1.0 MHz, V
OUT
= 1.8 V
100
95
VDD = 5.5V/VIN = 16.5V (PSM)
90
85
80
75
70
65
60
55
EFFICIENCY (%)
50
45
40
35
30
1001k10k
VDD = 5.5V/VIN = 16.5V
VDD = 5.5V/VIN = 13V
= 25°C
T
A
V
= 4V, VIN = 16.5V
OUT
F
= 1MHz
SW
WURTH INDUCTOR:
744318180, L = 1.4µH, DCR: 3.2m
INFINEON M OSFETS:
BSC042N03MS G ( UPPER/LOWER)