Wide input voltage range: 3.15 V to 14 V
Wide output voltage range: 0.8 V to input voltage
Pin-to-pin compatible with LTC1772, LTC3801
Up to 94% efficiency
0.8 V ± 1.25% reference accuracy over temperature
Internal soft start
100% duty cycle for low dropout voltage
Current-mode operation for good line and load
transient response
7 μA shutdown supply current
235 μA quiescent supply current
Short-circuit and overvoltage protection
Small 6-lead TSOT package
APPLICATIONS
Wireless devices
1- to 3-cell Li-Ion battery-powered applications
Set-top boxes
Processor core power supplies
Hard disk drives
Step-Down DC-to-DC Controller in TSOT
ADP1864
GENERAL DESCRIPTION
The ADP1864 is a compact, inexpensive, constant-frequency,
current-mode, step-down dc-to-dc controller. The ADP1864
drives a P-channel MOSFET that regulates an output voltage as
low as 0.8 V with ±1.25% accuracy, for up to 5 A load currents,
from input voltages as high as 14 V.
The ADP1864 provides system flexibility by allowing accurate
setting of the current limit with an external resistor, and the
output voltage is easily adjustable using two external resistors.
The ADP1864 includes an internal soft start to allow quick
power-up while preventing input inrush current. Additional
safety features include short-circuit protection, output overvoltage
protection, and input undervoltage protection. Current-mode
control provides fast and stable load transient performance,
while the 580 kHz operating frequency allows a small inductor
to be used in the system. To further the life of a battery source,
the controller turns on the external P-channel MOSFET 100%
of the duty cycle during dropout.
The ADP1864 operates over the −40°C to +125°C temperature
range and is available in a small, low profile, 6-lead TSOT package.
TYPICAL APPLICATIONS DIAGRAM
25kΩ
470pF
68pF
80.6kΩ
174kΩ
1
2
3
COMP
ADP1864
GND
FB
PGATE
CS
6
5
IN
4
Figure 1.
0.03Ω
= 3.15V TO 14V
V
IN
10µF
5µH
2.5V, 2.0A
47µF
05562-001
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
FB Regulation Voltage VIN = 3.15 V to 14 V, TJ = −40°C to +125°C 0.790 0.8 0.810 V
Overvoltage Protection Threshold V
Measured at FB, TJ = −40°C to +125°C 0.87 0.885 0.9 V
OVP
Overvoltage Protection Hysteresis 50 mV
CURRENT SENSE
Peak Current Sense Voltage TJ = −40°C to +125°C 90 125 mV
V
Current Sense Gain VCS to V
OUTPUT REGULATION
Line Regulation
Load Regulation
1
V
2
V
OSCILLATOR
Oscillator Frequency VFB = 0.8 V, TJ = −40°C to +125°C 500 580 650 kHz
V
FB Frequency Foldback Threshold 0.35 V
GATE DRIVE
Gate Rise Time C
Gate Fall Time C
Minimum On Time PGATE minimum low duration 190 ns
SOFT START POWER-ON TIME 1.1 ms
1
Line regulation is measured using the application circuit in . Line regulation is specified as the change in the FB voltage resulting from a 1 V change in
the IN voltage.
2
Load regulation is measured using the application circuit in . Load regulation is specified as the change in the FB voltage resulting from a 1 V change in the
COMP voltage. The COMP voltage range is typically 0.9 V to 2.3 V for the minimum to maximum load current condition.
= 3.15 V to 14 V, PGATE = IN 235 360 μA
IN
= 3.15 V to 14 V, COMP = GND 7 15 μA
IN
falling, TJ = −40°C to +125°C 2.75 2.90 3.01 V
IN
rising, TJ = −40°C to +125°C 2.85 3.00 3.15 V
IN
= 0.8 V, TJ = 25°C −20 −2 +20 nA
FB
= 0.8 V, TJ = −40°C to +125°C −40 −2 +40 nA
FB
= ±5 μA 0.24 mmho
COMP
= 3.15 V to 14 V, TJ = −40°C to +125°C 70 125 mV
IN
12 V/V
COMP
= 3.15 V to 14 V, VFB/VIN 0.12 mV/V
IN
−2 mV/V
FB/VCOMP
= 0 V 190 kHz
FB
= 3 nF 50 ns
GATE
= 3 nF 40 ns
GATE
Figure 1
Figure 1
Rev. B | Page 3 of 16
ADP1864
www.BDTIC.com/ADI
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
IN to GND −0.3 V to +16 V
CS, PGATE to GND −0.3 V to (VIN + 0.3 V)
FB, COMP to GND −0.3 V to +6 V
θJA 2-Layer (SEMI Standard Board) 315°C/W
θJA 4-Layer (JEDEC Standard Board) 186°C/W
Operating Junction Temperature Range −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Lead Temperature
Rework Temperature (J-STD-020B) 260°C
Peak Reflow Temperature,
(20 sec to 40 sec, J-STD-020B)
260°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. B | Page 4 of 16
ADP1864
www.BDTIC.com/ADI
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PGATE
6
5
IN
4
CS
05562-003
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1 COMP
Regulator Compensation Node. COMP is the output of the internal transconductance error amplifier. Connect a
series RC from COMP to GND to compensate for the control loop. Add an extra high frequency capacitor between
COMP and GND to further reduce switching jitter. The value of this is typically one-tenth of the main compensation
capacitor. Pulling the COMP pin below 0.3 V disables the ADP1864 and turns off the external PFET.
2 GND
Analog Ground. Directly connect the compensation and feedback networks to GND, preferably with a small analog
GND plane. Connect GND to the power ground (PGND) plane with a narrow track at a single point close to the GND
pin. See the Layout Considerations section for more information.
3 FB
Feedback Input. Connect a resistive voltage divider from the output voltage to FB to set the output voltage. The
regulation feedback voltage is 0.8 V. Place the feedback resistors as close as possible to the FB pin.
4 CS
Current Sense Input. CS is the negative input of the current sense amplifier. It provides the current feedback signal
used to terminate the PWM on time. Place a current sense resistor between IN and CS to set the current limit. The
current limit threshold is typically 125 mV.
5 IN
Power Input. IN is the power supply to the ADP1864 and the positive input of the current sense amplifier. Connect
IN to the positive side of the input voltage source. Bypass IN to PGND with a 10 μF or larger capacitor as close as possible
to the ADP1864. For additional high frequency noise reduction, add a 0.1 μF capacitor to PGND at the IN pin.
6 PGATE
Gate Drive Output. PGATE drives the gate of the external P-channel MOSFET. Connect PGATE to the gate of the
external MOSFET.
COMP
1
ADP1864
2
GND
TOP VIEW
(Not to Scale)
3
FB
Figure 2. Pin Configuration
Rev. B | Page 5 of 16
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