ANALOG DEVICES ADP1850 Service Manual

Wide Range Input, Dual/Two-Phase, DC-to-DC

V

Data Sheet

FEATURES

Wide range input: 2.75 V to 20 V
Power stage input voltage: 1 V to 20 V
Output voltage range: 0.6 V up to 90% V
Output current to more than 25 A per channel
Accurate current sharing between channels (interleaved)
Programmable frequency: 200 kHz to 1.5 MHz
180° phase shift between channels for reduced input

capacitance

±0.85% reference voltage accuracy from −40°C to +85°C
Integrated boost diodes
Power saving mode (PSM) at light loads
Accurate power good with internal pull-up resistor
Accurate voltage tracking capability
Independent channel precision enable
Overvoltage and overcurrent limit protection
Externally programmable soft start, slope compensation and

current sense gain
Synchronization input
Thermal overload protection
Input undervoltage lockout (UVLO)
Available in 32-lead 5 mm × 5 mm LFCSP

APPLICATIONS

High current single and dual output intermediate bus and

point of load converters requiring sequencing and

tracking capability, including converters for:

Point-of-load power supplies
Telecom base station and networking
Consumer
Industrial and instrumentation
Healthcare and medical

GENERAL DESCRIPTION

The ADP1850 is a configurable dual output or two-phase, single
output dc-to-dc synchronous buck controller capable of running
from commonly used 3.3 V to 12 V (up to 20 V) voltage inputs.
The device operates in current mode for improved transient
response and uses valley current sensing for enhanced noise
immunity.

The architecture enables accurate current sharing between
interleaved phases for high current outputs.

The ADP1850 is ideal in system applications requiring multiple
output voltages: the ADP1850 includes a synchronization fea­ture to eliminate beat frequencies between switching devices;
provides accurate tracking capability between supplies and
includes precision enable for simple, robust sequencing.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

IN

Synchronous Buck Controller

ADP1850

TYPICAL OPERATION CIRCUIT

R

RAMP2

R

R

CSG1

CSG2

IN

M1

L1

R11

M2

R12

V

IN

M3

L2

R21

M4

R22

R

RAMP1

RAMP1

VIN

ADP1850

EN1
EN2
VDL

VCCO
TRK1
TRK2

PGOOD1
PGOOD2

HI

LO

SYNC

FREQ

COMP1

COMP2

SS1
SS2

AGND

DH1

BST1

SW1

ILIM1

FB1

DL1

PGND1

RAMP2

DH2

BST2

SW2

ILIM2

FB2

DL2

PGND2

Figure 1. Single Phase Circuit

The ADP1850 provides high speed, high peak current drive
capability with dead-time optimization to enable energy
efficient power conversion. For low load operation, the device
can be configured to operate in power saving mode (PSM) by
skipping pulses and reducing switching losses to improve the
energy efficiency at light load and standby conditions.

The accurate current limit (±6%) allows the power architect to
design within a narrower range of tolerances and can reduce
overall converter size and cost.

The ADP1850 provides a configurable architecture capable
of wide range input operation to provide the designer with
maximum re-use opportunities and improved time to market.
Additional flexibility is provided by external programmability
of loop compensation, soft start, frequency setting, power
saving mode, current limit and current sense gain can all be
programmed using external components.

The ADP1850 includes a high level of integration in a small size
package. The start-up linear regulator and the boot-strap diode
for the high side drive are included. Protection features include:
undervoltage lock-out, overvoltage, overcurrent/short-circuit
and over temperature. The ADP1850 is available in a compact
32-lead LFCSP 5 mm × 5 mm thermally enhanced package.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2010-2012 Analog Devices, Inc. All rights reserved.

V

V

OUT1

OUT2

09440-001

ADP1850 Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

General Description ......................................................................... 1

Typical Operation Circuit ................................................................ 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Absolute Maximum Ratings ............................................................ 5

ESD Caution .................................................................................. 5

Simplified Block Diagram ............................................................... 6

Pin Configuration and Function Descriptions ............................. 7

Typical Performance Characteristics ............................................. 9

Theory of Operation ...................................................................... 12

Control Architecture .................................................................. 12

Oscillator Fre quency .................................................................. 12

Modes of Operation ................................................................... 13

Synchronization .......................................................................... 13

Synchronous Rectifier and Dead Time ................................... 14

Input Undervoltage Lockout ..................................................... 14

Internal Linear Regulator .......................................................... 14

Overvoltage Protection .............................................................. 14

Power Good ................................................................................. 14

Short-Circuit and Current-Limit Protection .......................... 15

Shutdown Control ...................................................................... 15

Thermal Overload Protection ................................................... 15

Applications Information .............................................................. 16

Setting the Output Voltage ........................................................ 16

Soft Start ...................................................................................... 16

Setting the Current Limit .......................................................... 16

Accurate Current-Limit Sensing .............................................. 17

Setting the Slope Compensation .............................................. 17

Setting the Current Sense Gain ................................................ 17

Input Capacitor Selection .......................................................... 18

Input Filter ................................................................................... 18

Boost Capacitor Selection ......................................................... 18

Inductor Selection ...................................................................... 18

Output Capacitor Selection ....................................................... 19

MOSFET Selection ..................................................................... 19

Loop Compensation (Single Phase Operation) ..................... 21

Configuration and Loop Compensation (Dual-Phase

Operation) ................................................................................... 22

Switching Noise and Overshoot Reduction ............................ 22

Voltage Tracking ......................................................................... 23

Indepdendent Power Stage Input Voltage ............................... 24

PCB Layout Guidelines .................................................................. 25

MOSFETs, Input Bulk Capacitor, and Bypass Capacitor ...... 25

High Current and Current Sense Paths ................................... 25

Signal Paths ................................................................................. 25

PGND Plane ................................................................................ 25

Feedback and Current-Limit Sense Paths ............................... 25

Switch Node ................................................................................ 26

Gate Driver Paths ....................................................................... 26

Output Capacitors ...................................................................... 26

Typical Operating Circuits ............................................................ 27

Outline Dimensions ....................................................................... 31

Ordering Guide .......................................................................... 31



REVISION HISTORY

4/12—Rev. 0 to Rev. A

Changes to Setting the Current Sense Gain Section .................. 17

Updated Outline Dimensions ....................................................... 31

11/10—Revision 0: Initial Version

Rev. A | Page 2 of 32

Data Sheet ADP1850

SPECIFICATIONS

All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). VIN = 12 V. The
specifications are valid for T

Table 1.

Parameter Symbol Conditions Min Typ Max Unit

POWER SUPPLY

Input Voltage VIN 2.75 20 V

Undervoltage Lockout Threshold IN

V

Undervoltage Lockout Hysteresis 0.1 V

Quiescent Current IIN

EN1 = EN2 = VIN = 12 V, VFB = V

Shutdown Current I

ERROR AMPLIFIER

FBx Input Bias Current IFB −100 +1 +100 nA

Transconductance Gm Sink or source 1 µA 385 550 715 µS

TRK1, TRK2 Input Bias Current I

CURRENT SENSE AMPLIFIER GAIN ACS

Default setting, R

OUTPUT CHARACTERICTISTICS

Feedback Accuracy Voltage VFB

Line Regulation of PWM ∆VFB/∆VIN ±0.015 %/V

Load Regulation of PWM ∆VFB/∆V

OSCILLATOR

Frequency fSW R

R

R

FREQ to AGND 235 300 345 kHz

FREQ to VCCO 475 600 690 kHz

SYNC Input Frequency Range f

SYNC Input Pulse Width t

SYNC Pin Capacitance to GND C

LINEAR REGULATOR

VCCO Output Voltage I

VCCO Load Regulation I

VCCO Line Regulation VIN = 5.5 V to 20 V, I

VCCO Current Limit1 VCCO drops to 4 V from 5 V 350 mA

VCCO Short-Circuit Current1 VCCO < 0.5 V 370 400 mA

VIN to VCCO Dropout Voltage2 V

LOGIC INPUTS

EN1, EN2 EN1/EN2 rising 0.57 0.63 0.68 V

EN1, EN2 Hysteresis 0.03 V

EN1, EN2 Input Leakage Current IEN V

SYNC Logic Input Low 1.3 V

SYNC Logic Input High 1.9 V

SYNC Input Pull-Down Resistance R

= −40°C to +125°C, unless otherwise specified. Typical values are at TA = 25°C.

J

V

UVLO

rising 2.45 2.6 2.75 V

IN

falling 2.4 2.5 2.6

IN

EN1 = EN2 = V

= 12 V, VFB = V

IN

in PWM mode

CCO

4.5 5.8

(no switching)

in PSM mode 2.8

CCO

EN1 = EN2 = GND, VIN = 5.5 V or 20 V 100 200

IN_SD

0 V ≤ V

TRK

TRK1/VTRK2

Gain resistor connected to DLx,

= 47 kΩ ± 5%

R

CSG

Gain resistor connected to DLx,

= 22 kΩ ± 5%

R

CSG

Gain resistor connected to DLx,

= 100 kΩ ± 5%

R

CSG

= −40°C to +85°C, VFB = 0.6 V

T

J

= −40°C to +125°C, VFB = 0.6 V

T

J

V

COMP

f

SYNC

100 ns

SYNCMIN

5 pF

SYNC

I

DROPOUT

1 MΩ

SYNC

range = 0.9 V to 2.2 V ±0.3 %

COMP

= 340 kΩ to AGND 170 200 235 kHz

FREQ

= 78.7 kΩ to AGND 720 800 880 kHz

FREQ

= 39.2 kΩ to AGND 1275 1500 1725 kHz

FREQ

= 2 × fSW 400 3000 kHz

SYNC

= 100 mA 4.7 5.0 5.3 V

VCCO

= 0 mA to 100 mA, 35 mV

VCCO

= 100 mA, VIN ≤ 5 V 0.33 V

VCCO

= 2.75 V to 20 V 1 200 nA

IN

≤ 5 V −100 +1 +100 nA

2.4 3 3.6 V/V

5.2 6 6.9 V/V

= open 10.5 12 13.5 V/V

CSG

20.5 24 26.5 V/V

−0.85% +0.6 +0.85% V

−1.5% +0.6 +1.5% V

= 20 mA 10 mV

VCCO

Rev. A | Page 3 of 32

mA

mA
µA

ADP1850 Data Sheet

Parameter Symbol Conditions Min Typ Max Unit

GATE DRIVERS

DHx Rise Time CDH = 3 nF, V
DHx Fall Time CDH = 3 nF, V
DLx Rise Time CDL = 3 nF 16 ns
DLx Fall Time CDL = 3 nF 14 ns
DHx to DLx Dead Time External 3 nF is connected to DHx and DLx 25 ns
DHx or DLx Driver RON, Sourcing

Current

1

R

Sourcing 2 A with a 100 ns pulse 2 Ω

ON_SOURCE

Sourcing 1 A with a 100 ns pulse, VIN = 3 V 2.3 Ω
DHx or DLx Driver RON, Tempco TC
DHx or DLx Driver RON, Sinking

Current

1

V

RON

R

Sinking 2 A with a 100 ns pulse 1.5 Ω

ON_SINK

= 3 V or 12 V 0.3 %/oC

IN

Sinking 1 A with a 100 ns pulse, VIN = 3 V 2 Ω

DHx Maximum Duty Cycle fSW = 300 kHz 90 %
DHx Maximum Duty Cycle fSW = 1500 kHz 50 %
Minimum DHx On Time fSW = 200 kHz to 1500 kHz 135 ns
Minimum DHx Off Time fSW = 200 kHz to 1500 kHz 335 ns
Minimum DLx On Time fSW = 200 kHz to 1500 kHz 285 ns

COMPx VOLTAGE RANGE

COMPx Pulse Skip Threshold V
COMPx Clamp High Voltage V

In pulse skip mode 0.9 V

COMP,THRES

2.25 V

COMP,HIGH

THERMAL SHUTDOWN

Thermal Shutdown Threshold T

155

TMSD

Thermal Shutdown Hysteresis 20

OVERVOLTAGE AND POWER GOOD

THRESHOLDS
FBx Overvoltage Threshold VOV V

rising 0.635 0.65 0.665 V

FB

FBx Overvoltage Hysteresis 30 mV
FBx Undervoltage Threshold VUV V

falling 0.525 0.55 0.578 V

FB

FBx Undervoltage Hysteresis 30 mV
TRKx INPUT VOLTAGE RANGE 0 5 V
FBx TO TRKx OFFSET VOLTAGE TRKx = 0.1 V to 0.57 V, offset = VFB − V
SOFT START

SSx Output Current ISS During start-up 4.6 6.5 8.4 µA

SSx Pull-Down Resistor During a fault condition 3 kΩ

FBx to SSx Offset VSS = 0.1 V to 0.6 V, offset = VFB − VSS −10 +10 mV
PGOODx

PGOODx Pull-up Resistor R

Internal pull-up resistor to VCCO 12.5 kΩ

PGOOD

PGOODx Delay 12 µs

Over Voltage or Under Voltage

This is the minimum duration required to trip

the PGOOD signal
Minimum Duration
ILIM1, ILIM2 Threshold Voltage1 Relative to PGNDx −5 0 +5 mV
ILIM1, ILIM2 Output Current ILIMx = PGNDx 47 50 53 µA
Current Sense Blanking Period

After DLx goes high, current limit is not sensed

during this period

INTEGRATED RECTIFIER

At 20 mA forward current 16 Ω

(BOOST DIODE) RESISTANCE

ZERO CURRENT CROSS OFFSET

(SWx TO PGNDx)

1

Guaranteed by design.

2

Connect VIN to VCCO when 2.75 V < VIN < 5.5 V.

1

In pulse skip mode only, f

− VSW = 5 V 16 ns

BST

− VSW = 5 V 14 ns

BST

−10 0 +10 mV

TRK

10 µs

100 ns

= 600 kHz 0 2 4 mV

SW

°C
°C

Rev. A | Page 4 of 32

Data Sheet ADP1850

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

VIN, EN1/EN2, RAMP1/RAMP2 21 V
FB1/FB2, COMP1/COMP2, SS1/SS2, TRK1/TRK2,

FREQ, SYNC, VCCO, VDL, PGOOD1/PGOOD2
ILIM1/ILIM2, SW1/SW2 to PGND1/PGND2 −0.3 V to +21 V
BST1/BST2, DH1/DH2 to PGND1/PGND2 −0.3 V to +28 V
DL1/DL2 to PGND1/PGND2 −0.3V to VCCO + 0.3 V
BST1/BST2 to SW1/SW2 −0.3 V to +6 V
BST1/BST2 to PGND1/PGND2

20 ns Transients
SW1/SW2 to PGND1/PGND2

20 ns Transients
DL1/DL2, SW1/SW2, ILIM1/ILIM2 to

PGND1/PGND2
20 ns Negative Transients

PGND1/PGND2 to AGND −0.3 V to +0.3 V
PGND1/PGND2 to AGND 20 ns Transients −8 V to +4 V

θJA on Multilayer PCB (Natural Convection)

Operating Junction Temperature Range3 −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Maximum Soldering Lead Temperature 260°C

1

Measured with exposed pad attached to PCB.

2

Junction-to-ambient thermal resistance (θJA) of the package was calculated
or simulated on multilayer PCB.

3

The junction temperature, TJ, of the device is dependent on the ambient
temperature, TA, the power dissipation of the device, PD, and the junction-to­ambient thermal resistance of the package, θJA. Maximum junction
temperature is calculated from the ambient temperature and power
dissipation using the formula: TJ = TA + PD × θJA.

1, 2

−0.3 V to +6 V

32 V

25 V

−8 V

32.6°C/W

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Absolute maximum ratings apply individually only, not in
combination. Unless otherwise specified, all other voltages are
referenced to GND.

ESD CAUTION

Rev. A | Page 5 of 32

ADP1850 Data Sheet

V

V

SIMPLIFIED BLOCK DIAGRAM

IN

CCO

THERMAL

SHUTDOWN

LDO

REF

OV

0.6V
UV

EN1

EN2

SYNC

FREQ

COMP1

FB1

TRK1

SS1

RAMP1

0.6V

1MΩ

1kΩ

+

–

+

–

ERROR
AMPLIFIER

–
+

G

m

+
+

V

=

0

.

6

V

R

F

E

6.5µA

LOGIC

FAULT

EN1

SLOPE COMP AND
RAMP GENERATOR

OSCILLAT OR

5V

OV1

OVER_LIM1

OVER_LIM1

UVLO

LOGIC

0.9V

COMPARATOR

CURRENT

CONTROL

PH1

PH2

0.6V

–

+

–

+

PWM

LIMIT

EN1_SW
EN2_SW

DUPLICATE FOR

CHANNEL 2

OV

FB1

UV

SYNC

EN1_SW

OVER_LIM1

OV1

PULSE SKIP

AV = 3, 6, 12, 24

+

–

+

–

DRIVER LOG IC
CONTROL AND

MACHINE

DCM

ZERO CROSS

DETECT

CS GAIN

–

+

+

–

OV1

UV1

VDL

STATE

+

–

CURRENT SENSE
AMPLIFIER

AGND

VCCO

LOGIC

12kΩ

PGOOD1

BST1

DH1

SW1

VDL

DL1

PGND1

VCCO

50µA

ILIM1

9440-003

Figure 2.

Rev. A | Page 6 of 32

Data Sheet ADP1850

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TRK1

FB1

COMP1

RAMP1

SS1

PGOOD1

ILIM1

SS2

BST1

25

24

SW1

23

DH1
PGND1

22

DL1

21
20

DL2

19

PGND2

18

DH2

17 SW2

ILIM2

BST2

PGOOD2

09440-004

32313029282726

1

EN1

2

SYNC

VIN

3
4
5
6
7
8

ADP1850

TOP VIEW

(Not to Scale)

9

10111213141516

FB2

TRK2

RAMP2

COMP2

VCCO

VDL

AGND

FREQ

EN2

NOTES

1. CONNECT THE BOTTOM EXPOSED PAD OF THE
LFCSP PACKAGE TO SYST EM AGND PLANE .

Figure 3. Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

1 EN1

Enable Input for Channel 1. Drive EN1 high to turn on the Channel 1 controller, and drive EN1 low to turn off the
Channel 1 controller. Tie EN1 to VIN for automatic startup. For a precision UVLO, put an appropriately sized
resistor divider from VIN to AGND and tie the midpoint to this pin.

2 SYNC

Frequency Synchronization Input. Accepts an external signal between 1× and 2.3× of the internal oscillator
frequency, f

, set by the FREQ pin. The controller operates in forced PWM when a signal is detected at SYNC or

SW

when SYNC is high. The resulting switching frequency is ½ of the SYNC frequency. When SYNC is low or left
floating, the controller operates in pulse skip mode. For dual-phase operation, connect SYNC to a logic high or an
external clock.

3 VIN

Connect to Main Power Supply. Bypass with a 1 µF or larger ceramic capacitor connected as close to this pin as
possible and PGNDx.

4 VCCO

Output of the Internal Low Dropout Regulator (LDO). Bypass VCCO to AGND with a 1 F or larger ceramic
capacitor. The VCCO output remains active even when EN1 and EN2 are low. For operation with VIN below 5 V,
VIN may be shorted to VCCO. Do not use the LDO to power other auxiliary system loads.

5 VDL

Power Supply for the Low-Side Driver. Bypass VDL to PGNDx with a 1 µF or greater ceramic capacitor. Connect

VCCO to VDL.
6 AGND Analog Ground.
7 FREQ

Sets the desired operating frequency between 200 kHz and 1.5 MHz with one resistor between FREQ and AGND.

Connect FREQ to AGND for a preprogrammed 300 kHz or FREQ to VCCO for 600 kHz operating frequency.
8 EN2

Enable Input for Channel 2. Drive EN2 high to turn on the Channel 2 controller, and drive EN2 low to turn off the

Channel 2 controller. Tie EN2 to VIN for automatic startup. For a precision UVLO, put an appropriately sized

resistor divider from VIN to AGND, and tie the midpoint to this pin.
9 TRK2 Tracking Input for Channel 2. Connect TRK2 to VCCO if tracking is not used.
10 FB2 Output Voltage Feedback for Channel 2. Connect to Output 2 via a resistor divider.
11 COMP2

Compensation Node for Channel 2. Output of Channel 2 error amplifier. Connect a series resistor-capacitor

network from COMP2 to AGND to compensate the regulation control loop.
12 RAMP2

Connect a resistor from RAMP2 to VIN to set up a ramp current for slope compensation in Channel 2. The voltage

at RAMP2 is 0.2 V. This pin is high impedance when the channel is disabled.
13 SS2

Soft Start Input for Channel 2. Connect a capacitor from SS2 to AGND to set the soft start period. The node is

internally pulled up to 5 V with a 6.5 µA current source.
14 PGOOD2

Power Good. Open-drain power-good indicator logic output with an internal 12 kΩ resistor connected between

PGOOD2 and VCCO. PGOOD2 is pulled to ground when the Channel 2 output is outside the regulation window.

An external pull-up resistor is not required.

Rev. A | Page 7 of 32

ADP1850 Data Sheet

Pin No. Mnemonic Description

15 ILIM2

16 BST2

17 SW2

18 DH2

19 PGND2

20 DL2

21 DL1

22 PGND1

23 DH1

24 SW1

25 BST1

26 ILIM1

27 PGOOD1

28 SS1

29 RAMP1

30 COMP1

31 FB1 Output Voltage Feedback for Channel 1. Connect to Output 1 via a resistor divider.
32 TRK1 Tracking Input for Channel 1. Connect TRK1 to VCCO if tracking is not used.
33

(EPAD)

Exposed Pad
(EPAD)

Current Limit Sense Comparator Inverting Input for Channel 2. Connect a resistor between ILIM2 and SW2 to set
the current limit offset. For accurate current limit sensing, connect ILIM2 to a current sense resistor at the source
of the low-side MOSFET.

Boot-Strapped Upper Rail of High Side Internal Driver for Channel 2. Connect a multilayer ceramic capacitor
(0.1 µF to 0.22 µF) between BST2 and SW2. There is an internal boost rectifier connected between VDL and BST2.

Switch Node for Channel 2. Connect to source of the high-side N-channel MOSFET and the drain of the low-side
N-channel MOSFET of Channel 2.

High-Side Switch Gate Driver Output for Channel 2. Capable of driving MOSFETs with total input capacitance up
to 20 nF.

Power Ground for Channel 2. Ground for internal Channel 2 driver. Differential current is sensed between SW2
and PGND2. Use the Kelvin sensing connection technique between PGND2 and source of the low-side MOSFET.

Low-Side Synchronous Rectifier Gate Driver Output for Channel 2. To set the gain of the current sense amplifier,
connect a resistor between DL2 and PGND2. Capable of driving MOSFETs with a total input capacitance up to 20 nF.

Low-Side Synchronous Rectifier Gate Driver Output for Channel 1. To set the gain of the current sense amplifier,
connect a resistor between DL1 and PGND1. Capable of driving MOSFETs with a total input capacitance up to 20 nF.

Power Ground for Channel 1. Ground for internal Channel 1 driver. Differential current is sensed between SW1
and PGND1. Use the Kelvin sensing connection technique between PGND1 and source of the low-side MOSFET.

High-Side Switch Gate Driver Output for Channel 1. Capable of driving MOSFETs with a total input capacitance
up to 20 nF.

Power Switch Node for Channel 1. Connect to source of the high-side N-channel MOSFET and the drain of the
low-side N-channel MOSFET of Channel 1.

Boot-Strapped Upper Rail of High Side Internal Driver for Channel 1. Connect a multilayer ceramic capacitor
(0.1 µF to 0.22 µF) between BST1 and SW1. There is an internal boost diode or rectifier connected between VDL
and BST1.

Current Limit Sense Comparator Inverting Input for Channel 1. Connect a resistor between ILIM1 and SW1 to set
the current limit offset. For accurate current limit sensing, connect ILIM1 to a current sense resistor at the source
of the low-side MOSFET.

Power Good. Open-drain power-good indicator logic output with an internal 12 kΩ resistor connected between
PGOOD1 and VCCO. PGOOD1 is pulled to ground when the Channel 1 output is outside the regulation window.
An external pull-up resistor is not required.

Soft Start Input for Channel 1. Connect a capacitor from SS1 to AGND to set the soft start period. This node is
internally pulled up to 5 V with a 6.5 µA current source.

Connect a resistor from RAMP1 to VIN to set up a ramp current for slope compensation in Channel 1. The voltage
at RAMP2 is 0.2 V. This pin is high impedance when the channel is disabled.

Compensation Node for Channel 1. Output of Channel 1 error amplifier. Connect a series resistor-capacitor
network from COMP1 to AGND to compensate the regulation control loop.

Connect the bottom exposed pad of the LFCSP package to the system AGND plane.

Rev. A | Page 8 of 32

Data Sheet ADP1850

TYPICAL PERFORMANCE CHARACTERISTICS

100

90

VO = 3.3V, PSM

80

70

60

50

= 1.8V, PSM

V

O

40

EFFICIENCY (%)

30

20

10

0

0.01 0.1 1 10 100

V

V

O

= 1.8V, PWM

O

LOAD (A)

= 3.3V, PWM

V

= 12V, 600kHz

IN

Figure 4. Efficiency Plot of Figure 44

100

90

80

VO = 5V, PSM

70

60

50

40

VO = 5V, PWM

EFFICIENCY (%)

30

20

10

0

0.01 0. 1 1 10

VO = 1.8V, PW M

LOAD (A)

VO = 1.8V, P SM

V

= 12V, 750kHz

IN

Figure 5. Efficiency Plot of Figure 45

0

09440-005

09440-006

5.10

5.05

5.00

4.95

4.90

4.85

VCCO (V)

4.80

4.75

4.70

4.65
5 7 9 11131517

NO LOAD O N LDO

100mA LOAD ON LDO

VIN (V)

Figure 7. LDO Line Regulation

6

5

4

3

VCCO (V)

2

1

0

0123456

VIN (V)

Figure 8. VCCO vs. V

IN

09440-008

09440-009

–0.05

–0.10

∆VCCO (V)

–0.15

–0.20

–0.25

50mA LOAD

100mA LOAD

2.5 3.0 3. 5 4. 0 4.5 5.0

VIN (V)

Figure 6. LDO Load Regulation

09440-007

Rev. A | Page 9 of 32

1

2

3

CH1 10V
CH3 5V

SW1

SW2

SYNC 600kHz

CH2 10V M1µs A CH1 5.60V

Figure 9. An Example of Synchronization, f

= 600 kHz

SYNC

09440-010

ADP1850 Data Sheet

OUTPUT RESPONSE

1

8A TO 13A STEP LOAD

4

VIN = 12V
V

= 3.3V

OUT

CH1 20mV

B

W

CH4 5A Ω

M200µs A CH4 11.5A

Figure 10. Step Load Transient of Figure 44

= 1.8V

DH1

DL1

IL1

CH2 5VCH1 5V

CH4 1A Ω

M1ms A CH1 2.4V

1

2

VOUT1

3

4

VIN = 12V
V

OUT

OUTPUT PRECHARGED TO 1V

CH3 1V

Figure 11. Soft Start into Precharged Output

SW1

1

PGOOD1

VCCO (CH3)

2

V

, PRELOADED (CH4)

CH2 2VCH1 10V

CH4 2V Ω

OUT

M10ms A CH2 3.76V

09440-014

3

4

09440-011

CH3 2V

Figure 13. Thermal Shutdown Waveform

0.5

0

–0.5

(%)

SW

f

–1.0

–1.5

CHANGE IN

–2.0

–2.5

09440-012

3 5 7 9 11 13 15 17 19 21

Figure 14. Change in f

REFERENCED AT VIN = 2.75V

600kHz

300kHz

850kHz

VIN (V)

vs. VIN

SW

09440-015

1

3
2
4

SW

EN

CH3 1V

V

(CH3)

OUT

SS (CH4)

CSS = 100nF

CH2 2VCH1 10V

CH4 1V

M10ms A CH2 1.52V

Figure 12. Enable Start-Up Function

09440-013

Rev. A | Page 10 of 32

2.0

1.5

1.0

0.5

(%)

SW

f

0

–0.5

–1.0

CHANGE IN

–1.5

–2.0

–2.5

–40 –15 10 35 60 85 110 135

Figure 15. f

VIN = 12V; REFERENCED AT 25° C

TEMPERATURE (° C)

vs. Temperature

SW

09440-016