ANALOG DEVICES ADP1823 Service Manual

Dual, Interleaved, Step-Down

www.BDTIC.com/ADI

FEATURES

Fixed-frequency operation: 300 kHz, 600 kHz, or

synchronized operation up to 1 MHz
Supply input range: 3.7 V to 20 V
Wide power stage input range: 1 V to 24 V
Interleaved operation results in smaller, low cost input

ca

pacitor

All-N-channel MOSFET design for low cost
±0.85% accuracy at 0°C t
Soft start, thermal overload, current-limit protection
10 μA shutdown supply current
Internal linear regulator
Lossless R

current-limit sensing

DSON

Reverse current protection during soft start for handling

pr

echarged outputs
Independent Power OK (POK) outputs
Voltage tracking for sequencing or DDR termination
Available in 5 mm × 5 mm, 32-lead LFCSP

APPLICATIONS

Telecommunications and networking systems
Medical imaging systems
Base station power
Set-top boxes
Printers
DDR termination

o 70°C

DC-to-DC Controller with Tracking

ADP1823

TYPICAL APPLICATION CIRCUIT

IN = 12V

390pF

4.53kΩ

180µF

IRLR7807Z

2kΩ

1kΩ

1.8V,
8A

560µF560µF

1.2V,
6A

180µF

IRLR7807Z

2kΩ

2kΩ

1µF

EN1

PV IN

TRK1

EN2

TRK2

VREG

BST2

0.47µF

2.2µH 2.2µH

IRFR3709Z

3900pF

4.53kΩ

BST1

DH2

DH1

ADP1823

SW2

SW1

2kΩ 2kΩ

390pF

CSL1

DL1

PGND1

FB1

COMP1

GND

Figure 1.

CSL2

DL2

PGND2

FB2

COMP2

FREQ

LDOSD

SYNC

0.47µF

IRFR3709Z

3900pF

05936-001

GENERAL DESCRIPTION

The ADP1823 is a versatile, dual, interleaved, synchronous,
PWM buck controller that generates two independent output
rails from an input of 3.7 V to 20 V, with a power input voltage
that ranges from 1 V to 24 V. Each controller can be configured
to provide output voltages from 0.6 V to 85% of the input voltage
and is sized to handle large MOSFETs for point-of-load regulators.
The two channels operate 180° out of phase, reducing stress on
the input capacitor and allowing smaller, low cost components.
The ADP1823 is ideal for a wide range of high power applications,
such as DSP and processor core I/O power, and general-purpose
power in telecommunications, medical imaging, PCs, gaming,
and industrial applications.

Rev. D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

The ADP1823 operates at a pin-selectable, fixed switching
f

requency of either 300 kHz or 600 kHz, minimizing external

component size and cost. For noise sensitive applications, it can
also be synchronized to an external clock to achieve switching
frequencies between 300 kHz and 1 MHz. The ADP1823 includes
soft start protection to prevent inrush current from the input
supply during startup, reverse current protection during soft
start for precharged outputs, as well as a unique adjustable
lossless current-limit scheme using external MOSFET sensing.

For applications requiring power supply sequencing, the
AD

P1823 also provides tracking inputs that allow the output
voltages to track during startup, shutdown, and faults. This
feature can also be used to implement DDR memory bus
termination.

The ADP1823 is specified over the −40°C to +125°C junction

emperature range and is available in a 32-lead LFCSP.

t

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006–2007 Analog Devices, Inc. All rights reserved.

ADP1823

www.BDTIC.com/ADI

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Typical Applicat i o n C i rc uit ............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Functional Block Diagram .............................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 9

Theory of Operation ...................................................................... 13

Input Power ................................................................................. 13

Start-Up Logic............................................................................. 13

Internal Linear Regulator .......................................................... 13

Oscillator and Synchronization................................................ 13

Error Amplifier........................................................................... 14

Soft Start ......................................................................................14

Power OK Indicator ................................................................... 14

Tr ac ki n g ....................................................................................... 14

MOSFET Drivers........................................................................ 15

Current Limit .............................................................................. 15

Applications Information.............................................................. 16

Selecting the Input Capacitor ................................................... 16

Selecting the MOSFETs ............................................................. 17

Setting the Current Limit .......................................................... 18

Feedback Voltage Divider ......................................................... 18

Compensating the Voltage Mode Buck Regulator................. 19

Soft Start...................................................................................... 22

Volt a ge Tr ack in g ......................................................................... 22

Coincident Tracking .................................................................. 23

Ratiometric Tracking................................................................. 23

Thermal Considerations............................................................ 24

PCB Layout Guidelines.................................................................. 25

LFCSP Considerations............................................................... 26

Application Circuits ....................................................................... 27

Outline Dimensions ....................................................................... 29

Ordering Guide .......................................................................... 29

REVISION HISTORY

10/07—Rev. C to Rev D

Changes to Table 1............................................................................ 3

Changes to Equation 33 and Type III Compensator Section ... 21

7/07—Rev. B to Rev C

hanges to Figure 34...................................................................... 27

C

5/07—Rev. A to Rev. B

C

hanges to Features Section............................................................ 1

Changes to General Description Section ...................................... 1

Changes to Power Supply and Logic Thresholds Sections.......... 3

Changes to Absolute Maximum Ratings Section......................... 5

Changes to Figure 17...................................................................... 11

Changes to Theory of Operation Section.................................... 13

Changes to Current Limit Section................................................ 15

Changes to Setting the Current Limit Section............................ 18

Changes to Compensating the Voltage Mode Buck

Regulator Section............................................................................ 19

Inserted Figure 25........................................................................... 19

Deleted Table 4................................................................................ 27

Changes to Application Circuits Section..................................... 27

Changes to Figure 34...................................................................... 27

11/06—Rev. 0 to Rev. A

C

hanges to Features and Applications Sections ............................1

Changes to Specifications Section...................................................3

Changes to Absolute Maximum Ratings Section..........................5

Replaced Theory of Operation Section ....................................... 13

Added Feedback Voltage Divider Section................................... 18

Changes to Ratiometric Tracking Section................................... 23

Replaced PCB Layout Guidelines Section................................... 25

Added Application Circuits Section ............................................ 29

Changes to Ordering Guide.......................................................... 31

4/06—Revision 0: Initial Version

Rev. D | Page 2 of 32

ADP1823

www.BDTIC.com/ADI

SPECIFICATIONS

IN = 12 V, ENx = FREQ = PV = VREG = 5 V, SYNC = GND, TJ = −40°C to +125°C, unless otherwise specified. All limits at temperature
extremes are guaranteed via correlation using standard statistical quality control (SQC). Typical values are at T

Table 1.

Parameter Conditions Min Typ Max Unit

POWER SUPPLY

IN Input Voltage PV = VREG (using internal regulator) 5.5 20 V
IN = PV = VREG (not using internal regulator) 3.7 5.5 V
IN Quiescent Current Not switching, I
IN Shutdown Current EN1 = EN2 = GND 10 20 A
VREG Undervoltage Lockout Threshold VREG rising 2.4 2.7 2.9 V
VREG Undervoltage Lockout Hysteresis 0.125 V

ERROR AMPLIFIER

FB1, FB2 Regulation Voltage TA = 25°C, TRK1, TRK2 > 700 mV 597 600 603 mV
T
T
T
FB1, FB2 Input Bias Current 100 nA
Open-Loop Voltage Gain 70 dB
Gain-Bandwidth Product 20 MHz
COMP1, COMP2 Sink Current 600 A
COMP1, COMP2 Source Current 120 A
COMP1, COMP2 Clamp High Voltage 2.4 V
COMP1, COMP2 Clamp Low Voltage 0.75 V

LINEAR REGULATOR

VREG Output Voltage TA = 25°C, I

VREG Load Regulation I
VREG Line Regulation IN = 7 V to 20 V, I
VREG Current Limit VREG = 4 V 220 mA
VREG Short-Circuit Current VREG < 0.5 V 50 140 200 mA
IN to VREG Dropout Voltage I
VREG Minimum Output Capacitance 1 F

PWM CONTROLLER

PWM Ramp Voltage Peak SYNC = GND 1.3 V
DH1, DH2 Maximum Duty Cycle FREQ = GND (300 kHz) 85 90 %
DH1, DH2 Minimum Duty Cycle FREQ = GND (300 kHz) 1 3 %

SOFT START

SS1, SS2 Pull-Up Resistance SS1, SS2 = GND 90 kΩ
SS1, SS2 Pull-Down Resistance SS1, SS2 = 0.6 V 6 kΩ
SS1, SS2 to FB1, FB2 Offset Voltage SS1, SS2 = 0 mV to 500 mV −45 mV
SS1, SS2 Pull-Up Voltage 0.8 V

TRACKING

TRK1, TRK2 Common-Mode Input Voltage Range 0 600 mV
TRK1, TRK2 to FB1, FB2 Offset Voltage TRK1, TRK2 = 0 mV to 500 mV −5 +5 mV
TRK1, TRK2 Input Bias Current 100 nA

= 0°C to 85°C, TRK1, TRK2 > 700 mV 591 609 mV

J

= −40°C to +125°C, TRK1, TRK2 > 700 mV 588 612 mV

J

= 0°C to 70°C, TRK1, TRK2 > 700 mV 595 605 mV

J

IN = 7 V to 20 V, I

= −40°C to +85°C

T

A

= 0 mA to 100 mA, IN = 12 V −40 mV

VREG

= 100 mA, IN < 5 V 0.7 1.4 V

VREG

= 0 mA 1.5 3 mA

VREG

= 20 mA 4.85 5.0 5.15 V

VREG

= 0 mA to 100 mA,

VREG

= 20 mA 1 mV

VREG

= 25°C.

A

4.75 5.0 5.25 V

Rev. D | Page 3 of 32

ADP1823

www.BDTIC.com/ADI

Parameter Conditions Min Typ Max Unit

OSCILLATOR

Oscillator Frequency SYNC = FREQ = GND (fSW = f
SYNC = GND, FREQ = VREG (fSW = f
SYNC Synchronization Range

1

FREQ = GND, SYNC = 600 kHz to 1.2 MHz (fSW = f
FREQ = VREG, SYNC = 1.2 MHz to 2 MHz (fSW = f
SYNC Minimum Input Pulse Width 200 ns

CURRENT SENSE

CSL1, CSL2 Threshold Voltage Relative to PGND −30 0 +30 mV
CSL1, CSL2 Output Current CSL1, CSL2 = PGND 44 50 56 A
Current Sense Blanking Period 100 ns

GATE DRIVERS

DH1, DH2 Rise Time CDH = 3 nF, V
DH1, DH2 Fall Time CDH = 3 nF, V

− VSW = 5 V 15 ns

BST

− VSW = 5 V 10 ns

BST

DL1, DL2 Rise Time CDL = 3 nF 15 ns
DL1, DL2 Fall Time CDL = 3 nF 10 ns
DH to DL, DL to DH Dead Time 40 ns

LOGIC THRESHOLDS

SYNC, FREQ, LDOSD Input High Voltage 2.2 V
SYNC, FREQ, LDOSD Input Low Voltage 0.4 V
SYNC, FREQ Input Leakage Current SYNC, FREQ = 0 V to 5.5 V 1 A
LDOSD Pull-Down Resistance 100 kΩ
EN1, EN2 Input High Voltage IN = 3.7 V to 20 V 2.0 V
EN1, EN2 Input Low Voltage IN = 3.7 V to 20 V 0.8 V
EN1, EN2 Current Source EN1, EN2 = 0 V to 3.0 V −0.05 −0.6 −1.5 A
EN1, EN2 Input Impedance to 5 V Zener EN1, EN2 = 5.5 V to 20 V 100 kΩ

THERMAL SHUTDOWN

Thermal Shutdown Threshold
Thermal Shutdown Hysteresis

2

2

145

15

POWER GOOD

FB1, UV2 Overvoltage Threshold V

, V

rising 750 mV

FB1

UV2

FB1, UV2 Overvoltage Hysteresis 50 mV
FB1, UV2 Undervoltage Threshold V

, V

rising 550 mV

FB1

UV2

FB1, UV2 Undervoltage Hysteresis 50 mV
POK1, POK2 Propagation Delay 8 s
POK1, POK2 Off Leakage Current V
POK1, POK2 Output Low Voltage I

POK1

POK1

, V

= 5.5 V 1 A

POK2

, I

= 10 mA 150 500 mV

POK2

UV2 Input Bias Current 10 100 nA

1

SYNC input frequency is 2× the single-channel switching frequency. The SYNC frequency is divided by 2, and the separate phases were used to clock the controllers.

2

Guaranteed by design and not subject to production test.

) 240 300 370 kHz

OSC

) 480 600 720 kHz

OSC

/2) 300 600 kHz

SYNC

/2) 600 1000 kHz

SYNC

°C
°C

Rev. D | Page 4 of 32

ADP1823

www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

IN, EN1, EN2 −0.3 V to +20 V
BST1, BST2 −0.3 V to +30 V
BST1, BST2 to SW1, SW2 −0.3 V to +6 V
CSL1, CSL2 −1 V to +30 V
SW1, SW2 −2 V to +30 V
DH1 SW1 − 0.3 V to BST1 + 0.3 V
DH2 SW2 − 0.3 V to BST2 + 0.3 V
DL1, DL2 to PGND −0.3 V to PV + 0.3 V
PGND to GND ±2 V
LDOSD, SYNC, FREQ, COMP1,

−0.3 V to +6 V
COMP2, SS1, SS2, FB1, FB2, VREG,
PV, POK1, POK2, TRK1, TRK2

θJA 4-Layer

(JEDEC Standard Board)

1, 2

45°C/W

Operating Ambient Temperature −40°C < TA < +85°C
Operating Junction Temperature

3

−55°C < TJ < +125°C

Storage Temperature Range −65°C to +150°C

1

Measured with exposed pad attached to PCB.

2

Junction-to-ambient thermal resistance (θJA) of the package is based on

modeling and calculation using a 4-layer board. The junction-to-ambient
thermal resistance is application and board-layout dependent. In appl ications
where high maximum power dissipation exists, attention to thermal
dissipation issues in board design is required. For more information, refer
to Application Note AN-772, A Design and Manufacturing Guide for the Lead
Frame Chip Scale Package (LFCSP).

3

In applications where high power dissipation and poor package thermal

resistance are present, the maximum ambient temperature may have to be
derated. Maximum ambient temperature (T
maximum operating junction temperature (T
power dissipation of the device in the application (P
to-ambient thermal resistance of the part/package in the application (θJA),
and is given by: T

A_MAX

= T

J_MAX_OP

− (θJA × P

) is dependent on the

A_MAX

= 125oC), the maximum

J_MAX_OP

D_MAX

).

D_MAX

), and the junction-

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. D | Page 5 of 32

ADP1823

www.BDTIC.com/ADI

FUNCTIONAL BLOCK DIAGRAM

VREG

0.75V

0.55V

VREG

–
+
+
+

0.8V

FAULT1

–
+
+
+

0.8V

FAULT2

VREG

LDOSD

EN1

EN2

FREQ

SYNC

COMP1

FB1

TRK1

SS1

COMP2

FB2

TRK2

UV2

SS2

0.6V

0.8V

OSCILLATOR
PHASE 1 = 0°
PHASE 2 = 180°

REF

0.6V

0.6V

CK1

RAMP1

CK2

RAMP2

RAMP1

RAMP2

0.75V

0.55V

0.75V

0.55V

UVLO

+

–

+

–

+

–

+

–

+

–

+

–

IN

LINEAR REG

LOGIC

FAULT2FAULT1

50µA

THERMAL

SHUTDOWN

VREG

50µA

ILIM2

CK2

VREG

ILIM1

CK1

ILIM2

PWM

R

PWM

R

ADP1823

QS

Q

+

–

QS

Q

+

–

BST1

DH1

SW1

PV

DL1

PGND1

CSL1

POK1

BST2

DH2

SW2

PV

DL2

PGND2

CSL2

POK2

GND

BOTTOM PADDLE

OF LFCSP

Figure 2.

Rev. D | Page 6 of 32

05936-002

ADP1823

www.BDTIC.com/ADI

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

OMP1

S1

C

TRK1

S

VREG

IN

LDOSD

EN2

EN1

28

27

26

25

29

31

30

32

1FB1
2SYNC
3FREQ
4GND
5UV2
6FB2
7COMP2
8TRK2

PIN 1
INDICATOR

ADP1823

TOP VIEW

(Not to Scale)

1

9

1

10

12

SS2

DH2

BST2

POK2

13

SW2

24 PO K1
23 BST 1
22 DH1
21 SW 1
20 CSL 1
19 PG ND1
18 DL1
17 PV

14

15

16

DL2

CSL2

PGND2

05936-003

Figure 3. Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

1 FB1

Feedback Voltage Input for Channel 1. Connect a resistor divider fr

om the buck regulator output to GND and

tie the tap to FB1 to set the output voltage.

2 SYNC

Frequency Synchronization Input. Accepts external signal between 600 kHz and 1.2 MHz or between 1.2 MHz
and 2 MH

z depending on whether FREQ is low or high, respectively. Connect SYNC to ground if not used.
3 FREQ Frequency Select Input. Low for 300 kHz or high for 600 kHz.
4 GND

5 UV2

Ground. Connect to a ground plane directly beneath the ADP1823. Tie the bottom of the feedback dividers to
this GND

Input to the POK2 Undervoltage and Overvoltage Compar

.

ators. For the default thresholds, connect UV2

directly to FB2. For some tracking applications, connect UV2 to an extra tap on the FB2 voltage divider string.

6 FB2

Feedback Voltage Input for Channel 2. Connect a resistor divider fr

om the buck regulator output to GND and

tie the tap to FB2 to set the output voltage.
7 COMP2 Error Amplifier Output for Channel 2. Connect an RC network from COMP2 to FB2 to compensate Channel 2.
8 TRK2

Tracking Input for Channel 2. To track a master voltage

, drive TRK2 from a voltage divider to the master

voltage. If the tracking function is not used, connect TRK2 to VREG.
9 SS2 Soft Start Control Input. Connect a capacitor from SS2 to GND to set the soft start period.
10 POK2

Open-Drain Power OK Output for Channel 2. Sinks current when UV2 is out of r

egulation. Connect a pull-up

resistor from POK2 to VREG.
11 BST2

Boost Capacitor Input for Channel 2. Powers the high-side ga

te driver, DH2. Connect a 0.22 F to 0.47 F

ceramic capacitor from BST2 to SW2 and a Schottky diode from PV to BST2.
12 DH2 High-Side (Switch) Gate Driver Output for Channel 2.
13 SW2 Switch Node Connection for Channel 2.
14 CSL2

Current Sense Comparator Inverting Input for Channel 2. Connect a resistor between CSL2 and SW2 to set

rent-limit offset.

the cur
15 PGND2 Ground for Channel 2 Gate Driver. Connect to a ground plane directly beneath the ADP1823.
16 DL2 Low-Side (Synchronous Rectifier) Gate Driver Output for Channel 2.
17 PV

Positive Input Voltage for Gate Driver DL1 and Gate Driv

er DL2. Connect PV to VREG and bypass to ground

with a 1 µF capacitor.
18 DL1 Low-Side (Synchronous Rectifier) Gate Driver Output for Channel 1.
19 PGND1 Ground for Channel 1 Gate Driver. Connect to a ground plane directly beneath the ADP1823.
20 CSL1

Current Sense Comparator Inverting Input for Channel 1. Connect a resistor between CSL1 and SW1 to set

rent-limit offset.

the cur
21 SW1 Switch Node Connection for Channel 1.
22 DH1 High-Side (Switch) Gate Driver Output for Channel 1.
23 BST1

Boost Capacitor Input for Channel 1. Powers the high-side ga

te driver, DH1. Connect a 0.22 F to 0.47 F

ceramic capacitor from BST1 to SW1 and a Schottky diode from PV to BST1.

Rev. D | Page 7 of 32

ADP1823

www.BDTIC.com/ADI

Pin No. Mnemonic Description

24 POK1

25 EN1

26 EN2

27 LDOSD

28 IN

29 VREG

30 SS1 Soft Start Control Input. Connect a capacitor from SS1 to GND to set the soft start period.
31 TRK1

32 COMP1 Error Amplifier Output for Channel 1. Connect an RC network from COMP1 to FB1 to compensate Channel 1.

Open-Drain Power OK Output for Channel 1. Sinks current when FB1 is out of r
resistor from POK1 to VREG.

Enable Input for Channel 1. Drive EN1 high to turn on the Chann
the Channel 1 controller. Enabling starts the internal LDO. Tie to IN for automatic startup.

Enable Input for Channel 2. Drive EN2 high to turn on the Chann
the Channel 2 controller. Enabling starts the internal LDO. Tie to IN for automatic startup.

LDO Shut-Down Input. Only used to shut do
Otherwise, connect LDOSD to GND or leave it open because it has an internal 100 kΩ pull-down resistor.

Input Supply to the Internal Linear Regulator. Drive IN with 5.5
For input voltages between 3.7 V and 5.5 V, tie IN to VREG and PV.

Output of the Internal Linear Regulator (LDO). The internal cir
Bypass VREG to the ground plane with a 1 F ceramic capacitor.

Tracking Input for Channel 1. To track a master voltage, dr
If the tracking function is not used, connect TRK1 to VREG.

wn the LDO in those applications where IN is tied directly to VREG.

el 1 controller, and drive it low to turn off

el 2 controller, and drive it low to turn off

V to 20 V to power the ADP1823 from the LDO.

cuitry and gate drivers are powered from VREG.

ive TRK1 from a voltage divider to the master voltage.

egulation. Connect a pull-up

Rev. D | Page 8 of 32

ADP1823

www.BDTIC.com/ADI

TYPICAL PERFORMANCE CHARACTERISTICS

95

90

85

80

EFFICIENCY (%)

75

VIN = 5V

VIN = 12V

VIN = 20V

VIN = 15V

92

90

88

86

84

EFFICIENCY (%)

82

80

SWITCHI NG FREQUENCY = 300kHz

SWITCHI NG FREQUENCY = 600kHz

70

02

Figure 4. Efficiency vs. Load Current, V

51015

LOAD CURRENT (A)

= 1.8 V, 300 kHz Switching

OUT

0

05936-004

78

020

Figure 7. Efficiency vs. Load Current, V

95

V

= 3.3V

OUT

90

85

80

EFFICIENCY (%)

75

70

02

51015

Figure 5. Efficiency vs. Load Current, V

94

92

90

88

86

SWITCHING FREQUENCY = 600kHz

84

EFFICIENCY (%)

82

80

78

02

51015

Figure 6. Efficiency vs. Load Current, V

V

= 1.8V

OUT

V

= 1.2V

OUT

LOAD CURRENT (A)

= 12 V, 300 kHz Switching

IN

SWITCHI NG FREQUENCY = 300kHz

LOAD CURRENT (A)

= 5 V, V

IN

OUT

= 1.8 V

0

05936-005

0

05936-006

4.980

4.975

4.970

VREG VOLTAGE (V)

4.965

4.960
–40 85

Figure 8. VREG Voltage vs. Temperature

4.970

4.968

4.966

4.964

4.962

4.960

VREG (V)

4.958

4.956

4.954

4.952

4.950

520

Figure 9. VREG vs. Input Voltage, 10 mA Load

51015

LOAD CURRENT (A)

= 12 V, V

IN

OUT

–15 10 35 60

TEMPERATURE ( °C)

811

INPUT VOLTAGE (V)

1417

= 1.8 V

05936-007

05936-008

05936-009

Rev. D | Page 9 of 32

ADP1823

www.BDTIC.com/ADI

4.960

0.6010

4.956

4.952

VREG (V)

4.948

4.944

4.940
0 100

20 40 60 80

LOAD CURRENT (mA)

Figure 10. VREG vs. Load Current, VIN = 12 V

5

4

3

2

VREG OUTPUT (V)

1

0.6005

0.6000

0.5995

0.5990

FEEDBACK VOLT AGE (V)

0.5985

0.5980
–40 85

05936-010

–15 10 35 60

TEMPERATURE ( °C)

05936-013

Figure 13. Feedback Voltage vs. Temperature, VIN = 12 V

330

320

310

300

290

FREQUENCY (Hz)

280

270

0

0 50 100 150 200 250

LOAD CURRENT (mA)

Figure 11. VREG Current-Limit Foldback

T

VREG, AC-CO UPLED, 1V/ DIV

SW2 PIN, V

= 1.2V, 10V /DIV

OUT

SW1 PIN, V

200ns/DIV

= 1.8V, 10V/DIV

OUT

Figure 12. VREG Output During Normal Operation

260

–40 85

05936-011

–15 10 35 60

TEMPERATURE ( °C)

05936-014

Figure 14. Switching Frequency vs. Temperature, VIN = 12 V

5

4

3

2

SUPPLY CURRENT (mA)

1

05936-012

0

22

5 8 11 14 17

SUPPLY VOLTAGE (V)

0

05936-015

Figure 15. Supply Current vs. Supply Voltage

Rev. D | Page 10 of 32