ANALOG DEVICES ADP1754 Service Manual

1.2 A, Low VIN, Low Dropout

V

V

V

V

V

V

V

FEATURES

Maximum output current: 1.2 A
Input voltage range: 1.6 V to 3.6 V
Low shutdown current: <2 µA
Very low dropout voltage: 105 mV @ 1.2 A load
Initial accuracy: ±1%
Accuracy over line, load, and temperature: ±2%
7 fixed output voltage options with soft start

0.75 V to 2.5 V (ADP1754)

Adjustable output voltage option with soft star t

0.75 V to 3.0 V (ADP1755)

High PSRR

65 dB @ 1 kHz
65 dB @ 10 kHz

54 dB @ 100 kHz
23 V rms at 0.75 V output
Stable with small 4.7 µF ceramic output capacitor
Excellent load and line transient response
Current-limit and thermal overload protection
Power-good indicator
Logic-controlled enable
Reverse current protection

APPLICATIONS

Server computers
Memory components
Telecommunications equipment
Network equipment
DSP/FPGA/microprocessor supplies
Instrumentation equipment/data acquisition systems

Linear Regulator

ADP1754/ADP1755

TYPICAL APPLICATION CIRCUITS

= 1.8

IN

4.7µF

100kΩ

PG

1

2

3

4

VIN

VIN

VIN

EN

16

VIN

VIN

ADP1754

TOP VIEW

(Not to Scale)

GND

PG

5

15

6

Figure 1. ADP1754 with Fixed Output Voltage, 1.5 V

= 1.8

IN

4.7µF

100kΩ

PG

1

2

3

4

VIN

VIN

VIN

EN

16

VIN

ADP1755

TOP VIEW

(Not to Scale)

GND

PG

5

15

VIN

6

Figure 2. ADP1755 with Adjustable Output Voltage, 0.75 V to 3.0 V

VOUT

14

VOUT

SS

7

14

SS

7

10nF

10nF

13

VOUT

VOUT

VOUT

VOUT

ADJ

NC

8

13

VOUT

VOUT

VOUT

VOUT

SENSE

NC

8

12

11

10

9

= 0.5V(1 + R1/R2)

OUT

12

11

10

9

R1

R2

OUT

4.7µF

= 1.5

4.7µF

07722-001

07722-002

GENERAL DESCRIPTION

The ADP1754/ADP1755 are low dropout (LDO) CMOS linear
regulators that operate from 1.6 V to 3.6 V and provide up to

1.2 A of output current. These low V

LDOs are ideal for

IN/VOUT

regulation of nanometer FPGA geometries operating from 2.5 V
down to 1.8 V I/O rails, and for powering core voltages down to

0.75 V. Using an advanced proprietary architecture, the ADP1754/
ADP1755 provide high power supply rejection ratio (PSRR) and
low noise, and achieve excellent line and load transient response
with only a small 4.7 µF ceramic output capacitor.

The ADP1754 is available in seven fixed output voltage options.
The ADP1755 is the adjustable version, which allows output

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

voltages that range from 0.75 V to 3.0 V via an external divider.
The ADP1754/ADP1755 allow an external soft start capacitor
to be connected to program the startup. A digital power-good
output allows power system monitors to check the health of the
output voltage.

The ADP1754/ADP1755 are available in a 16-lead, 4 mm × 4 mm
LFCSP, making them not only very compact solutions, but also
providing excellent thermal performance for applications that
require up to 1.2 A of output current in a small, low profile
footprint.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2008–2010 Analog Devices, Inc. All rights reserved.

ADP1754/ADP1755

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Typical Application Circuits ............................................................ 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Input and Output Capacitor, Recommended Specifications .. 4

Absolute Maximum Ratings ............................................................ 5

Thermal Data ................................................................................ 5

Thermal Resistance ...................................................................... 5

ESD Caution .................................................................................. 5

Pin Configurations and Function Descriptions ........................... 6

Typical Performance Characteristics ............................................. 7

Theory of Operation ...................................................................... 11

Soft Start Function (ADP1754/ADP1755) ............................. 11

Adjustable Output Voltage (ADP1755) ................................... 12

Enable Feature ............................................................................ 12

Power-Good Feature .................................................................. 12

Reverse Current Protection Feature ........................................ 13

Applications Information .............................................................. 14

Capacitor Selection .................................................................... 14

Undervoltage Lockout ............................................................... 15

Current-Limit and Thermal Overload Protection ................. 15

Thermal Considerations ............................................................ 15

PCB Layout Considerations ...................................................... 18

Outline Dimensions ....................................................................... 19

Ordering Guide .......................................................................... 19

REVISION HISTORY

2/10—Rev. A to Rev. B

Changes to Table 4 ............................................................................ 5

Changes to Ordering Guide .......................................................... 19

4/09—Rev. 0 to Rev. A

Changes to Adjustable Output Voltage Accuracy (ADP1755)

Parameter, Table 1 ............................................................................. 3

Changes to Table 3 ............................................................................ 5

10/08—Revision 0: Initial Version

Rev. B | Page 2 of 20

ADP1754/ADP1755

SPECIFICATIONS

VIN = (V

Table 1.

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

INPUT VOLTAGE RANGE VIN T
OPERATING SUPPLY CURRENT1 I
I
I
I
I

SHUTDOWN CURRENT I

OUTPUT VOLTAGE ACCURACY

Fixed Output Voltage Accuracy

Adjustable Output Voltage Accuracy

LINE REGULATION V
LOAD REGULATION3 V
DROPOUT VOLTAGE4 V
I
I
I
START-UP TIME5 t
C
CURRENT-LIMIT THRESHOLD6 I
THERMAL SHUTDOWN

Thermal Shutdown Threshold TSSD T

Thermal Shutdown Hysteresis TS

PG OUTPUT LOGIC LEVEL

PG Output Logic High PG

PG Output Logic Low PG

PG Output Delay from EN Transition

Low to High

PG OUTPUT THRESHOLD

Output Voltage Falling PG

Output Voltage Rising PG

EN INPUT

EN Input Logic High VIH 1.6 V ≤ VIN ≤ 3.6 V 1.2 V

EN Input Logic Low VIL 1.6 V ≤ VIN ≤ 3.6 V 0.4 V

EN Input Leakage Current V

UNDERVOLTAGE LOCKOUT UVLO

Input Voltage Rising UVLO

Input Voltage Falling UVLO

Hysteresis UVLO

SOFT START CURRENT ISS 1.6 V ≤ VIN ≤ 3.6 V
ADJ INPUT BIAS CURRENT (ADP1755) ADJ
SENSE INPUT BIAS CURRENT SNS

+ 0.4 V) or 1.6 V (whichever is greater), I

OUT

(ADP1754)

2

(ADP1755)

= 10 mA, CIN = C

OUT

= −40°C to +125°C 1.6 3.6 V

J

I

GND

GND-SD

= 500 A

OUT

= 100 mA

OUT

= 100 mA, TJ = −40°C to +125°C

OUT

= 1.2 A

OUT

= 1.2 A, TJ = −40°C to +125°C

OUT

EN = GND,

VIN = 1.6 V
EN = GND, VIN = 1.6 V, TJ = −40°C to +85°C
EN = GND, VIN = 3.6 V, TJ = −40°C to +85°C

I

V

OUT

I
10 mA < I

I

V

ADJ

I
10 mA < I

/VIN VIN = (V

OUT

/I

OUT

OUT

I

DROPOUT

CSS = 0 nF, I

START-UP

1.5 2 5 A

LIMIT

15

SD-HYS

1.6 V ≤ VIN ≤ 3.6 V, IOH < 1 µA 1.0 V

HIGH

1.6 V ≤ VIN ≤ 3.6 V, IOL < 2 mA 0.4 V

LOW

1.6 V ≤ V

1.6 V ≤ VIN ≤ 3.6 V −10 %

FAL L

1.6 V ≤ VIN ≤ 3.6 V −6.5 %

RISE

EN = VIN or GND 0.1 1 µA

I-LEAKAGE

TJ = −40°C to +125°C

RISE

TJ = −40°C to +125°C

FAL L

TJ = 25°C

HYS

= 10 mA −1 +1 %

OUT

= 10 mA to 1.2 A −1.5 +1.5 %

OUT

< 1.2 A, TJ = −40°C to +125°C −2 +2 %

OUT

= 10 mA 0.495 0.5 0.505 V

OUT

= 10 mA to 1.2 A 0.495 0.505 V

OUT

< 1.2 A, TJ = −40°C to +125°C 0.490 0.510 V

OUT

+ 0.4 V) to 3.6 V, TJ = −40°C to +125°C −0.3 +0.3 %/V

OUT

I

= 10 mA to 1.2 A, TJ = −40°C to +125°C 0.6 %/A

OUT

= 100 mA, V

OUT

= 100 mA, V

OUT

= 1.2 A, V

OUT

= 1.2 A, V

OUT

= 10 nF, I

SS

rising 150

J

OUT

OUT

OUT

OUT

≤ 3.6 V, CSS = 10 nF 5.5 ms

IN

= 4.7 µF, TA = 25°C, unless otherwise noted.

OUT

90
400
800

1.1

1.4

µA
µA
µA
mA
mA

2 6 µA
30 µA
100 µA

≥ 1.8 V 10 mV

OUT

≥ 1.8 V, TJ = −40°C to +125°C 16 mV

OUT

≥ 1.8 V 105 mV
≥ 1.8 V, TJ = −40°C to +125°C 200 mV

= 10 mA 200 µs

= 10 mA 5.2 ms

°C
°C

1.58 V

1.25 V
100 mV

0.6 0.9 1.2 µA

1.6 V ≤ VIN ≤ 3.6 V, TJ = −40°C to +125°C 10 150 nA

I-BIAS

1.6 V ≤ VIN ≤ 3.6 V 10 µA

I-BIAS

Rev. B | Page 3 of 20

ADP1754/ADP1755

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

OUTPUT NOISE OUT
10 Hz to 100 kHz, V

POWER SUPPLY REJECTION RATIO PSRR VIN = V
1 kHz, V
1 kHz, V
10 kHz, V
10 kHz, V
100 kHz, V
100 kHz, V

1

Minimum output load current is 500 A.

2

Accuracy when VOUT is connected directly to ADJ. When VOUT voltage is set by external feedback resistors, absolute accuracy in adjust mode depends on the

tolerances of resistors used.

3

Based on an end-point calculation using 10 mA and 1.2 A loads. See for typical load regulation performance. Figure 6

4

Dropout voltage is defined as the input to output voltage differential when the input voltage is set to the nominal output voltage. This applies only to output voltages

above 1.6 V.

5

Start-up time is defined as the time between the rising edge of EN to V

6

Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 1.0 V

output voltage is defined as the current that causes the output voltage to drop to 90% of 1.0 V, or 0.9 V.

INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS

Table 2.

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

MINIMUM INPUT AND OUTPUT CAPACITANCE1 C
CAPACITOR ESR R

1

The minimum input and output capacitance should be greater than 3.3 µF over the full range of operating conditions. The full range of operating conditions in the

application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended;
Y5V and Z5U capacitors are not recommended for use with this LDO.

10 Hz to 100 kHz, V

NOISE

+ 1 V, I

OUT

OUT

OUT

OUT

OUT

being at 95% of its nominal value.

OUT

TA = −40°C to +125°C 3.3 µF

MIN

T

ESR

= 0.75 V 23 µV rms

OUT

= 2.5 V 65 µV rms

OUT

= 10 mA

OUT

= 0.75 V 65 dB
= 2.5 V 56 dB

= 0.75 V 65 dB
= 2.5 V 56 dB

= 0.75 V 54 dB

OUT

= 2.5 V 51 dB

OUT

= −40°C to +125°C 0.001 0.1 Ω

A

Rev. B | Page 4 of 20

ADP1754/ADP1755

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

VIN to GND −0.3 V to +3.6 V
VOUT to GND −0.3 V to +3.6 V
EN to GND −0.3 V to +3.6 V
SS to GND −0.3 V to +3.6 V
PG to GND −0.3 V to +3.6 V
SENSE/ADJ to GND −0.3 V to +3.6 V
Storage Temperature Range −65°C to +150°C
Operating Junction Temperature Range −40°C to +125°C
Soldering Conditions JEDEC J-STD-020

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL DATA

Absolute maximum ratings apply individually only, not in
combination. The ADP1754/ADP1755 may be damaged if the
junction temperature limits are exceeded. Monitoring ambient
temperature does not guarantee that T
temperature limits. In applications with high power dissipation
and poor thermal resistance, the maximum ambient temperature
may need to be derated. In applications with moderate power
dissipation and low PCB thermal resistance, the maximum
ambient temperature can exceed the maximum limit as long
as the junction temperature is within specification limits.

The junction temperature (T
ambient temperature (T
(P

), and the junction-to-ambient thermal resistance of the

D

package (θ

). TJ is calculated using the following formula:

JA

T

= TA + (PD × θJA)

J

) of the device is dependent on the

J

), the power dissipation of the device

A

is within the specified

J

Junction-to-ambient thermal resistance (θ
based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent
on the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θ
on PCB material, layout, and environmental conditions. The
specified values of θ
board. Refer to JEDEC JESD51-7 for detailed information about
board construction. For more information, see the AN-772
Application Note, A Design and Manufacturing Guide for the
Lead Frame Chip Scale Package (LFCSP), at www.analog.com.

Ψ

is the junction-to-board thermal characterization parameter

JB

with units of °C/W. Ψ
calculation using a 4-layer board. The JESD51-12 document,

Guidelines for Reporting and Using Electronic Package Thermal
Information, states that thermal characterization parameters are

not the same as thermal resistances. Ψ
power flowing through multiple thermal paths rather than through
a single path as in thermal resistance, θ
paths include convection from the top of the package as well as
radiation from the package, factors that make Ψ
real-world applications. Maximum junction temperature (T
is calculated from the board temperature (T
dissipation (P

= TB + (PD × ΨJB)

T

J

Refer to the JEDEC JESD51-8 and JESD51-12 documents for more
detailed information about Ψ

THERMAL RESISTANCE

θJAand ΨJB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.

Table 4. Thermal Resistance

Package Type θJA ΨJB Unit

16-Lead LFCSP with Exposed Pad (CP-16-4) 42 25.5 °C/W

are based on a 4-layer, 4 in × 3 in circuit

JA

of the package is based on modeling and

JB

) using the following formula:

D

.

JB

) of the package is

JA

may vary, depending

JA

measures the component

JB

. Therefore, ΨJB thermal

JB

more useful in

JB

) and the power

B

)

J

ESD CAUTION

Rev. B | Page 5 of 20

ADP1754/ADP1755

T

T

2

T

T

2

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

VOU

VIN

VIN

VOU

14

13

15

16

PIN 1
INDICATO R

1VIN

2VIN

ADP1754

3VIN

TOP VIEW

(Not to Scale)

4EN

5

6

PG

NOTES

1. NC = NO CONNECT.
. THE EXPOS ED PAD ON THE BOTTOM O F THE LFCSP ENHANCES

THERMAL PERFORMANCE AND IS ELECTRICALLY CONNECTED TO GND
INSIDE THE PACKAGE. IT IS RECOMMENDED THAT THE EXP OSED PAD
BE CONNECTED TO THE GROUND PL ANE ON THE BOARD.

GND

7

SS

8

C
N

12 VOUT

11 VOUT

10 VOUT

9SENSE

1VIN

2VIN

ADP1755

3VIN

TOP VIEW

(Not to Scale)

4EN

NOTES

1. NC = NO CONNECT.
. THE EXPOS ED PAD ON THE BOTTOM O F THE LFCSP ENHANCES

THERMAL PERFORMANCE AND IS ELECTRICALLY CONNECTED TO GND
INSIDE THE PACKAGE. IT IS RECOMMENDED THAT THE EXP OSED PAD

07722-003

BE CONNECTED TO THE GROUND PL ANE ON THE BOARD.

VIN

VIN

15

16

PIN 1
INDICATO R

5

6

PG

GND

VOU

VOU

14

13

12 VOUT

11 VOUT

10 VOUT

9ADJ

8

7

C

SS

N

Figure 3. ADP1754 Pin Configuration Figure 4. ADP1755 Pin Configuration

Table 5. Pin Function Descriptions

ADP1754
Pin No.

1, 2, 3, 15,
16

4 4 EN

ADP1755
Pin No. Mnemonic Description

1, 2, 3, 15,
16

VIN

Regulator Input Supply. Bypass VIN to GND with a 4.7 µF or greater capacitor. Note that all five
VIN pins must be connected to the source.

Enable Input. Drive EN high to turn on the regulator; drive it low to turn off the regulator. For
automatic startup, connect EN to VIN.

5 5 PG

Power Good. This open-drain output requires an external pull-up resistor to VIN. If the part is in
shutdown mode, current-limit mode, thermal shutdown, or if it falls below 90% of the nominal

output voltage, PG immediately transitions low.
6 6 GND Ground.
7 7 SS Soft Start. A capacitor connected to this pin determines the soft start time.
8 8 NC Not Connected. No internal connection.
9 N/A SENSE

Sense. This pin measures the actual output voltage at the load and feeds it to the error

amplifier. Connect SENSE as close as possible to the load to minimize the effect of IR drop

between the regulator output and the load.
N/A 9 ADJ Adjust. A resistor divider from VOUT to ADJ sets the output voltage.
10, 11, 12,

13, 14

10, 11, 12,
13, 14

17 (EPAD) 17 (EPAD)

VOUT

Exposed
paddle
(EPAD)

Regulated Output Voltage. Bypass VOUT to GND with a 4.7 µF or greater capacitor. Note that all

five VOUT pins must be connected to the load.

The exposed pad on the bottom of the LFCSP package enhances thermal performance and is

electrically connected to GND inside the package. It is recommended that the exposed pad be

connected to the ground plane on the board.

07722-004

Rev. B | Page 6 of 20