Datasheet ADP1706, ADP1707, ADP1708 Datasheet (ANALOG DEVICES)

1 A, Low Dropout,

V

A

V

FEATURES

Maximum output current: 1 A
Input voltage range: 2.5 V to 5.5 V
Low shutdown current: <1 μA
Low dropout voltage: 345 mV @ 1 A load
Initial accuracy: ±1%
Accuracy over line, load, and temperature: ±2.5%
16 fixed output voltage options with soft start:

0.75 V to 3.3 V (ADP1706)

16 fixed output voltage options with tracking

0.75 V to 3.3 V (ADP1707)

Adjustable output voltage option:

0.8 V to 5.0 V (ADP1708)
Stable with small 4.7 μF ceramic output capacitor
Excellent load/line transient response
Current limit and thermal overload protection
Logic-controlled enable
Available in an 8-lead, exposed paddle SOIC and

3 mm × 3 mm, 8-lead exposed paddle LFCSP

APPLICATIONS

Notebook computers
Memory components
Telecommunications equipment
Network equipment
DSP/FPGA/microprocessor supplies
Instrumentation equipment/data acquisition systems

CMOS Linear Regulator

ADP1706/ADP1707/ADP1708

TYPICAL APPLICATION CIRCUITS

ADP1706

1

EN

2

SENSE

GND

3

V

= 5V

IN

IN

4

IN

Figure 1. ADP1706 with Fixed Output Voltage, 3.3 V

ADP1707

1

EN

2

GND

3

IN

= 5V

4

V

OUT

3

2

1

0

IN

IN

(V)

12345

V

TRK

Figure 2. ADP1707 with Output Voltage Tracking

DP1708

IN

= 5V

1

2

3

4

EN

GND

IN

IN

ADJ

SENSE

OUT

OUT

Figure 3. ADP1708 with Adjustable Output Voltage, 0.8 V to 5.0 V

SS

OUT

OUT

TRK

SENSE

OUT

OUT

(V)

8

7

6

5

10nF

8

7

6

5

8

7

6

5

R2

R1

4.7µF4.7µF

V

OUT

4.7µF4.7µF

V

TRK

4.7µF4.7µF

V

= 0.8V(1 + R1/R2)

OUT

= 3.3V

V

OUT

06640-001

06640-003

06640-002

GENERAL DESCRIPTION

The ADP1706/ADP1707/ADP1708 are CMOS, low dropout
linear regulators that operate from 2.5 V to 5.5 V and provide
up to 1 A of output current. Using an advanced proprietary
architecture, they provide high power supply rejection and
achieve excellent line and load transient response with a small

4.7 μF ceramic output capacitor.

The ADP1706/ADP1707 are available in 16 fixed output volt­age options. The ADP1708 is available in an adjustable version,
which allows output voltages that range from 0.8 V to 5.0 V via
an external divider. The ADP1706 allows an external soft start
capacitor to be connected to program the start-up time; the

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

ADP1707 and ADP1708 contain internal soft start capacitors
that give a typical start-up time of 100 μs. The ADP1707
includes a tracking feature that allows the output to follow an
external voltage rail or reference.

The ADP1706/ADP1707/ADP1708 are available in an 8-lead,
exposed paddle SOIC package and an 8-lead, 3 mm × 3 mm
exposed paddle LFCSP, making them not only very compact
solutions but also providing excellent thermal performance for
applications requiring up to 1 A of output current in a small,
low profile footprint.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2007 Analog Devices, Inc. All rights reserved.

ADP1706/ADP1707/ADP1708

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

Typical Application Circuits............................................................ 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 5

Thermal Resistance ...................................................................... 5

ESD Caution.................................................................................. 5

Pin Configurations and Function Descriptions ........................... 6

Typical Performance Characteristics ............................................. 7

Theory of Operation ...................................................................... 10

REVISION HISTORY

6/07—Revision 0: Initial Version

Soft Start Function (ADP1706)................................................ 10

Adjustable Output Voltage (ADP1708)................................... 11

Track Mode (ADP1707) ............................................................ 11

Enable Feature ............................................................................ 11

Application Information................................................................ 12

Capacitor Selection .................................................................... 12

Voltage Tracking Applications.................................................. 12

Current Limit and Thermal Overload Protection ................. 12

Thermal Considerations............................................................ 13

PCB Layout Considerations...................................................... 15

Outline Dimensions....................................................................... 16

Ordering Guide .......................................................................... 17

Rev. 0 | Page 2 of 20

ADP1706/ADP1707/ADP1708

SPECIFICATIONS

VIN = (V

Table 1.

Parameter Symbol Test Conditions Min Typ Max Unit

INPUT VOLTAGE RANGE VIN T
OPERATING SUPPLY CURRENT I
I
I
I
I
SHUTDOWN CURRENT I
EN = GND, TJ = −40°C to +125°C 1.0 μA
OUTPUT VOLTAGE ACCURACY

Fixed Output Voltage Accuracy
(ADP1706 and ADP1707)

Adjustable Output Voltage Accuracy
(ADP1708)

LINE REGULATION ∆V

LOAD REGULATION
DROPOUT VOLTAGE

I
I
I

I

START-UP TIME

ADP1707 and ADP1708 100 μs

ADP1706 CSS = 10 nF 7.3 ms
CURRENT LIMIT THRESHOLD
THERMAL SHUTDOWN

Thermal Shutdown Threshold TSSD T

Thermal Shutdown Hysteresis TS

SOFT START SOURCE CURRENT (ADP1706) SS
V

OUT

EN INPUT

EN Input Logic High VIH 2.5 V ≤ VIN ≤ 5.5 V 1.8 V

EN Input Logic Low VIL 2.5 V ≤ VIN ≤ 5.5 V 0.4 V

EN Input Leakage Current V
ADJ INPUT BIAS CURRENT (ADP1708) ADJ
SENSE INPUT BIAS CURRENT SNS

+ 0.6 V) or 2.5 V (whichever is greater), I

OUT

1

2

3

4

5

to V

ACCURACY (ADP1707) V

TRK

= 10 mA, CIN = C

OUT

= –40°C to +125°C 2.5 5.5 V

J

I

GND

EN = GND 0.1 μA

GND-SD

V

I

OUT

I
100 μA < I
V

I

OUT

I
100 μA < I

/∆VIN

OUT

∆V

/∆I

OUT

OUT

V

I

DROPOUT

t

START-UP

I

1.1 1.5 1.8 A

LIMIT

15

SD-HYS

SS = GND 0.6 1.1 1.6 μA

I-SOURCE

TRK-ERROR

EN = IN or GND 0.1 1 μA

I-LEAKAGE

30 100 nA

I-BIAS

4 μA

I-BIAS

= 0 mA 50 μA

OUT

= 100 mA 310 μA

OUT

= 100 mA, TJ = −40°C to +125°C 390 μA

OUT

= 1 A 1.2 mA

OUT

= 1 A, TJ = −40°C to +125°C 1.55 mA

OUT

= 10 mA −1 +1 %

OUT

= 100 μA to 1 A −1.5 +1.5 %

OUT

OUT

= 10 mA 0.792 0.8 0.808 V

OUT

= 100 μA to 1 A 0.788 0.812 V

OUT

OUT

= (V

V

IN

T

= −40°C to +125°C

J

I

OUT

OUT

I

OUT

= −40°C to +125°C

T

J

OUT

OUT

OUT

I

OUT

T

= −40°C to +125°C

J

OUT

I

OUT

= −40°C to +125°C

T

J

rising 150

J

0 V ≤ V
T

= −40°C to +125°C

J

0 V ≤ V
T

= −40°C to +125°C

J

Rev. 0 | Page 3 of 20

+ 0.6 V) to 5.5 V,

OUT

= 10 mA to 1 A, TJ = −40°C to +125°C 0.001 %/mA
= 100 mA, V
= 100 mA, V

= 1 A, V
= 1 A, V
= 100 mA, 2.5 V ≤ V
= 100 mA, 2.5 V ≤ V

= 1 A, 2.5 V ≤ V
= 1 A, 2.5 V ≤ V

≤ (0.5 × V

TRK

≤ (0.5 × V

TRK

= 4.7 μF, TA = 25°C, unless otherwise noted.

OUT

< 1 A, TJ = −40°C to +125°C −2.5 +2.5 %

< 1 A, TJ = −40°C to +125°C 0.780 0.820 V

−0.1 +0.1 %/ V

≥ 3.3 V 33 mV

OUT

≥ 3.3 V,

OUT

≥ 3.3 V 345 mV

OUT

≥ 3.3 V, TJ = −40°C to +125°C 600 mV

OUT

< 3.3 V 35 mV

OUT

< 3.3 V,

OUT

< 3.3 V 365 mV

OUT

< 3.3 V,

OUT

OUT (NOM)

OUT (NOM)

), V

), V

OUT (NOM)

OUT (NOM)

≤ 1.8 V,

> 1.8 V,

55 mV

60 mV

630 mV

−40 +40 mV

−60 +60 mV

°C
°C

ADP1706/ADP1707/ADP1708

Parameter Symbol Test Conditions Min Typ Max Unit

OUTPUT NOISE OUT
10 Hz to 100 kHz, V
POWER SUPPLY REJECTION RATIO PSRR 1 kHz, V
1 kHz, V

1

Accuracy when OUT is connected directly to ADJ. When OUT voltage is set by external feedback resistors, absolute accuracy in adjust mode depends on the tolerances

of resistors used.

2

Based on an end-point calculation using 10 mA and 1 A loads. See Figure 11 for typical load regulation performance for loads less than 10 mA.

3

Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output

voltages above 2.5 V.

4

Start-up time is defined as the time between the rising edge of EN to OUT being at 95% of its nominal value.

5

Current limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 1.0 V

output voltage is defined as the current that causes the output voltage to drop to 90% of 1.0 V, or 0.9 V.

10 Hz to 100 kHz, V

NOISE

OUT

OUT

= 0.75 V 125 μV rms

OUT

= 3.3 V 450 μV rms

OUT

= 0.75 V 70 dB
= 3.3 V 56 dB

Rev. 0 | Page 4 of 20

ADP1706/ADP1707/ADP1708

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

IN to GND −0.3 V to +6 V
OUT to GND –0.3 V to IN
EN to GND –0.3 V to +6 V
SS/ADJ/TRK to GND –0.3 V to +6 V
SENSE to GND –0.3 V to +6 V
Storage Temperature Range –65°C to +150°C
Operating Junction Temperature Range –40°C to +125°C
Soldering Conditions JEDEC J-STD-020

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 3. Thermal Resistance

Package Type θJA Unit

8-Lead SOIC (Exposed Paddle) 58 °C/W
8-Lead 3 mm × 3 mm LFCSP (Exposed Paddle) 66 °C/W

ESD CAUTION

Rev. 0 | Page 5 of 20

ADP1706/ADP1707/ADP1708

G

G

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

EN

1

ADP1706

2

GND

IN

IN

TOP VIEW

3

(Not to S cale)

4

Figure 4. 8-Lead SOIC, ADP1706 Figure 5. 8-Lead LFCSP, ADP1706

EN

1

IN

IN

ADP1707

2

TOP VIEW

3

(Not to S cale)

4

GND

Figure 6. 8-Lead SOIC, ADP1707 Figure 7. 8-Lead LFCSP, ADP1707

EN

1

IN

IN

ADP1708

2

TOP VIEW

3

(Not to Scale)

4

GND

Figure 8. 8-Lead SOIC, ADP1708 Figure 9. 8-Lead LFCSP, ADP1708

8

7

6

5

8

7

6

5

8

7

6

5

SS

SENSE

OUT

OUT

TRK

SENSE

OUT

OUT

ADJ

SENSE

OUT

OUT

PIN 1

1EN

ND

06640-004

ND

06640-006

06640-005

3IN

(Not to Scale)

4IN

1EN

2

3IN

(Not to Scale)

4IN

1EN

2GND

3IN

(Not to Scale)

4IN

ADP1706

TOP VIEW

PIN 1
INDICATOR

ADP1707

TOP VIEW

PIN 1
INDICATOR

ADP1708

TOP VIEW

INDICATOR

2

8SS

7 SENSE

6OUT

5OUT

8TRK

7SENSE

6OUT

5OUT

8 ADJ

7 SENSE

6OUT

5OUT

06640-007

06640-009

06640-008

Table 4. Pin Function Descriptions

ADP1706
Pin No.

1 1 1 EN

ADP1707
Pin No.

ADP1708
Pin No.

Mnemonic Description

Enable Input. Drive EN high to turn on the regulator; drive it low to turn off the

regulator. For automatic startup, connect EN to IN.
2 2 2 GND Ground.
3, 4 3, 4 3, 4 IN Regulator Input Supply. Bypass IN to GND with a 4.7 μF or greater capacitor.
5, 6 5, 6 5, 6 OUT Regulated Output Voltage. Bypass OUT to GND with a 4.7 μF or greater capacitor.
7 7 7 SENSE

Sense. Measures the actual output voltage at the load and feeds it to the error

amplifier. Connect SENSE as close as possible to the load to minimize the effect

of IR drop between the regulator output and the load.
8 N/A N/A SS Soft Start. A capacitor connected to this pin determines the soft start time.
N/A 8 N/A TRK

Track. The output follows the voltage applied at the TRK pin. See the

Operation

section for a more detailed description.

Theory of

N/A N/A 8 ADJ Adjust. A resistor divider from OUT to ADJ sets the output voltage.
EP EP EP EP

The exposed pad on the bottom of the SOIC package and the LFCSP package. EP

enhances thermal performance and is electrically connected to GND inside the

package. User is recommended to connect EP to the ground plane on the board.

Rev. 0 | Page 6 of 20

ADP1706/ADP1707/ADP1708

TYPICAL PERFORMANCE CHARACTERISTICS

VIN = 3.8 V, I

3.32

3.31

3.30

3.29

(V)

3.28

OUT

V

3.27

3.26

3.25

3.24

= 100 mA, CIN = 4.7 μF, C

OUT

I

= 100µA

LOAD

I

= 100mA

LOAD

I

= 300mA

LOAD

I

LOAD

–40 10 60 110

T

(°C)

J

= 4.7 μF, TA = 25°C, unless otherwise noted.

OUT

I

= 10mA

LOAD

I

= 500mA

LOAD

= 1A

Figure 10. Output Voltage vs. Junction Temperature

1400

1200

1000

800

(µA)

GND

600

I

400

I

= 10mA

200

06640-010

0
–40 10 60 110

LOAD

I

= 1A

LOAD

I

= 500mA

LOAD

I

= 300mA

LOAD

I

= 100mA

LOAD

I

= 100µA

LOAD

06640-013

T

(°C)

J

Figure 13. Ground Current vs. Junction Temperature

3.315

3.310

3.305

3.300

3.295

(V)

OUT

3.290

V

3.285

3.280

3.275

3.270

0.1 1000

1 10 100

I

(mA)

LOAD

Figure 11. Output Voltage vs. Load Current

3.32

I

= 100µA

3.31

3.30

3.29

(V)

OUT

V

3.28

3.27

LOAD

I

LOAD

I

LOAD

= 500mA

= 1A

I

LOAD

I

LOAD

I

LOAD

= 10mA

= 100mA

= 300mA

1400

1200

1000

800

(µA)

GND

600

I

400

200

06640-011

0

0.1 1000

110100

I

(mA)

LOAD

06640-014

Figure 14. Ground Current vs. Load Current

2100

I

= 1A

LOAD

(µA)

I

1800

1500

1200

GND

900

600

I

LOAD

= 500mA

I

LOAD

= 300mA

I

LOAD

= 100mA

I

LOAD

= 10mA

I

LOAD

= 100µA

3.26

3.25

3.8 4.2 4.6 5.0 5.4

V

(V)

IN

Figure 12. Output Voltage vs. Input Voltage

06640-012

Rev. 0 | Page 7 of 20

300

0

3.6 4. 0 4.4 4.8 5.2

V

(V)

IN

06640-015

Figure 15. Ground Current vs. Input Voltage

ADP1706/ADP1707/ADP1708

V

V

V
V

400

350

LOAD SWI TCHED FROM 50mA TO 950mA

300

AND BACK TO 50mA

250

(mV)

200

DROPOUT

150

V

100

50

0

10 1000

I

LOAD

100

(mA)

Figure 16. Dropout Voltage vs. Load Current

3.4

3.3

3.2

3.1

3.0

(V)

OUT

2.9

V

2.8

2.7

2.6

2.5

3.0 4.0

3.2 3.4 3.6 3.8

V

(V)

IN

I

LOAD

I

LOAD

I

LOAD

I

LOAD

I

LOAD

I

LOAD

= 10mA
= 100mA
= 300mA
= 500mA
= 750mA
= 1A

V

OUT

50mV/DI

VIN = 3.8V

= 1.6V

V

OUT

= 4.7µF

C

IN

= 4.7µF

C

06640-017

TIME (20µs/DIV)

OUT

06640-020

Figure 19. Load Transient Response, C

LOAD SWI TCHED FROM 50mA TO 950mA

AND BACK TO 50mA

V

OUT

50mV/DI

06640-018

TIME (20μs/DIV)

= 4.7 μF, C

IN

= 4.7 μF

OUT

VIN = 3.8V

= 1.6V

V

OUT

= 22μF

C

IN

= 22μF

C

OUT

06640-021

Figure 17. Output Voltage vs. Input Voltage (in Dropout)

2500

2000

1500

I

LOAD

I

LOAD

I

LOAD

I

LOAD

I

LOAD

I

LOAD

= 1A
= 750mA
= 500mA
= 300mA
= 100mA
= 10mA

Figure 20. Load Transient Response, C

2V/DI

VIN STEP FROM 4V TO 5V

= 22 μF, C

IN

= 22 μF

OUT

(µA)

GND

I

1000

V

OUT

TIME (100μ s/DIV)

Figure 21. Line Transient Response

V

OUT

C

IN

C

OUT

I

LOAD

= 3.3V

= 4.7μF

= 4.7μF

= 1A

06640-022

500

0

3.0 4.0

3.2 3.4 3.6 3.8

V

(V)

IN

Figure 18. Ground Current vs. Input Voltage (in Dropout)

20mV/DI

06640-019

Rev. 0 | Page 8 of 20

ADP1706/ADP1707/ADP1708

–

–

18

16

14

12

10

8

6

RAMP-UP TIME (ms)

4

2

0

02

5101520

(nF)

C

SS

Figure 22. Output Voltage Ramp-Up Time vs. Soft Start Capacitor Value

0

V

–10

–20

–30

RIPPLE

V

IN

V

OUT

C

OUT

= 5V

= 3.3V
= 4.7μF

= 50mV

I

LOAD

I

LOAD

I

LOAD

I

LOAD

I

LOAD

I

LOAD

= 300mA
= 200mA
= 100mA
= 10mA
= 1mA
= 100µA

–40

–50

PSRR (dB)

–60

–70

–80

–90

100 1k 10k 100k 1M

10 10M

FREQUENCY (Hz)

Figure 23. ADP1706 Power Supply Rejection Ratio vs. Frequency

40

V

= 2.4V

OUT

–45

V

OUT

PSRR (dB)

–50

06640-023

5

–55

2.7 3.2 3.7 4.2 4.7

Figu re 25. ADP1708 Power Supply Rejection Ratio vs. Input Voltage

35

V

= 50mV

RIPPLE

V

= 5V

IN

I

= 10mA

LOAD

C

= 4.7μF

OUT

FREQUENCY = 10kHz

–40

–45

PSRR (dB)

–50

06640-024

–55

0.8 4.3

1.3 1.8 2.3 2.8 3. 3 3. 8

Figu re 26. ADP1708 Power Supply Rejection Ratio vs. Output Voltage

= 1.6V

V

IN

V

OUT

V

RIPPLE

I

LOAD

C

OUT

FREQUENCY = 10kHz

V

= 0.8V

OUT

(V)

(V)

= 50mV
= 10mA
= 4.7μF

06640-026

06640-027

0

V

–10

–20

–30

RIPPLE

V

IN

V

OUT

C

OUT

= 5V

= 0.8V
= 4.7μF

= 50mV

I

LOAD

I

LOAD

I

LOAD

I

LOAD

I

LOAD

I

LOAD

= 300mA
= 200mA
= 100mA
= 10mA
= 1mA
= 100µA

–40

–50

PSRR (dB)

–60

–70

–80

–90

10 10M

100 1k 10k 100k 1M

FREQUENCY (Hz)

Figure 24. ADP1708 Power Supply Rejection Ratio vs. Frequency

06640-025

Rev. 0 | Page 9 of 20

ADP1706/ADP1707/ADP1708

V

V

V

V

THEORY OF OPERATION

The ADP1706/ADP1707/ADP1708 are low dropout linear
regulators that use an advanced, proprietary architecture to
provide high power supply rejection ratio (PSRR) and excellent
line and load transient response with a small 4.7 μF ceramic
output capacitor. All devices operate from a 2.5 V to 5.5 V input
rail and provide up to 1 A of output current. Supply current in
shutdown mode is typically 100 nA.

IN

OUT

SENSE

providing a smooth ramp-up to the nominal output voltage.
The soft start time is calculated by

T

SS

= V

REF × (CSS/ISS

) (1)

where:

T

is the soft start period.

SS

is the 0.8 V reference voltage.

V

REF

C

is the soft start capacitance from SS to GND.

SS

is the current sourced from SS (1.2 μA).

I

SS

When the ADP1706 is disabled (using EN), the soft start capacitor
is discharged to GND through an internal 100 Ω resistor.

CURRENT LIMI T

THERMAL PROTECT

SHUTDOWN

ADJ/
TRK/

EN

REFERENCE

GND

SOFT

START

SS

Figure 27. Internal Block Diagram

Internally, the ADP1706/ADP1707/ADP1708 consist of a
reference, an error amplifier, a feedback voltage divider, and a
PMOS pass transistor. Output current is delivered via the
PMOS pass device, which is controlled by the error amplifier.
The error amplifier compares the reference voltage with the
feedback voltage from the output and amplifies the difference. If
the feedback voltage is lower than the reference voltage, the gate
of the PMOS device is pulled lower, allowing more current
to pass and increasing the output voltage. If the feedback
voltage is higher than the reference voltage, the gate of the
PMOS device is pulled higher, allowing less current to pass
and decreasing the output voltage.

The ADP1706/ADP1707 are available in 16 fixed output voltage
options between 0.75 V and 3.3 V. The ADP1706 allows for
connection of an external soft start capacitor, which controls
the output voltage ramp during startup. The ADP1707 features
a TRK pin that allows the output voltage to follow the voltage at
this pin. The ADP1708 is available in an adjustable version with
an output voltage that can be set to between 0.8 V and 5.0 V by
an external voltage divider. All devices are controlled by an
enable pin (EN).

SOFT START FUNCTION (ADP1706)

For applications that require a controlled startup, the ADP1706
provides a programmable soft start function. The programma­ble soft start is useful for reducing inrush current upon startup
and for providing voltage sequencing. To implement a soft start,
connect a small ceramic capacitor from SS to GND. Upon
startup, a 1.2 μA current source charges this capacitor. The
ADP1706 start-up output voltage is limited by the voltage at SS,

Rev. 0 | Page 10 of 20

EN

2

2V/DI

06640-016

1

1V/DI

OUT

TIME (2ms/DIV)

VIN = 5V

= 3.3V

V

OUT

= 4.7μF

C

OUT

= 10nF

C

SS

I

LOAD

= 1A

06640-028

Figure 28. OUT Ramp-Up with External Soft Start Capacitor

The ADP1707 and ADP1708 have no pins for soft start;
therefore, the function is switched to an internal soft start
capacitor, which sets the soft start ramp-up period to approxi­mately 48 μs. Note that the ramp-up period is the time it takes
OUT to go from 0% to 90% of the nominal value and is
different from the start-up time in

Tabl e 1 , which is the time
between the rising edge of EN to OUT being at 90% of the
nominal value. For the worst-case output voltage of 5 V, using
the suggested 4.7 μF output capacitor, the resulting input
inrush current is approximately 490 mA, which is less than
the maximum 1 A load current.

EN

2

2V/DI

1

1V/DI

OUT

TIME (20µ s/DIV)

VIN = 5V

= 1.6V

V

OUT

= 4.7μF

C

OUT

I

LOAD

= 10mA

06640-029

Figure 29. OUT Ramp-Up with Internal Soft Start

ADP1706/ADP1707/ADP1708

V

ADJUSTABLE OUTPUT VOLTAGE (ADP1708)

The ADP1708 can have its output voltage set over a 0.8 V to

5.0 V range. The output voltage is set by connecting a resistive
voltage divider from OUT to ADJ. The output voltage is
calculated by

= 0.8 V (1 + R1/R2) (2)

V

OUT

where:

R1 is the resistor from OUT to ADJ.
R2 is the resistor from ADJ to GND.

The maximum bias current into ADJ is 100 nA, so for less
than 0.5% error due to the bias current, use values less than
60 kΩ for R2.

TRACK MODE (ADP1707)

The ADP1707 includes a tracking mode feature. As shown in
Figure 30, if the voltage applied at the TRK pin is less than the
nominal output voltage, OUT is equal to the voltage at TRK.
Otherwise, OUT regulates to its nominal output value.

4.0

3.5

3.0

2.5

(V)

2.0

OUT

V

1.5

1.0

0.5

0

05

0.5 1.0 1. 5 2.0 2.5 3.0 3.5 4. 0 4.5

(V)

V

TRK

Figure 30. ADP1707 Output Voltage vs. Tracking Voltage

For example, consider an ADP1707 with a nominal output
voltage of 3.3 V. If the voltage applied to its TRK pin is greater
than 3.3 V, OUT maintains a nominal output voltage of 3.3 V.
If the voltage applied to TRK is reduced below 3.3 V, OUT
tracks this voltage. OUT can track the TRK pin voltage from
the nominal value all the way down to 0 V. A voltage divider is
present from TRK to the error amplifier input with a divider
ratio equal to the divider from OUT to the error amplifier,
which sets the output voltage equal to the tracking voltage.
Both divider ratios are set by postpackage trim, depending on
the desired output voltage.

VIN = 3.8V
V

= 3.3V

OUT

I

= 10mA

LOAD

06640-030

.0

ENABLE FEATURE

The ADP1706/ADP1707/ADP1708 use the EN pin to enable
and disable the OUT pin under normal operating conditions.
As shown in
active threshold, OUT turns on. When a falling voltage on EN
crosses the inactive threshold, OUT turns off.

As shown in Figure 31, the EN pin has hysteresis built in. This
prevents on/off oscillations that can occur due to noise on the
EN pin as it passes through the threshold points.

The EN pin active/inactive thresholds are derived from the IN
voltage. Therefore, these thresholds vary when changing the
input voltage.
thresholds when the input voltage varies from 2.5 V to 5.5 V.

Figure 31, when a rising voltage on EN crosses the

EN

500mV/DI

OUT

VIN = 5V

= 1.6V

V

OUT

= 4.7μF

C

OUT

= 10mA

I

LOAD

TIME (10ms/ DIV)

Figure 31. ADP1706 Typical EN Pin Operation

Figure 32 shows typical EN active/inactive

1.4

1.3

1.2

1.1

1.0

0.9

0.8

0.7

TYPICAL EN THRESHOLDS (V)

0.6

0.5

2.50 5.50

2.75 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25

Figure 32. Typical EN Pin Thresholds vs. Input Voltage

EN ACTIVE

EN INACTIVE

HYSTERESIS

V

(V)

IN

06640-031

06640-032

Rev. 0 | Page 11 of 20

ADP1706/ADP1707/ADP1708

V

V

G

APPLICATION INFORMATION

CAPACITOR SELECTION

Output Capacitor

The ADP1706/ADP1707/ADP1708 are designed for operation
with small, space-saving ceramic capacitors, but they function
with most commonly used capacitors as long as care is taken with
the effective series resistance (ESR) value. The ESR of the output
capacitor affects stability of the LDO control loop. A minimum of

4.7 μF capacitance with an ESR of 500 mΩ or less is recommended
to ensure stability of the ADP1706/ADP1707/ADP1708. Transient
response to changes in load current is also affected by output
capacitance. Using a larger value of output capacitance improves
the transient response of the ADP1706/ADP1707/ADP1708 to
large changes in load current.
transient responses for output capacitance values of 4.7 μF and
22 μF, respectively.

V

RESPONSE TO LOAD STEP

OUT

FROM 50mA TO 950mA

50mV/DI

Figure 33. Output Transient Response, C

V

RESPONSE TO LOAD STEP

OUT

FROM 50mA TO 950mA

50mV/DI

Figure 34. Output Transient Response, C

Figure 33 and Figure 34 show the

VIN = 3.8V

= 1.6V

V

OUT

= 4.7μF

C

IN

= 4.7μF

C

OUT

TIME (2μs/DIV)

= 4.7 μF

OUT

VIN = 3.8V

= 1.6V

V

OUT

= 22μF

C

IN

= 22μF

C

OUT

TIME (2μs/DIV)

= 22 μF

OUT

06640-033

06640-034

Input Bypass Capacitor

Connecting a 4.7 μF capacitor from the IN pin to GND reduces
the circuit sensitivity to the printed circuit board (PCB) layout,
especially when long input traces, or high source impedance,
is encountered. If greater than 4.7 μF of output capacitance is
required, it is recommended that the input capacitor be increased
to match it.

Input and Output Capacitor Properties

Any good quality ceramic capacitors can be used with the
ADP1706/ADP1707/ADP1708, as long as they meet the
minimum capacitance and maximum ESR requirements.
Ceramic capacitors are manufactured with a variety of dielec­trics, each with different behavior over temperature and applied
voltage. Capacitors must have a dielectric adequate to ensure
the minimum capacitance over the necessary temperature range
and dc bias conditions. X5R or X7R dielectrics with a voltage
rating of 6.3 V or 10 V are recommended. Y5V and Z5U
dielectrics are not recommended, due to their poor temperature
and dc bias characteristics.

VOLTAGE TRACKING APPLICATIONS

RATIO VO LTAGE T RACKIN

ADP1706-2.5

IN

OUT

5V

EN

SS

GND

R1

R2

2.5V

ADP1707-1.2

OUT

TRK
IN
EN

GND

2.5V

V

OUT

1.2V

1.2V

I/O PO WER RAIL

RATIO
TRACKING

CORE RAIL

TIME

06640-042

Figure 35. Voltage Tracking Feature Using ADP1707

Figure 35 shows an application where the ADP1707 tracking
feature is used. An ADP1706 powers the I/O of a microproces­sor and an ADP1707 powers the core. At startup, the output of
the ADP1706 ramps to 2.5 V, which is divided down via a
voltage divider (R1 and R2) to a lower voltage at the TRK pin of
the ADP1707. The output of the ADP1707 thus follows the
TRK pin and ramps up steadily to 1.2 V. This implementation
ensures that the core of the processor powers up after the I/O.

CURRENT LIMIT AND THERMAL OVERLOAD PROTECTION

The ADP1706/ADP1707/ADP1708 are protected against
damage due to excessive power dissipation by current and
thermal overload protection circuits. The ADP1706/ADP1707/
ADP1708 are designed to reach current limit when the output
load reaches 1.5 A (typical). When the output load exceeds

1.5 A, the output voltage is reduced to maintain a constant
current limit.

Rev. 0 | Page 12 of 20

ADP1706/ADP1707/ADP1708

Thermal overload protection is included, which limits the
junction temperature to a maximum of 150°C (typical). Under
extreme conditions (that is, high ambient temperature and
power dissipation) when the junction temperature starts to
rise above 150°C, the output is turned off, reducing the output
current to zero. When the junction temperature drops below
135°C (typical), the output is turned on again and output
current is restored to its nominal value.

Consider the case where a hard short from OUT to ground
occurs. At first, the ADP1706/ADP1707/ADP1708 reach
current limit so that only 1.5 A is conducted into the short. If
self-heating of the junction becomes great enough to cause its
temperature to rise above 150°C, thermal shutdown activates,
turning off the output and reducing the output current to
zero. As the junction temperature cools and drops below
135°C, the output turns on and conducts 1.5 A into the short,
again causing the junction temperature to rise above 150°C.
This thermal oscillation between 135°C and 150°C causes a
current oscillation between 1.5 A and 0 A that continues as
long as the short remains at the output.

Current and thermal limit protections are intended to protect
the device against accidental overload conditions. For reliable
operation, device power dissipation should be externally limited
so junction temperatures do not exceed 125°C.

THERMAL CONSIDERATIONS

To guarantee reliable operation, the junction temperature of
the ADP1706/ADP1707/ADP1708 must not exceed 125°C. To
ensure that the junction temperature stays below this maximum
value, the user needs to be aware of the parameters that contrib­ute to junction temperature changes. These parameters include
ambient temperature, power dissipation in the power device,

values

JA

).

JA

and thermal resistance between the junction and ambient air (θ

value is dependent on the package assembly compounds

The θ

JA

used and the amount of copper to which the GND pins of the
package are soldered on the PCB. Table 5 shows typical θ
of the 8-lead SOIC and 8-lead LFCSP for various PCB copper sizes.

Table 5. Typical θ

Values

JA

Copper Size (mm2) θJA (°C/W), SOIC θJA (°C/W), LFCSP

01 57.6 65.9
50 53.1 62.3
100 52.3 61.2
300 51.3 59.7
500 51.3 59.4

1

Device soldered to minimum size pin traces.

The junction temperature of the ADP1706/ADP1707/ADP1708
can be calculated by

T

= TA + (PD × θJA) (3)

J

where:

T

is the ambient temperature.

A

is the power dissipation in the die, given by

P

D

= [(VIN – V

P

D

OUT

) × I

] + (VIN × I

LOAD

) (4)

GND

where:

I

is the load current.

LOAD

is the ground current.

I

GND

V

and V

IN

are the input and output voltages, respectively.

OUT

Power dissipation due to ground current is quite small and can
be ignored. Therefore, the junction temperature equation
simplifies to the following:

= TA + {[(VIN – V

T

J

OUT

) × I

] × θJA} (5)

LOAD

As shown in Equation 5, for a given ambient temperature,
input-to-output voltage differential, and continuous load
current, a minimum copper size requirement exists for the PCB
to ensure the junction temperature does not rise above 125°C.
Figure 36 to Figure 41 show junction temperature calculations

to V

for different ambient temperatures, load currents, V

IN

OUT

differentials, and areas of PCB copper.

140

MAX TJ (DO NOT OPERATE ABOVE THIS POINT)

120

100

80

(°C)

J

T

60

40

20

1mA
10mA

0

0.5 5.0

1.01.52.02.53.03.54.04.5

Figure 36. 500 mm

100mA
300mA

2

of PCB Copper, TA = 25°C, SOIC

500mA

(LOAD CURRENT)

750mA

V

– V

(V)

IN

OUT

1A

06640-035

Rev. 0 | Page 13 of 20

ADP1706/ADP1707/ADP1708

140

MAX TJ (DO NOT OPERATE ABOVE THIS POINT)

120

140

MAX TJ (DO NOT OPERATE ABOVE THIS POINT)

120

100

80

(°C)

J

T

60

40

20

1mA
10mA

0

0.5 5.0

1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

Figure 37. 100 mm

100mA
300mA

2

of PCB Copper, TA = 25°C, SOIC

500mA

(LOAD CURRENT)

750mA

V

– V

(V)

IN

OUT

1A

06640-036

140

MAX TJ (DO NOT OPERATE ABOVE THIS POINT)

120

100

80

(°C)

J

T

60

40

20

1mA
10mA

0

0.5 5.0

1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

Figure 38. 0 mm

140

100mA
300mA

2

of PCB Copper, TA = 25°C, SOIC

500mA
750mA

V

– V

(V)

IN

OUT

1A

(LOAD CURRENT)

06640-037

100

80

(°C)

J

T

60

40

20

1mA
10mA

0

0.5 5.0

1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

Figure 40. 100 mm

100mA
300mA

2

of PCB Copper, TA = 25°C, LFCSP

500mA
750mA

V

– V

(V)

IN

OUT

1A

(LOAD CURRENT)

06640-039

140

MAX TJ (DO NOT OPERATE ABOVE THIS POINT)

120

100

80

(°C)

J

T

60

40

20

1mA
10mA

0

0.5 5.0

1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

Figure 41. 0 mm

100mA
300mA

2

of PCB Copper, TA = 25°C, LFCSP

500mA
750mA

V

– V

(V)

IN

OUT

1A

(LOAD CURRENT)

06640-040

MAX TJ (DO NOT OPERATE ABOVE THIS POINT)

120

100

80

(°C)

J

T

60

40

20

1mA
10mA

0

0.5 5.0

1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

Figure 39. 500 mm

100mA
300mA

2

of PCB Copper, TA = 25°C, LFCSP

500mA
750mA

V

– V

(V)

IN

OUT

1A

(LOAD CURRENT)

06640-038

Rev. 0 | Page 14 of 20

ADP1706/ADP1707/ADP1708

PCB LAYOUT CONSIDERATIONS

Heat dissipation from the package can be improved by
increasing the amount of copper attached to the pins of the
ADP1706/ADP1707/ADP1708. However, as can be seen from
Tabl e 5 , a point of diminishing returns is eventually reached,
beyond which an increase in the copper size does not yield
significant heat dissipation benefits.

The ADP1706/ADP1707/ADP1708 feature an exposed pad on
the bottom of both the SOIC and LFCSP packages to improve
thermal performance. Because the exposed pad is electrically
connected to GND inside the package, it is recommended that
it also be connected to the ground plane on the PCB with a
sufficient amount of copper.

Here are a few general tips when designing PCBs:

• Place the input capacitor as close as possible to the IN and

GND pins.

• Place the output capacitor as close as possible to the OUT

and GND pins.

• For the ADP1706, place the soft start capacitor as close as

possible to the SS pin.

• Connect the load as close as possible to the OUT and

SENSE pins.

Use of 0402 or 0603 size capacitors and resistors achieves the
smallest possible footprint solution on boards where area is
limited.

ANALOG
DEVICES

ADP1706/ADP1707/ADP1708

GND GND

VIN VOUT

C1 C2

J1

Figure 42. Example PCB Layout

SOIC8

C3

U1

R1

R2

GNDGND EN ADJ/TRK/SS

06640-041

Rev. 0 | Page 15 of 20

ADP1706/ADP1707/ADP1708

OUTLINE DIMENSIONS

5.00 (0.197)

4.00 (0.157)

3.90 (0.154)

3.80 (0.150)

4.90 (0.193)

4.80 (0.189)

85

TOP VIEW

41

6.20 (0.244)

6.00 (0.236)

5.80 (0.228)

3.098 (0.122)

2.41 (0.095)

1.27 (0.05)
BSC

1.75 (0.069)

1.35 (0.053)

0.10 (0.004)
MAX

COPLANARITY

0.10

CONTROLL I NG DI M ENSIONS ARE IN MILL I M ET E R; I NCH DIM ENS I O NS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQ UIVALENTS FO R
REFERENCE ON LY AND ARE NO T APPROPRIATE FOR USE IN DESIGN.

0.51 (0.020)

0.31 (0.012)

COMPLIANT TO JEDEC STANDARDS MS-012-AA

1.65 (0.065)

1.25 (0.049)

SEATING
PLANE

BOTTOM VIEW

0.25 (0.0098)

0.17 (0.0067)

(PINS UP)

8°
0°

0.50 (0.020)

0.25 (0.010)

45°

1.27 (0.050)

0.40 (0.016)

060506-A

Figure 43. 8-Lead Standard Small Outline Package, with Expose Pad [SOIC_N_EP]

Narrow Body

(RD-8-2)

Dimensions shown in millimeters and (inches)

INDICATOR

0.90 MAX

0.85 NOM

SEATING

PLANE

PIN 1

3.25

3.00 SQ

12° MAX

2.75

TOP

VIEW

0.70 MAX

0.65TYP

0.30

0.23

0.18

2.95

2.75 SQ

2.55

0.05 MAX

0.01 NOM

0.20 REF

0.60 MAX

Figure 44. 8-Lead Frame Chip Scale Package [LFCSP_VD]

3 mm × 3 mm Body, Very Thin, Dual Lead

Dimensions shown in millimeters

0.50

0.40

0.30

(CP-8-2)

0.60 MAX

5

EXPOSED

PAD

(BOTT OM VIEW)

4

0.50
BSC

8

1.60

1.45

1.30

1

1.89

1.74

1.59

PIN 1
INDICATOR

61507-B

Rev. 0 | Page 16 of 20

ADP1706/ADP1707/ADP1708

ORDERING GUIDE

Model Temperature Range Output Voltage (V) Package Description Package Option Branding

ADP1706ARDZ-0.75R71–40°C to +125°C 0.75 8-Lead SOIC_N_EP RD-8-2
ADP1706ARDZ-0.8-R71–40°C to +125°C 0.8 8-Lead SOIC_N_EP RD-8-2
ADP1706ARDZ-0.85R71–40°C to +125°C 0.85 8-Lead SOIC_N_EP RD-8-2
ADP1706ARDZ-0.9-R71–40°C to +125°C 0.9 8-Lead SOIC_N_EP RD-8-2
ADP1706ARDZ-0.95R71–40°C to +125°C 0.95 8-Lead SOIC_N_EP RD-8-2
ADP1706ARDZ-1.0-R71–40°C to +125°C 1.0 8-Lead SOIC_N_EP RD-8-2
ADP1706ARDZ-1.05R71–40°C to +125°C 1.05 8-Lead SOIC_N_EP RD-8-2
ADP1706ARDZ-1.1-R71–40°C to +125°C 1.1 8-Lead SOIC_N_EP RD-8-2
ADP1706ARDZ-1.15R71–40°C to +125°C 1.15 8-Lead SOIC_N_EP RD-8-2
ADP1706ARDZ-1.2-R71–40°C to +125°C 1.2 8-Lead SOIC_N_EP RD-8-2
ADP1706ARDZ-1.3-R71–40°C to +125°C 1.3 8-Lead SOIC_N_EP RD-8-2
ADP1706ARDZ-1.5-R71–40°C to +125°C 1.5 8-Lead SOIC_N_EP RD-8-2
ADP1706ARDZ-1.8-R71–40°C to +125°C 1.8 8-Lead SOIC_N_EP RD-8-2
ADP1706ARDZ-2.5-R71–40°C to +125°C 2.5 8-Lead SOIC_N_EP RD-8-2
ADP1706ARDZ-3.0-R71–40°C to +125°C 3.0 8-Lead SOIC_N_EP RD-8-2
ADP1706ARDZ-3.3-R71–40°C to +125°C 3.3 8-Lead SOIC_N_EP RD-8-2
ADP1706ACPZ-0.75R71–40°C to +125°C 0.75 8-Lead LFCSP_VD CP-8-2 L62
ADP1706ACPZ-0.8-R7
ADP1706ACPZ-0.85R71–40°C to +125°C 0.85 8-Lead LFCSP_VD CP-8-2 L64
ADP1706ACPZ-0.9-R7
ADP1706ACPZ-0.95R71–40°C to +125°C 0.95 8-Lead LFCSP_VD CP-8-2 L68
ADP1706ACPZ-1.0-R7
ADP1706ACPZ-1.05R71–40°C to +125°C 1.05 8-Lead LFCSP_VD CP-8-2 L67
ADP1706ACPZ-1.1-R7
ADP1706ACPZ-1.15R71–40°C to +125°C 1.15 8-Lead LFCSP_VD CP-8-2 L69
ADP1706ACPZ-1.2-R7
ADP1706ACPZ-1.3-R7
ADP1706ACPZ-1.5-R7
ADP1706ACPZ-1.8-R7
ADP1706ACPZ-2.5-R7
ADP1706ACPZ-3.0-R7
ADP1706ACPZ-3.3-R7
ADP1707ARDZ-0.75R71–40°C to +125°C 0.75 8-Lead SOIC_N_EP RD-8-2
ADP1707ARDZ-0.8-R71–40°C to +125°C 0.8 8-Lead SOIC_N_EP RD-8-2
ADP1707ARDZ-0.85R71–40°C to +125°C 0.85 8-Lead SOIC_N_EP RD-8-2
ADP1707ARDZ-0.9-R71–40°C to +125°C 0.9 8-Lead SOIC_N_EP RD-8-2
ADP1707ARDZ-0.95R71–40°C to +125°C 0.95 8-Lead SOIC_N_EP RD-8-2
ADP1707ARDZ-1.0-R71–40°C to +125°C 1.0 8-Lead SOIC_N_EP RD-8-2
ADP1707ARDZ-1.05R71–40°C to +125°C 1.05 8-Lead SOIC_N_EP RD-8-2
ADP1707ARDZ-1.1-R71–40°C to +125°C 1.1 8-Lead SOIC_N_EP RD-8-2
ADP1707ARDZ-1.15R71–40°C to +125°C 1.15 8-Lead SOIC_N_EP RD-8-2
ADP1707ARDZ-1.2-R71–40°C to +125°C 1.2 8-Lead SOIC_N_EP RD-8-2
ADP1707ARDZ-1.3-R71–40°C to +125°C 1.3 8-Lead SOIC_N_EP RD-8-2
ADP1707ARDZ-1.5-R71–40°C to +125°C 1.5 8-Lead SOIC_N_EP RD-8-2
ADP1707ARDZ-1.8-R71–40°C to +125°C 1.8 8-Lead SOIC_N_EP RD-8-2
ADP1707ARDZ-2.5-R71–40°C to +125°C 2.5 8-Lead SOIC_N_EP RD-8-2
ADP1707ARDZ-3.0-R71–40°C to +125°C 3.0 8-Lead SOIC_N_EP RD-8-2
ADP1707ARDZ-3.3-R71–40°C to +125°C 3.3 8-Lead SOIC_N_EP RD-8-2

1

–40°C to +125°C 0.8 8-Lead LFCSP_VD CP-8-2 L63

1

–40°C to +125°C 0.9 8-Lead LFCSP_VD CP-8-2 L6J

1

–40°C to +125°C 1.0 8-Lead LFCSP_VD CP-8-2 L65

1

–40°C to +125°C 1.1 8-Lead LFCSP_VD CP-8-2 L66

1

–40°C to +125°C 1.2 8-Lead LFCSP_VD CP-8-2 L6A

1

–40°C to +125°C 1.3 8-Lead LFCSP_VD CP-8-2 L6C

1

–40°C to +125°C 1.5 8-Lead LFCSP_VD CP-8-2 L6D

1

–40°C to +125°C 1.8 8-Lead LFCSP_VD CP-8-2 L6H

1

–40°C to +125°C 2.5 8-Lead LFCSP_VD CP-8-2 L6E

1

–40°C to +125°C 3.0 8-Lead LFCSP_VD CP-8-2 L6F

1

–40°C to +125°C 3.3 8-Lead LFCSP_VD CP-8-2 L6G

Rev. 0 | Page 17 of 20

ADP1706/ADP1707/ADP1708

Model Temperature Range Output Voltage (V) Package Description Package Option Branding

ADP1707ACPZ-0.75R71–40°C to +125°C 0.75 8-Lead LFCSP_VD CP-8-2 L6P
ADP1707ACPZ-0.8-R71–40°C to +125°C 0.8 8-Lead LFCSP_VD CP-8-2 L6Q
ADP1707ACPZ-0.85R71–40°C to +125°C 0.85 8-Lead LFCSP_VD CP-8-2 L6R
ADP1707ACPZ-0.9-R71–40°C to +125°C 0.9 8-Lead LFCSP_VD CP-8-2 L6S
ADP1707ACPZ-0.95R71–40°C to +125°C 0.95 8-Lead LFCSP_VD CP-8-2 L6T
ADP1707ACPZ-1.0-R71–40°C to +125°C 1.0 8-Lead LFCSP_VD CP-8-2 L6U
ADP1707ACPZ-1.05R71–40°C to +125°C 1.05 8-Lead LFCSP_VD CP-8-2 L6V
ADP1707ACPZ-1.1-R71–40°C to +125°C 1.1 8-Lead LFCSP_VD CP-8-2 L6W
ADP1707ACPZ-1.15R71–40°C to +125°C 1.15 8-Lead LFCSP_VD CP-8-2 L6X
ADP1707ACPZ-1.2-R71–40°C to +125°C 1.2 8-Lead LFCSP_VD CP-8-2 L6Y
ADP1707ACPZ-1.3-R71–40°C to +125°C 1.3 8-Lead LFCSP_VD CP-8-2 L6Z
ADP1707ACPZ-1.5-R71–40°C to +125°C 1.5 8-Lead LFCSP_VD CP-8-2 L70
ADP1707ACPZ-1.8-R71–40°C to +125°C 1.8 8-Lead LFCSP_VD CP-8-2 L71
ADP1707ACPZ-2.5-R71–40°C to +125°C 2.5 8-Lead LFCSP_VD CP-8-2 L72
ADP1707ACPZ-3.0-R71–40°C to +125°C 3.0 8-Lead LFCSP_VD CP-8-2 L73
ADP1707ACPZ-3.3-R71–40°C to +125°C 3.3 8-Lead LFCSP_VD CP-8-2 L74
ADP1708ARDZ-R7
ADP1708ACPZ-R7
ADP1706-3.3-EVALZ
ADP1707-3.3-EVALZ
ADP1708-EVALZ

1

Z = RoHS Compliant Part.

1

1

1

–40°C to +125°C 0.8 to 5.0 8-Lead SOIC_N_EP RD-8-2
–40°C to +125°C 0.8 to 5.0 8-Lead LFCSP_VD CP-8-2 L7P

1

3.3 Evaluation Board

1

3.3 Evaluation Board
Adjustable, but set to 1.6 V Evaluation Board

Rev. 0 | Page 18 of 20

ADP1706/ADP1707/ADP1708

NOTES

Rev. 0 | Page 19 of 20

ADP1706/ADP1707/ADP1708

NOTES

©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06640-0-6/07(0)

Rev. 0 | Page 20 of 20