ANALOG DEVICES ADP151-EP Service Manual
CMOS Linear Regulator
ADP151-EP
Rev. 0
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Fax: 781.461.3113 ©2012 Analog Devices, Inc. All rights reserved.
1µF
1µF
V
OUT
= 3.3VV
IN
= 3.7V
VOUT
NC
VIN
GND
EN
OFF
ON
NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
1
2
3 4
5
10681-001
Enhanced Product
FEATURES
Ultralow noise: 9 µV rms
Input voltage range: 2.2 V to 5.5 V
Low quiescent current
I
= 10 µA with 0 load
GND
I
= 265 μA with 200 mA load
GND
Low shutdown current: <1 µA
Low dropout voltage: 150 mV at 200 mA load
Accuracy over line, load, and temperature: −2.5%/+3%
PSRR performance of 70 dB at 10 kHz
Current-limit and thermal overload protection
Internal pull-down resistor on EN input
5-lead TSOT package
Enhanced processing (EP) for −55°C to +125°C operation
APPLICATIONS
RF, VCO, and PLL power supplies
Portable and battery-powered equipment
Post dc-to-dc regulation
Portable medical devices
Aeronautic and military operating temperature environment
Ultralow Noise, 200 mA,
TYPICAL APPLICATION CIRCUIT
Figure 1. TSOT ADP151-EP with Fixed Output Voltage, 3.3 V
GENERAL DESCRIPTION
The ADP151-EP is an ultralow noise, low dropout linear
regulator that operates from 2.2 V to 5.5 V and provides up to
200 mA of output current. The low 150 mV dropout voltage at
200 mA load improves efficiency and allows operation over a
wide input voltage range.
Using an innovative circuit topology, the ADP151-EP achieves
ultralow noise performance without the necessity of a bypass
capacitor, making it ideal for noise-sensitive analog and RF
applications. The ADP151-EP also achieves ultralow noise
performance without compromising PSRR or transient line
and load performance. The low 265 μA of quiescent current
at 200 mA load makes the ADP151-EP suitable for battery-
operated portable equipment.
The ADP151-EP also includes an internal pull-down resistor
on the EN input.
The ADP151-EP is specifically designed for stable operation
with tiny 1 µF, ±30% ceramic input and output capacitors to
meet the requirements of high performance, space constrained
applications.
The ADP151-EP is capable of 16 fixed output voltage options,
ranging from 1.1 V to 3.3 V.
Short-circuit and thermal overload protection circuits prevent
damage in adverse conditions. The ADP151-EP is available in a
tiny 5-lead TSOT package.
Additional application and technical information can be found
in the ADP151 data sheet.
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
ADP151-EP Enhanced Product
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Typical Application Circuit ............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Input and Output Capacitor, Recommended Specifications .. 4
Absolute Maximum Ratings ............................................................ 5
Thermal Data ................................................................................ 5
REVISION HISTORY
7/12—Revision 0: Initial Version
Thermal Resistance .......................................................................5
ESD Caution...................................................................................5
Pin Configurations and Function Descriptions ............................6
Typical Performance Characteristics ..............................................7
Applications Information .............................................................. 11
Thermal Considerations ............................................................ 11
Printed Circuit Board Layout Considerations ............................ 13
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 14
Rev. 0 | Page 2 of 16
Enhanced Product ADP151-EP
GND
OUT
OUT
OUT
OUT
OUT
OUT
OUT
I
OUT
= 200 mA, TJ = −55°C to +125°C
350
μA
GND-SD
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
DROPOUT VOLTAGE2
V
DROPOUT
I
OUT
= 10 mA
10 mV
OUT
OUT
OUT
STA RT-UP
LIMIT
RISE
Input Voltage Falling
UVLO
FAL L
1.28
V
HYS
Thermal Shutdown Threshold
TSSD
TJ rising
150
°
NOISE
OUT
OUT
OUT
SPECIFICATIONS
VIN = (V
Table 1.
Parameter Symbol Conditions Min Typ Max Unit
INPUT VOLTAGE RANGE VIN TJ = −55°C to +125°C 2.2 5.5 V
OPERATING SUPPLY CURRENT I
I
I
I
I
I
I
+ 0.4 V) or 2.2 V, whichever is greater; EN = VIN, I
OUT
I
= 0 µA 10 µA
= 0 µA, TJ = −55°C to +125°C 20 µA
= 100 µA 20 µA
= 100 µA, TJ = −55°C to +125°C 40 µA
= 10 mA 60 µA
= 10 mA, TJ = −55°C to +125°C 90 µA
= 200 mA 265 μA
= 10 mA, CIN = C
OUT
= 1 µF, TA = 25°C, unless otherwise noted.
OUT
SHUTDOWN CURRENT I
EN = GND 0.2 µA
EN = GND, TJ = −55°C to +125°C 1.0 µA
OUTPUT VOLTAGE ACCURACY
V
V
V
100 µA < I
V
100 µA < I
I
= 10 mA −1 +1 %
TJ = −55°C to +125°C
< 1.8 V
< 200 mA, VIN = (V
+ 0.4 V) to 5.5 V −3 +3 %
≥ 1.8 V
< 200 mA, VIN = (V
+ 0.4 V) to 5.5 V −2.5 +3 %
REGULATION
Line Regulation ∆V
Load Regulation1 ∆V
I
I
V
I
I
I
I
I
START-UP TIME3 t
CURRENT-LIMIT THRESHOLD4 I
/∆VIN VIN = (V
/∆I
V
+ 0.4 V ) to 5.5 V, TJ = −55°C to +125°C −0.05 +0.05 %/V
< 1.8 V %/mA
= 100 µA to 200 mA 0.006 %/mA
= 100 µA to 200 mA, TJ = −55°C to +125°C 0.012 %/mA
≥ 1.8 V
= 100 µA to 200 mA 0.003 %/mA
= 100 µA to 200 mA, TJ = −55°C to +125°C 0.008 %/mA
= 10 mA, TJ = −55°C to +125°C 30 mV
= 200 mA 150 mV
= 200 mA, TJ = −55°C to +125°C 230 mV
VOUT = 3.3 V 180 µs
TJ = 0°C to +125°C 220 300 400 mA
UNDERVOLTAGE LOCKOUT TJ = −55°C to +125°C
Input Voltage Rising UVLO
1.96 V
Hysteresis UVLO
THERMAL SHUTDOWN
Thermal Shutdown Hysteresis TS
EN INPUT
EN Input Logic High VIH 2.2 V ≤ VIN ≤ 5.5 V 1.2 V
EN Input Logic Low VIL 2.2 V ≤ VIN ≤ 5.5 V 0.4 V
EN Input Pull-Down Resistance REN VIN = VEN = 5.5 V 2.6 MΩ
OUTPUT NOISE OUT
10 Hz to 100 kHz, VIN = 5 V, V
10 Hz to 100 kHz, VIN = 5 V, V
120 mV
15
SD-HYS
10 Hz to 100 kHz, VIN = 5 V, V
= 3.3 V 9 µV rms
= 2.5 V 9 µV rms
= 1.1 V 9 µV rms
Rev. 0 | Page 3 of 16
C
°C
ADP151-EP Enhanced Product
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
100 kHz, VIN = 4.3 V, V
OUT
= 3.3 V, I
OUT
= 10 mA
55 dB
OUT
OUT
OUT
OUT
MIN
ESR
Parameter Symbol Conditions Min Typ Max Unit
POWER SUPPLY REJECTION RATIO PSRR
VIN = V
100 kHz, VIN = 3.8 V, V
VIN = V
+ 0.5 V 10 kHz, VIN = 3.8 V, V
+ 1 V 10 kHz, VIN = 4.3 V, V
= 3.3 V, I
= 3.3 V, I
= 3.3 V, I
= 10 mA 70 dB
= 10 mA 55 dB
= 10 mA 70 dB
10 kHz, VIN = 2.2 V, V
100 kHz, VIN = 2.2 V, V
1
Based on an end-point calculation using 0.1 mA and 200 mA loads. See Figure 4 for typical load regulation performance for loads less than 1 mA.
2
Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output
voltages above 2.2 V.
3
Start-up time is defined as the time between the rising edge of EN and V
4
Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V (that is, 2.7 V).
being at 90% of its nominal value.
OUT
= 1.1 V, I
= 1.1 V, I
= 10 mA 70 dB
= 10 mA 55 dB
INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS
Table 2.
Parameter Symbol Conditions Min Typ Max Unit
Minimum Input and Output Capacitance1 C
Capacitor ESR R
1
The minimum input and output capacitance should be greater than 0.7 μF over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended;
Y5V and Z5U capacitors are not recommended for use with any LDO.
TA = −55°C to +125°C 0.7 µF
TA = −55°C to +125°C 0.001 0.2 Ω
Rev. 0 | Page 4 of 16
Enhanced Product ADP151-EP
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
VIN to GND −0.3 V to +6.5 V
VOUT to GND −0.3 V to VIN
EN to GND −0.3 V to +6.5 V
Storage Temperature Range −65°C to +150°C
Operating Junction Temperature Range −55°C to +125°C
Operating Ambient Temperature Range −55°C to +125°C
Soldering Conditions JEDEC J-STD-020
Stresses above those listed under absolute maximum ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination. The ADP151-EP can be damaged when the
junction temperature limits are exceeded. Monitoring ambient
temperature does not guarantee that T
temperature limits. In applications with high power dissipation
and poor thermal resistance, the maximum ambient
temperature may have to be derated.
In applications with moderate power dissipation and low PCB
thermal resistance, the maximum ambient temperature can
exceed the maximum limit as long as the junction temperature
is within specification limits. The junction temperature (T
the device is dependent on the ambient temperature (T
power dissipation of the device (P
thermal resistance of the package (θ
The maximum junction temperature (T
ambient temperature (T
) and power dissipation (PD) using the
A
formula
T
= TA + (PD × θJA)
J
The junction-to-ambient thermal resistance (θ
is based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent
on the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
is within the specified
J
) of
J
), the
A
), and the junction-to-ambient
D
).
JA
) is calculated from the
J
) of the package
JA
board design is required. The value of θ
on PCB material, layout, and environmental conditions. The
specified values of θ
are based on a 4-laye r, 4 in. × 3 in. circuit
JA
board. See JESD51-7 for detailed information on the board
construction.
Ψ
is the junction-to-board thermal characterization parameter
JB
with units of °C/W. Ψ
of the package is based on modeling and
JB
calculation using a 4-layer board. The JESD51-12, Guidelines for
Reporting and Using Electronic Package Thermal Information, states
that thermal characterization parameters are not the same as
thermal resistances. Ψ
measures the component power flowing
JB
through multiple thermal paths rather than a single path as in
thermal resistance, θ
. Therefore, ΨJB thermal paths include
JB
convection from the top of the package as well as radiation from
the package, factors that make Ψ
applications. Maximum junction temperature (T
from the board temperature (T
B
using the formula
T
= TB + (PD × ΨJB)
J
See JESD51-8 and JESD51-12 for more detailed information
about Ψ
.
JB
THERMAL RESISTANCE
θJA and ΨJB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type θJA ΨJB Unit
5-Lead TSOT 174 43 °C/W
ESD CAUTION
may vary, depending
JA
more useful in real-world
JB
) is calculated
J
) and power dissipation (PD)
Rev. 0 | Page 5 of 16
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