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ADP125
Service Manual
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ANALOG DEVICES ADP124, ADP125 Service Manual

Current, CMOS Linear Regulators
ADP124/ADP125
2
4
1
5
8
V
OUT
= 3.3V V
IN
= 5.5V
VOUT
VOUT VIN
VOUT SENSE
NC
GND
VIN
EN
C2 C1
ADP124
OFF
ON
7
3
6
08476-001
2
4
1
5
8
V
OUT
= 3.3V
V
IN
= 5.5V
VOUT
VOUT VIN
ADJ
NC
GND
VIN
EN
C2 R1
R2
C1
ADP125
7
3 6
08476-002
OFF
ON
Data Sheet

FEATURES

Input voltage supply range: 2.3 V to 5.5 V 500 mA maximum output current Fixed and adjustable output voltage versions 1% initial accuracy Up to 31 fixed-output voltage options available
from 1.75 V to 3.3 V Adjustable-output voltage range from 0.8 V to 5.0 V Very low dropout voltage: 130 mV Low quiescent current: 45 µA Low shutdown current: <1 µA Excellent PSRR performance: 60 dB at 100 kHz Excellent load/line transient response Optimized for small 1.0 μF ceramic capacitors Current limit and thermal overload protection Logic controlled enable Compact 8-lead exposed paddle MSOP and LFCSP packages

APPLICATIONS

Digital camera and audio devices Portable and battery-powered equipment Automatic meter reading (AMR) meters GPS and location management units Medical instrumentation Point of load power
5.5 V Input, 500 mA, Low Quiescent

TYPICAL APPLICATION CIRCUITS

Figure 1. ADP124 with Fixed Output Voltage
Figure 2. ADP 125 with Adjustable Output Voltage

GENERAL DESCRIPTION

The ADP124/ADP125 are low quiescent current, low dropout linear regulators. They are designed to operate from an input voltage between 2.3 V and 5.5 V and to provide up to 500 mA of output current. The low 130 mV dropout voltage at a 500 mA load improves efficiency and allows operation over a wide input voltage range.
The low 210 μA of quiescent current with a 500 mA load makes the ADP124/ADP125 ideal for battery-operated portable equipment.
The ADP124 is capable of 31 fixed-output voltages from 1.75 V to 3.3 V. The ADP125 is the adjustable version of the device and allows the output voltage to be set between 0.8 V and 5.0 V by an external voltage divider.
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or othe r rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
The ADP124/ADP125 are specifically designed for stable operation with tiny 1 µF ceramic input and output capacitors to meet the requirements of high performance, space constrained applications.
The ADP124/ADP125 have an internal soft start that gives a constant start-up time of 350 µs. Short-circuit protection and thermal overload protection circuits prevent damage in adverse conditions. The ADP124/ADP125 are available in 8-lead exposed paddle MSOP and LFCSP packages. When compared with the standard MSOP and LFCSP packages, the exposed paddle MSOP and LFCSP packages have lower thermal resistance (θ
). The lower thermal resistance package allows the ADP124/
JA
ADP125 to meet the needs of a variety of portable applications while minimizing the rise in junction temperature.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700
www.analog.com
ADP124/ADP125 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Typical Application Circuits ............................................................ 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Recommended Capacitor Specifications ................................... 4
Absolute Maximum Ratings ............................................................ 5
Thermal Data ................................................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution .................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6

REVISION HISTORY

6/12—Rev. B to Rev. C
Changes to Table 3 ............................................................................. 5
Updated Outline Dimensions ........................................................ 17
4/12—Rev. A to Rev. B
Updated Outline Dimensions ........................................................ 17
Changes to Ordering Guide ........................................................... 18
9/10—Rev. 0 to Rev. A
Added 8-Lead LFCSP Package ..................................... Throughout
Added Figure 4 and Figure 6 (Renumbered Sequentially) ......... 6
Changes to Thermal Conditions Section and Table 6 ............... 14
Added Table 7 .................................................................................. 14
Changes to Junction Temperature Calculations Section ........... 15
Added Figure 44 .............................................................................. 16
Updated Outline Dimensions ....................................................... 17
Changes to Ordering Guide .......................................................... 18
12/09—Revision 0: Initial Version
Typical Performance Characteristics ..............................................7
Theory of Operation ...................................................................... 11
Applications Information .............................................................. 12
Capacitor Selection .................................................................... 12
Undervoltage Lockout ............................................................... 13
Enable Feature ............................................................................ 13
Current Limit and Thermal Overload Protection ................. 14
Thermal Considerations ............................................................ 14
Junction Temperature Calculations ......................................... 15
Printed Circuit Board Layout Considerations........................ 16
Outline Dimensions ....................................................................... 17
Ordering Guide .......................................................................... 18
Rev. C | Page 2 of 20
Data Sheet ADP124/ADP125
GND
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
J
OUT
J
OUT
OUT
OUT
OUT
I
OUT
= 1 mA to 500 mA, TJ = −40°C to +125°C
0.001
%/mA
I-BIAS
DROPOUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
STA RT-UP
OUT
LIMIT
I-LEAKAGE
RISE
FAL L
HYS

SPECIFICATIONS

Unless otherwise noted, VIN = (V C
= 1.0 µF; TA = 25°C.
OUT
Table 1.
Parameter Symbol Test Conditions Min Typ Max Unit
INPUT VOLTAGE RANGE VIN 2.3 5.5 V OPERATING SUPPLY CURRENT1 I
I
I
I
I
I
I
I
SHUTDOWN CURRENT ISD EN = GND 0.1 µA
EN = GND, TJ = −40°C to +125°C 1 µA
OUTPUT VOLTAGE ACCURACY2 V
Fixed Output I
100 µA < I
Adjustable Output
I
100 µA < I
LINE REGULATION ∆V LOAD REGULATION3 ∆V
+ 0.5 V) or 2.3 V, whichever is greater; ADJ connected to VOUT; I
OUT
I
= 0 µA 45 µA = 0 µA, TJ = −40°C to +125°C 105 µA = 1 mA 60 µA = 1 mA, TJ = −40°C to +125°C 120 µA = 250 mA 160 µA = 250 mA, TJ = −40°C to +125°C 210 µA = 500 mA 210 µA = 500 mA, TJ = −40°C to +125°C 280 µA
= 10 mA −1 +1 %
< 500 mA, VIN = (V
T
OUT
= −40°C to +125°C
+ 0.5 V) to 5.5 V,
OUT
= 10 mA 0.495 0.500 0.505 V
< 500 mA, VIN = 2.3 V to 5.5 V,
T
= −40°C to +125°C
OUT
/∆VIN VIN = VIN = 2.3 V to 5.5 V, TJ = −40°C to +125°C −0.05 +0.05 %/V /∆I
I
= 1 mA to 500 mA 0.0005 %/mA
= 10 mA; CIN = 1.0 µF;
OUT
−2 +1.5 %
0.485 0.500 0.515 V
ADJ INPUT BIAS CURRENT ADJ DROPOUT VOLTAGE4 V
I
I
I
I
I
I
START-UP TIME5 t CURRENT LIMIT THRESHOLD6 I
2.3 V ≤ VIN ≤ 5.5 V, ADJ connected to VOUT 15 nA
= 10 mA, V
> 2.3 V 3 mV = 10 mA, TJ = −40°C to +125°C 5 mV = 250 mA, V
> 2.3 V
65 mV = 250 mA, TJ = −40°C to +125°C 120 mV = 500 mA, V
> 2.3V
130 mV = 500 mA, TJ = −40°C to +125°C 230 mV
V
= 3.0 V 350 µs
550 750 1000 mA
THERMAL SHUTDOWN
Thermal Shutdown Threshold TSSD TJ rising 150 Thermal Shutdown Hysteresis TS
15
SD-HYS
EN INPUT
EN Input Logic High VIH 2.3 V ≤ VIN ≤ 5.5 V 1.2 V EN Input Logic Low VIL 2.3 V ≤ VIN ≤ 5.5 V 0.4 V EN Input Leakage Current V
EN = VIN or GND 0.1 µA
EN = VIN or GND, TJ = −40°C to +125°C 1 µA
UNDERVOLTAGE LOCKOUT UVLO
Input Voltage Rising UVLO Input Voltage Falling UVLO Hysteresis UVLO
TJ = −40°C to +125°C 2.1 V
TJ = −40°C to +125°C 1.5 V
TA = 25°C 125 mV
°C °C
Rev. C | Page 3 of 20
ADP124/ADP125 Data Sheet
NOISE
OUT
OUT
OUT
OUT
10 Hz to 100 kHz, VIN = 5.5 V, V
OUT
= 4.2V
65 µV rms
IN
OUT
Capacitor ESR
R
ESR
TA = −40°C to +125°C
0.001
1 Ω
Parameter Symbol Test Conditions Min Typ Max Unit
OUTPUT NOISE OUT 10 Hz to 100 kHz, VIN = 5.5 V, V
10 Hz to 100 kHz, VIN = 5.5 V, V 10 Hz to 100 kHz, VIN = 5.5 V, V
10 Hz to 100 kHz, VIN = 5.5 V, V
= 1.2 V 25 µV rms = 1.8 V 35 µV rms = 2.5 V 45 µV rms = 3.3 V 55 µV rms
POWER SUPPLY REJECTION RATIO
(V
= V
+1V)
1
The current from the external resistor divider network in the case of adjustable voltage output (as with the ADP125) should be subtracted from the ground current measured.
2
Accuracy when VOUT is connected directly to ADJ. When VOUT voltage is set by external feedback resistors, absolute accuracy in adjust mode depends on the tolerances of
the resistors used.
3
Based on an endpoint calculation using 1 mA and 500 mA loads.
4
Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output voltages
greater than 2.3 V.
5
Start-up time is defined as the time between the rising edge of EN to VOUT being at 90% of its nominal value.
6
Current limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.3 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 3.3 V, or 2.97 V.
PSRR 10 kHz to 100 kHz, V
= 1.8 V, 2.5 V, 3.3 V 60 dB
OUT

RECOMMENDED CAPACITOR SPECIFICATIONS

Table 2.
Parameter Symbol Test Conditions Min Typ Max Unit
Minimum Input and Output
Capacitance
1
The minimum input and output capacitance should be greater than 0.70 µF over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended; Y5V and Z5U capacitors are not recommended for use with this LDO.
1
TA = −40°C to +125°C 0.70 µF
CAP
MIN
Rev. C | Page 4 of 20
Data Sheet ADP124/ADP125
ADJ to GND
−0.3 V to +6.5 V

ABSOLUTE MAXIMUM RATINGS

Table 3.
Parameter Rating
VIN to GND −0.3 V to +6.5 V
EN to GND −0.3 V to +6.5 V VOUT to GND −0.3 V to VIN Storage Temperature Range −65°C to +150°C Operating Ambient Temperature Range −40°C to +85°C Operating Junction Temperature Range −40°C to +125°C Soldering Conditions JEDEC J-STD-020
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL DATA

Absolute maximum ratings apply individually only, not in combination. The ADP124/ADP125 can be damaged when the junction temperature limits are exceeded. Monitoring ambient temperature does not guarantee that T specified temperature limits. In applications with high power dissipation and poor thermal resistance, the maximum ambient temperature may have to be limited.
In applications with moderate power dissipation and low PCB thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. The junction temperature (T the device is dependent on the ambient temperature (T power dissipation of the device (P thermal resistance of the package (θ
Maximum junction temperature (T ambient temperature (T
) and power dissipation (PD) using the
A
formula
T
= TA + (PD × θJA)
J
The junction-to-ambient thermal resistance (θ is based on modeling and calculation using a 4-layer board. The junction-to-ambient thermal resistance is highly dependent on the
will remain within the
J
J
), the
A
), and the junction-to-ambient
D
).
JA
) is calculated from the
J
) of the package
JA
) of
application and board layout. In applications in which high maxi­mum power dissipation exists, close attention to thermal board design is required. The value of θ
may vary, depending on PCB
JA
material, layout, and environmental conditions. The specified values of θ
are based on a 4-layer, 4 inch × 3 inch circuit board.
JA
Refer to JESD 51-7 for detailed information on the board construction.
Ψ
is the junction-to-board thermal characterization parameter
JB
and is measured in °C/ W. The Ψ
of the package is based on
JB
modeling and calculation using a 4-layer board. The Guidelines for Reporting and Using Package Thermal Information: JESD51-12 states that thermal characterization parameters are not the same as thermal resistances. Ψ
measures the component power flowing
JB
through multiple thermal paths rather than a single path as in thermal resistance, θ
. Therefore, ΨJB thermal paths include
JB
convection from the top of the package as well as radiation from the package—factors that make Ψ applications. Maximum junction temperature (T from the board temperature (T
more useful in real-world
JB
) is calculated
J
) and power dissipation (PD)
B
using the formula
T
= TB + (PD × ΨJB)
J
Refer to JESD51-8 and JESD51-12 for more detailed information about Ψ
.
JB

THERMAL RESISTANCE

θJA and ΨJB are specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type θJA ΨJB Unit
8-Lead MSOP 102.8 31.8 °C/W 8-Lead LFCSP 68.9 44.1 °C/W

ESD CAUTION

Rev. C | Page 5 of 20
ADP124/ADP125 Data Sheet
VOUT
1
VOUT
2
VOUT SENSE
3
GND
4
VIN
8
VIN
7
NC
6
EN
5
NOTES
1. NC = NO CONNEC T.
2. THE EXPOSED PAD MUST BE CONNECTED TO GROUND.
ADP124
TOP VIEW
(Not to Scale)
08476-003
TOP VIEW
(Not to Scale)
ADP124
3VOUT SENSE
4GND
1VOUT
2VOUT
6 NC 5 EN
8 VIN 7 VIN
08476-105
NOTES
1. NC = NO CONNEC T.
2. THE EXPOSED PAD MUST BE CONNECTED TO GROUND.
VOUT
1
VOUT
2
ADJ
3
GND
4
VIN
8
VIN
7
NC
6
EN
5
ADP125
TOP VIEW
(Not to Scale)
08476-004
NOTES
1. NC = NO CONNEC T.
2. THE EXPOSED PAD MUST BE CONNECTED TO GROUND.
TOP VIEW
(Not to Scale)
ADP125
3ADJ
4GND
1VOUT
2VOUT
6 NC 5 EN
8 VIN 7 VIN
08476-106
NOTES
1. NC = NO CONNEC T.
2. THE EXPOSED PAD MUST BE CONNECTED TO GROUND.

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 3. ADP124 Fixed Output MSOP Pin Configuration
Figure 4. ADP124 Fixed Output LFCSP Pin Configuration
Figure 5. ADP125 Adjustable Output MSOP Pin Configuration
Figure 6. ADP125 Adjustable Output LFCSP Pin Configuration
Table 5. Pin Function Descriptions
Mnemonic Pin No. ADP124 ADP125 Description
1 VOUT VOUT Regulated Output Voltage. Bypass VOUT to GND with a 1 µF or greater capacitor. 2 VOUT VOUT Regulated Output Voltage. Bypass VOUT to GND with a 1 µF or greater capacitor. 3 VOUT SENSE N/A Feedback Node for the Error Amplifier. Connect to VOUT. N/A ADJ Feedback Node for the Error Amplifier. Connect the midpoint of an external divider from VOUT to GND
to this pin to set the output voltage. 4 GND GND Ground. 5 EN EN Enable Input. Drive EN high to turn on the regulator; drive EN low to turn off the regulator. For
automatic startup, connect EN to VIN. 6 NC NC No Connect. This pin is not connected internally. 7 VIN VIN Regulator Input Supply. Bypass VIN to GND with a 1 µF or greater capacitor. 8 VIN VIN Regulator Input Supply. Bypass VIN to GND with a 1 µF or greater capacitor. EPAD EPAD The exposed pad must be connected to ground.
Rev. C | Page 6 of 20
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