ANALOG DEVICES ADP121 Service Manual
150 mA, Low Quiescent Current,
V
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FEATURES
Input voltage range: 2.3 V to 5.5 V
Output voltage range: 1.2 V to 3.3 V
Output current: 150 mA
Low quiescent current
I
= 11 µA with 0 A load
GND
I
= 30 µA with 150 mA load
GND
Low shutdown current: <1 µA
Low dropout voltage
90 mV @ 150 mA load
High PSRR
70 dB @ 1 kHz at V
70 dB @ 10 kHz at V
Low noise: 40 µV rms at V
No noise bypass capacitor required
Output voltage accuracy: ±1%
Stable with a small 1 µF ceramic output capacitor
16 fixed output voltage options
Current limit and thermal overload protection
Logic controlled enable
5-lead TSOT package
4-ball 0.4 mm pitch WLCSP
= 1.2 V
OUT
OUT
= 1.2 V
= 1.2 V
OUT
CMOS Linear Regulator
ADP121
TYPICAL APPLICATION CIRCUITS
= 1.8VVIN = 2.3V
V
OUT
VOUT
NC
5
1µF
4
06901-001
V
= 1.8V
OUT
1µF
06901-002
1
1µF
Figure 1. ADP121 TSOT with Fixed Output Voltage, 1.8 V
VIN
2
GND
3
EN
NC = NO CONNECT
= 2.3V
IN
1µF
Figure 2. ADP121 WLCSP with Fixed Output Voltage, 1.8 V
VIN VOUT
EN GND
APPLICATIONS
Mobile phones
Digital cameras and audio devices
Portable and battery-powered equipment
Post dc-to-dc regulation
Post regulation
GENERAL DESCRIPTION
The ADP121 is a quiescent current, low dropout, linear regulators
that operate from 2.3 V to 5.5 V and provide up to 150 mA of
output current. The low 135 mV dropout voltage at 150 mA
load improves efficiency and allows operation over a wide
input voltage range. The low 30 A of quiescent current at full
load make the ADP121 ideal for battery-operated portable
equipment.
The ADP121 is available in 16 fixed output voltage options
ranging from 1.2 V to 3.3 V. The parts are optimized for stable
operation with small 1 µF ceramic output capacitors. The
ADP121 delivers good transient performance with minimal
board area.
Short-circuit protection and thermal overload protection circuits
prevent damage in adverse conditions. The ADP121 is available
in a tiny 5-lead TSOT and 4-ball 0.4 mm pitch WLCSP packages and utilizes the smallest footprint solution to meet a
variety of portable applications.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved.
ADP121
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TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Typical Application Circuits ............................................................ 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
Thermal Data ................................................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution .................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
REVISION HISTORY
7/08—Revision 0: Initial Version
Typical Performance Characteristics ..............................................7
Theory of Operation ...................................................................... 11
Applications Information .............................................................. 12
Capacitor Selection .................................................................... 12
Undervoltage Lockout ............................................................... 13
Enable Feature ............................................................................ 13
Current Limit and Thermal Overload Protection ................. 14
Thermal Considerations ............................................................ 14
Printed Circuit Board Layout Considerations ....................... 17
Outline Dimensions ....................................................................... 18
Ordering Guide .......................................................................... 19
Rev. 0 | Page 2 of 20
ADP121
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SPECIFICATIONS
VIN = (V
Table 1.
Parameter Symbol Conditions Min Typ Max Unit
INPUT VOLTAGE RANGE VIN T
OPERATING SUPPLY CURRENT I
I
I
I
I
I
SHUTDOWN CURRENT I
EN = GND, TJ = −40°C to +125°C 1.5 µA
FIXED OUTPUT VOLTAGE ACCURACY V
REGULATION
Line Regulation V
Load Regulation
DROPOUT VOLTAGE
TSOT I
I
I
I
WLCSP I
I
I
I
START-UP TIME
CURRENT-LIMIT THRESHOLD
THERMAL SHUTDOWN
Thermal Shutdown Threshold TSSD T
Thermal Shutdown Hysteresis TS
EN INPUT
EN Input Logic High VIH 2.3 V ≤ VIN ≤ 5.5 V 1.2 V
EN Input Logic Low VIL 2.3 V ≤ VIN ≤ 5.5 V 0.4 V
EN Input Leakage Current V
EN = VIN or GND, TJ = −40°C to +125°C 1
UNDERVOLTAGE LOCKOUT UVLO
Input Voltage Rising UVLO
Input Voltage Falling UVLO
Hysteresis UVLO
OUTPUT NOISE OUT
10 Hz to 100 kHz, VIN = 5 V, V
10 Hz to 100 kHz, VIN = 5 V, V
+ 0.5 V) or 2.3 V, whichever is greater; EN = VIN; I
OUT
I
GND
EN = GND 0.1 µA
GND-SD
I
OUT
/VIN
OUT
1
2
V
3
T
4
I
V
/I
OUT
OUT
V
DROPOUT
V
START-UP
160 225 350 mA
LIMIT
15 °C
SD-HYS
EN = VIN or GND 0.05 µA
I-LEAKAGE
2.25 V
RISE
FAL L
120 mV
HYS
10 Hz to 100 kHz, VIN = 5 V, V
NOISE
= 10 mA; CIN = C
OUT
= −40°C to +125°C 2.3
J
= 0 µA 11 µA
OUT
= 0 µA, TJ = −40°C to +125°C 21 µA
OUT
= 10 mA 15 µA
OUT
= 10 mA, TJ = −40°C to +125°C 29 µA
OUT
= 150 mA 30 µA
OUT
= 150 mA, TJ = −40°C to +125°C 40 µA
OUT
= 10 mA −1 +1 %
OUT
100 µA < I
V
= (V
IN
100 µA < I
= (V
V
IN
T
= −40°C to +125°C
J
= (V
V
IN
= −40°C to +125°C
T
J
I
= 1 mA to 150 mA 0.001 %/mA
OUT
= 1 mA to 150 mA
I
OUT
T
= −40°C to +125°C
J
= 3.3 V
OUT
= 10 mA 8 mV
OUT
= 10 mA, TJ = −40°C to +125°C 12 mV
OUT
= 150 mA 120 mV
OUT
= 150 mA, TJ = −40°C to +125°C 180 mV
OUT
= 10 mA 6 mV
OUT
= 10 mA, TJ = −40°C to +125°C 9 mV
OUT
= 150 mA 90 mV
OUT
= 150 mA, TJ = −40°C to +125°C 135 mV
OUT
= 3.3 V 120 µs
OUT
rising 150 °C
J
< 150 mA,
OUT
+ 0.5 V) to 5.5 V
OUT
< 150 mA,
OUT
+ 0.5 V) to 5.5 V
OUT
+ 0.5 V) to 5.5 V, I
OUT
= 1 µF; TA = 25°C, unless otherwise noted.
OUT
5.5 V
−2 +2 %
−3 +3 %
= 1 mA
OUT
−0.03 +0.03 %/ V
0.005 %/mA
1.5 V
= 3.3 V 65 µV rms
OUT
= 2.5 V 52 µV rms
OUT
= 1.2 V 40 µV rms
OUT
Rev. 0 | Page 3 of 20
ADP121
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Parameter Symbol Conditions Min Typ Max Unit
POWER SUPPLY REJECTION RATIO PSRR 10 kHz, VIN = 5 V, V
10 kHz, VIN = 5 V, V
10 kHz, VIN = 5 V, V
INPUT AND OUTPUT CAPACITOR
Minimum Input and Output Capacitance CAP
Capacitor ESR R
1
Based on an end-point calculation using 1 mA and 100 mA loads. See for typical load regulation performance for loads less than 1 mA. Figure 6
2
Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output
voltages above 2.3 V.
3
Start-up time is defined as the time between the rising edge of EN to VOUT being at 90% of its nominal value.
4
Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V.
5
The minimum input and output capacitance should be greater than 0.70 F over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended;
Y5V and Z5U capacitors are not recommended for use with any LDO.
5
TJ = −40°C to +125°C 0.70 µF
MIN
T
ESR
= −40°C to +125°C 0.001 1 Ω
J
= 3.3 V 60 dB
OUT
= 2.5 V 66 dB
OUT
= 1.2 V 70 dB
OUT
Rev. 0 | Page 4 of 20
ADP121
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ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
VIN to GND −0.3 V to +6 V
VOUT to GND −0.3 V to VIN
EN to GND −0.3 V to +6 V
Storage Temperature Range −65°C to +150°C
Operating Junction Temperature Range −40°C to +125°C
Soldering Conditions JEDEC J-STD-020
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination. The ADP121 can be damaged when the junction
temperature limits are exceeded. Monitoring the ambient
temperature does not guarantee that T
temperature limits. In applications with high power dissipation
and poor thermal resistance, the maximum ambient temperature
may have to be derated. In applications with moderate power
dissipation and low PCB thermal resistance, the maximum
ambient temperature can exceed the maximum limit as long
as the junction temperature is within specification limits. The
junction temperature (T
ambient temperature (T
(P
), and the junction-to-ambient thermal resistance of the
D
package (θ
T
and PD using the following formula:
A
). TJ is calculated from
JA
= TA + (PD × θJA)
T
J
) of the device is dependent on the
J
), the power dissipation of the device
A
Junction-to-ambient thermal resistance, θ
modeling and calculation using a four-layer board. The
junction-to-ambient thermal resistance is highly dependent
on the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θ
is within the specified
J
, is based on
JA
may vary, depending
JA
on PCB material, layout, and environmental conditions. The
specified values of θ
are based on a 4-layer, 4” × 3”, circuit
JA
board. Refer to JESD 51-7 and JESD 51-9 for detailed
information on the board construction. For additional
information, see AN-617 Application Note, MicroCSP
TM
Wafer
Level Chip Scale Package.
Ψ
is the junction-to-board thermal characterization parameter
JB
measured in °C/W. Ψ
is based on modeling and calculation
JB
using a four-layer board. The JESD51-12 Guidelines for Reporting
and Using Package Thermal Information states that thermal
characterization parameters are not the same as thermal
resistances. Ψ
measures the component power flowing
JB
through multiple thermal paths rather than a single path as in
thermal resistance, θ
. Therefore, ΨJB thermal paths include
JB
convection from the top of the package as well as radiation
from the package, factors that make Ψ
world applications. Maximum T
temperature (T
= TB + (PD × ΨJB)
T
J
) and PD using the following formula:
B
more useful in real-
JB
is calculated from the board
J
Refer to JESD51-8 and JESD51-12 for more detailed
information about Ψ
.
JB
THERMAL RESISTANCE
θJA and ΨJB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
Table 3.
Package Type θJA ΨJB Unit
5-Lead TSOT 170 43 °C/W
4-Ball 0.4 mm Pitch WLCSP 260 58 °C/W
ESD CAUTION
Rev. 0 | Page 5 of 20
ADP121
A
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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
12
1
VIN
TOP VIEW
2
GND
(Not to Scale)
3
EN
NC = NO CONNECT
Figure 3. 5-Lead TSOT Pin Configuration Figure 4. 4-Ball WLCSP Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
TSOT WLCSP
Mnemonic Description
1 A1 VIN Regulator Input Supply. Bypass VIN to GND with a 1 µF or larger capacitor.
2 B2 GND Ground.
3 B1 EN
Enable Input. Drive EN high to turn on the regulator; drive EN low to turn off the regulator. For automatic
startup, connect EN to VIN.
4 N/A NC No Connect. Not connected internally.
5 A2 VOUT Regulated Output Voltage. Bypass VOUT to GND with a 1 µF or greater capacitor.
5
4
VOUT
NC
VIN VOUT
TOP VIEW
(Not to Scale)
EN GND
B
06901-003
06901-004
Rev. 0 | Page 6 of 20
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