ANALOG DEVICES ADP120 Service Manual
100 mA, Low Quiescent Current,
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FEATURES
Input voltage range: 2.3 V to 5.5 V
Output voltage range: 1.2 V to 3.3 V
Output current: 100 mA
Low quiescent current
I
= 11 μA with zero load
GND
I
= 22 μA with 100 mA load
GND
Low shutdown current: <1 μA
Low dropout voltage
60 mV @ 100 mA load
High PSRR
73 dB @ 1 kHz at V
70 dB @ 10 kHz at V
Low noise: 40 μV rms at V
No noise bypass capacitor required
Initial accuracy: ±1%
Stable with small 1 μF ceramic output capacitor
16 fixed output voltage options
Current-limit and thermal overload protection
Logic controlled enable
5-lead TSOT package
4-ball 0.4 mm pitch WLCSP
= 1.2 V
OUT
OUT
= 1.2 V
= 1.2 V
OUT
CMOS Linear Regulator
ADP120
TYPICAL APPLICATIONS CIRCUITS
NC
V
= 1.8V
OUT
5
+
1µF
4
07589-001
V
= 1.8V
OUT
+
1µF
07589-002
V
= 2.3V
IN
Figure 1. ADP120 TSOT with Fixed Output Voltage, 1.8 V
V
= 2.3V
IN
+
1µF
Figure 2. ADP120 WLCSP with Fixed Output Voltage, 1.8 V
+
1µF
1
2
3
NC = NO CONNECT
VIN VOUT
EN GND
VIN
GND
EN
VOUT
APPLICATIONS
Mobile phones
Digital camera and audio devices
Portable and battery-powered equipment
Post regulation
GENERAL DESCRIPTION
The ADP120 is a low quiescent current, low dropout, linear
regulator that operates from 2.3 V to 5.5 V and provides up to
100 mA of output current. The low 60 mV dropout voltage at
100 mA load improves efficiency and allows operation over a
wide input voltage range. The low 25 A of quiescent current at
full load makes the ADP120 ideal for battery-operated portable
equipment.
The ADP120 is available in 16 fixed output voltage options,
ranging from 1.2 V to 3.3 V. The part is optimized for stable
operation with small 1 µF ceramic output capacitors. The
ADP120 delivers good transient performance with minimal
board area.
Short-circuit protection and thermal overload protection circuits
prevent damage in adverse conditions. The ADP120 is available
in a tiny 5-lead TSOT and a 4-ball 0.4 mm pitch WLCSP for the
smallest footprint solution for use in a variety of portable
applications.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved.
ADP120
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TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Typical Application Circuits ............................................................ 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Recommended Specifications: Input and Output Capacitors 4
Absolute Maximum Ratings ............................................................ 5
Thermal Data ................................................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution .................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
REVISION HISTORY
7/08—Rev. 0 to Rev. A
Deleted ADP120-1.............................................................. Universal
Changes to General Description .................................................... 1
Changes to Dropout Voltage Parameter, Table 1 .......................... 3
Changes to Thermal Data Section .................................................. 5
Changes to Figure 12 and Figure 14 ............................................... 8
Changes to Figure 22 ........................................................................ 9
Changes to Table 6 and Table 7 ..................................................... 14
Changes to Figure 46 and Figure 47 Captions ............................ 17
Changes to Ordering Guide .......................................................... 18
6/08—Revision 0: Initial Version
Typical Performance Characteristics ..............................................7
Theory of Operation ...................................................................... 11
Applications Information .............................................................. 12
Capacitor Selection .................................................................... 12
Undervoltage Lockout ............................................................... 13
Enable Feature ............................................................................ 13
Current Limit and Thermal Overload Protection ................. 14
Thermal Considerations ............................................................ 14
PCB Layout Considerations ...................................................... 17
Outline Dimensions ....................................................................... 18
Ordering Guide .......................................................................... 19
Rev. A | Page 2 of 20
ADP120
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SPECIFICATIONS
VIN = (V
Table 1.
Parameter Symbol Conditions Min Typ Max Unit
INPUT VOLTAGE RANGE VIN T
OPERATING SUPPLY CURRENT I
I
I
I
I
I
SHUTDOWN CURRENT I
EN = GND, TJ = −40°C to +125°C 1.5 µA
FIXED OUTPUT VOLTAGE ACCURACY V
100 µA < I
REGULATION
Line Regulation V
Load Regulation
I
DROPOUT VOLTAGE
TSOT I
I
I
I
WLCSP I
I
I
I
START-UP TIME
CURRENT LIMIT THRESHOLD
THERMAL SHUTDOWN
Thermal Shutdown Threshold TSSD T
Thermal Shutdown Hysteresis TS
EN INPUT
EN Input Logic High VIH 2.3 V ≤ VIN ≤ 5.5 V 1.2 V
EN Input Logic Low VIL 2.3 V ≤ VIN ≤ 5.5 V 0.4 V
EN Input Leakage Current V
EN = VIN or GND, TJ = −40°C to +125°C 1 µA
UNDERVOLTAGE LOCKOUT UVLO
Input Voltage Rising UVLO
Input Voltage Falling UVLO
Hysteresis UVLO
OUTPUT NOISE OUT
10 Hz to 100 kHz, VIN = 5 V, V
10 Hz to 100 kHz, VIN = 5 V, V
+ 0.4 V) or 2.3 V, whichever is greater; EN = VIN, I
OUT
= −40°C to +125°C 2.3 5.5 V
J
I
GND
EN = GND 0.1 µA
GND-SD
I
OUT
= 0 µA 11 µA
OUT
= 0 µA, TJ = −40°C to +125°C 21 µA
OUT
= 10 mA 15 µA
OUT
= 10 mA, TJ = −40°C to +125°C 29 µA
OUT
= 100 mA 22 µA
OUT
= 100 mA, TJ = −40°C to +125°C 35 µA
OUT
= 10 mA −1 +1 %
OUT
100 µA < I
= −40°C to +125°C
T
J
1
2
V
3
t
4
I
/VIN
OUT
V
/I
OUT
OUT
V
DROPOUT
V
START-UP
110 180 350 mA
LIMIT
15 °C
SD-HYS
EN = VIN or GND 0.05 µA
I-LEAKAGE
TJ = −40°C to +125°C 2.25 V
RISE
FAL L
120 mV
HYS
10 Hz to 100 kHz, VIN = 5 V, V
NOISE
= (V
V
IN
= −40°C to +125°C
T
J
I
= 1 mA to 100 mA 0.001 %/mA
OUT
= 1 mA to 100 mA, TJ = −40°C to +125°C 0.005 %/mA
OUT
OUT
= 10 mA 8 mV
OUT
= 10 mA, TJ = −40°C to +125°C 12 mV
OUT
= 100 mA 80 mV
OUT
= 100 mA, TJ = −40°C to +125°C 120 mV
OUT
= 10 mA 6 mV
OUT
= 10 mA, TJ = −40°C to +125°C 9 mV
OUT
= 100 mA 60 mV
OUT
= 100 mA, TJ = −40°C to +125°C 90 mV
OUT
OUT
rising 150 °C
J
TJ = −40°C to +125°C 1.5 V
= 10 mA, CIN = C
OUT
< 100 mA, VIN = (V
OUT
< 100 mA, VIN = (V
OUT
+ 0.4 V) to 5.5 V, I
OUT
OUT
= 1 µF, TA = 25°C, unless otherwise noted.
OUT
+ 0.4 V) to 5.5 V −2 +2 %
OUT
+ 0.4 V) to 5.5 V,
OUT
= 1 mA,
−2.5 +2.5 %
−0.03 +0.03 %/ V
= 3.3 V
= 3.3 V 120 µs
= 3.3 V 65 µV rms
OUT
= 2.5 V 52 µV rms
OUT
= 1.2 V 40 µV rms
OUT
Rev. A | Page 3 of 20
ADP120
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Parameter Symbol Conditions Min Typ Max Unit
POWER SUPPLY REJECTION RATIO PSRR 10 kHz, VIN = 5 V, V
10 kHz, VIN = 5 V, V
10 kHz, VIN = 5 V, V
1
Based on an endpoint calculation using 1 mA and 100 mA loads. See Figure 6 for typical load regulation performance for loads less than 1 mA.
2
Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output
voltages above 2.3 V.
3
Start-up time is defined as the time between the rising edge of EN to V
4
Current limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V.
being at 90% of its nominal value.
OUT
RECOMMENDED SPECIFICATIONS: INPUT AND OUTPUT CAPACITORS
Table 2.
Parameter Symbol Conditions Min Typ Max Unit
MINIMUM INPUT AND OUTPUT CAPACITANCE1 C
CAPACITOR ESR R
1
The minimum input and output capacitance should be greater than 0.70 F over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R- and X5R-type capacitors are recommended,
Y5V and Z5U capacitors are not recommended for use with any LDO.
MIN
ESR
= 3.3 V 60 dB
OUT
= 2.5 V 66 dB
OUT
= 1.2 V 70 dB
OUT
TJ = −40°C to +125°C 0.70 µF
T
= −40°C to +125°C 0.001 1 Ω
J
Rev. A | Page 4 of 20
ADP120
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ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
VIN to GND Pins −0.3 V to +6 V
VOUT to GND Pins −0.3 V to VIN
EN to GND Pins −0.3 V to +6 V
Storage Temperature Range −65°C to +150°C
Operating Junction Temperature Range −40°C to +125°C
Soldering Conditions JEDEC J-STD-020
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination. The ADP120 can be damaged when the junction
temperature limits are exceeded. Monitoring ambient temperature
does not guarantee that T
limits. In applications with high power dissipation and poor
thermal resistance, the maximum ambient temperature may
have to be derated.
In applications with moderate power dissipation and low PCB
thermal resistance, the maximum ambient temperature can
exceed the maximum limit as long as the junction temperature
is within specification limits. The junction temperature (T
the device is dependent on the ambient temperature (T
power dissipation of the device (P
thermal resistance of the package (θ
Maximum junction temperature (T
ambient temperature (T
formula
T
= TA + (PD × θJA)
J
is within the specified temperature
J
) of
J
), the
A
), and the junction-to-ambient
D
).
JA
) is calculated from the
J
) and power dissipation (PD) using the
A
Junction-to-ambient thermal resistance (θ
based on modeling and calculation using a four-layer board.
The junction-to-ambient thermal resistance is highly dependent
on the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θ
PCB material, layout, and environmental conditions. The specified values of θ
Refer to JESD 51-7 and JESD 51-9 for detailed information
regarding board construction. For additional information, see
Application Note AN-617, MicroCSP
Package.
Ψ
is the junction-to-board thermal characterization parameter
JB
with units of °C/W. Ψ
calculation using a four-layer board. JESD51-12, Guidelines for
Reporting and Using Package Thermal Information, states that
thermal characterization parameters are not the same as
thermal resistances. Ψ
through multiple thermal paths rather than a single path as in
thermal resistance, θ
convection from the top of the package as well as radiation from
the package, factors that make Ψ
applications. Maximum junction temperature (T
from the board temperature (T
using the formula
T
= TB + (PD × ΨJB)
J
Refer to JESD51-8, JESD51-9, and JESD51-12 for more detailed
information about Ψ
THERMAL RESISTANCE
θJA and ΨJB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type θJA ΨJB Unit
5-Lead TSOT 170 43 °C/W
4-Ball, 0.4 mm Pitch WLCSP 260 58 °C/W
are based on a four-layer, 4 in. × 3 in. PCB.
JA
of the package is based on modeling and
JB
measures the component power flowing
JB
. Therefore, ΨJB thermal paths include
JB
more useful in real-world
JB
) and power dissipation (PD)
B
.
JB
) of the package is
JA
may vary, depending on
JA
TM
Wafer Le v el Chip S cal e
) is calculated
J
Rev. A | Page 5 of 20
ESD CAUTION
ADP120
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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
VIN
2
GND
Figure 3. 5-Lead TSOT Pin Configuration
TOP VIEW
(Not to Scale)
3
EN
NC = NO CONNECT
5
4
VOUT
NC
07589-033
Figure 4. 4-Ball WLCSP Pin Configuration
12
VIN VOUT
A
TOP VIEW
(Not to Scale)
ENB
GND
Table 5. Pin Function Descriptions
Pin No.
TSOT WLCSP
Mnemonic Description
1 A1 VIN Regulator Input Supply. Bypass VIN to GND with a 1 µF or greater capacitor.
2 B2 GND Ground.
3 B1 EN
Enable Input. Drive EN high to turn on the regulator; drive EN low to turn off the regulator. For automatic
startup, connect EN to VIN.
4 N/A NC No Connect. Not connected internally. Not applicable (N/A) for the WLCSP.
5 A2 VOUT Regulated Output Voltage. Bypass VOUT to GND with a 1 µF or greater capacitor.
4
07589-03
Rev. A | Page 6 of 20
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