ANALOG DEVICES ADP1046 Service Manual

Digital Controller for Isolated

Data Sheet

FEATURES

Integrates all typical PWM controller functions

7 PWM control signals Digital control loop Integrated programmable loop filters Programmable voltage line feedforward Dedicated soft start filter Programmable dead time for improved efficiency Remote and local voltage sense Primary and secondary side current sense Synchronous rectifier control Current sharing OrFET control

C interface Extensive fault detection and protection Extensive programming and telemetry Fast digital calibration User accessible EEPROM

APPLICATIONS

AC-to-DC power supplies Isolated dc-to-dc power supplies Redundant power supply systems Server, storage, network, and communications

infrastructure

INPU

Power Supply Applications

GENERAL DESCRIPTION

The ADP1046 is a flexible, digital secondary side controller designed for ac-to-dc and isolated dc-to-dc secondary side applications. The ADP1046 is pin-compatible with the

ADP1043A and offers several enhancements and new features,

including voltage feedforward, improved loop response, and programmable dead time control to maximize efficiency.

The ADP1046 is optimized for minimal component count, maximum flexibility, and minimum design time. Features include local and remote voltage sense, primary and secondary side current sense, digital pulse-width modulation (PWM) generation, current sharing, and redundant OrFET control. The control loop digital filter and compensation terms are integrated and can be programmed over the I protection features include overcurrent protection (OCP), overvoltage protection (OVP), undervoltage lockout (UVLO), and overtemperature protection (OTP).

The built-in EEPROM provides extensive programming of the integrated loop filter, PWM signal timing, inrush current, and soft start timing and sequencing. Reliability is improved through a built-in checksum and programmable protection circuits.

A comprehensive GUI is provided for easy design of loop filter characteristics and programming of the safety features. The industry-standard I monitoring and system test functions.

The ADP1046 is available in a 32-lead LFCSP and operates from a single 3.3 V supply.

TYPICAL APPLICATION CIRCUIT

ADP1046

C interface. Programmable

C bus provides access to the many

LOAD

DRIVER

SR1 SR2 ACSNS VS1 GATE

CS1 OUTA

DRIVER

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

iCoupler

OUTB OUTC OUTD OUTAUX

RES RTDADD VCORE FLAGIN PSON PGOOD2 PGOOD1 SDA SCL VDD DGND AGND

Figure 1.

CS2– CS2+ PGND

ADP1046

MICROCONTROLLER

VS2

VS3+

VS3–

SHAREo

SHAREi

10045-001

ADP1046 Data Sheet

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Typical Application Circuit ............................................................. 1

Revision History ............................................................................... 3

Functional Block Diagram .............................................................. 4

Specifications ..................................................................................... 5

Absolute Maximum Ratings .......................................................... 10

Thermal Resistance .................................................................... 10

Soldering ...................................................................................... 10

ESD Caution ................................................................................ 10

Pin Configuration and Function Descriptions ........................... 11

Typical Performance Characteristics ........................................... 13

Theory of Operation ...................................................................... 15

Current Sense .............................................................................. 15

Voltage Sense and Control Loop .............................................. 16

ADCs ............................................................................................ 16

VS1 Operation (VS1) ................................................................. 16

VS2 Operation (VS2) ................................................................. 17

VS3 Operation (VS3+, VS3−) ................................................... 17

Voltage Line Feedforward and ACSNS.................................... 17

Digital Filter ................................................................................ 17

PWM and Sync Rect Outputs (OUTA, OUTB, OUTC,

OUTD, OUTAUX, SR1, SR2) ................................................... 18

Synchronous Rectification ........................................................ 19

SR (Synchronous Rectifier) Delay ............................................ 19

Adaptive Dead Time Control.................................................... 19

Light Load Mode ........................................................................ 19

Modulation Limit ....................................................................... 19

Soft Start ...................................................................................... 20

OrFET Control (GATE) ............................................................ 22

VDD ............................................................................................. 24

VDD/VCORE OVLO ................................................................ 24

Power Good ................................................................................. 24

Current Sharing (Share) ............................................................ 25

Power Supply System and Fault Monitoring ............................... 27

Flags .............................................................................................. 27

Monitoring Functions ................................................................ 27

Voltage Readings ........................................................................ 27

Current Readings ........................................................................ 27

Rev. A | Page 2 of 96

Power Readings .......................................................................... 28

Power Monitoring Accuracy ..................................................... 28

First Flag Fault ID and Value Registers ................................... 28

External Flag Input (FLAGIN Pin) .......................................... 28

Temperature Readings (RTD Pin) ........................................... 28

Overtemperature Protection (OTP) ........................................ 29

Overcurrent Protection (OCP) ................................................ 29

Constant Current Mode ............................................................ 30

Overvoltage Protection (OVP) ................................................. 30

Undervoltage Protection (UVP) .............................................. 31

AC Sense (ACSNS)..................................................................... 31

Volt-Second Balance .................................................................. 32

Digital Load Line and Slew Rate .............................................. 32

Power Supply Calibration and Trim ............................................ 33

CS1 Tri m ...................................................................................... 33

CS2 Tri m ...................................................................................... 33

Voltage Calibration and Trim ................................................... 34

Output Voltage Setting (VS3+, VS3− Trim) ........................... 34

VS1 Trim ...................................................................................... 34

VS2 Trim ...................................................................................... 34

RTD/OTP Trim .......................................................................... 34

ACSNS Calibration and Trim ................................................... 35

Layout Guidelines ........................................................................... 36

CS2+ and CS2− ........................................................................... 36

VS3+ and VS3−........................................................................... 36

VDD ............................................................................................. 36

SDA and SCL .............................................................................. 36

CS1 ............................................................................................... 36

Exposed Pad ................................................................................ 36

VCORE ........................................................................................ 36

RES ............................................................................................... 36

RTD .............................................................................................. 36

AGND, DGND, and PGND ...................................................... 36

I2C Interface Communication ...................................................... 37

Features ........................................................................................ 37

Overview ..................................................................................... 37

I2C Address .................................................................................. 37

Data Transfer............................................................................... 37

General Call Support ................................................................. 39

10-Bit Addressing ....................................................................... 39

Data Sheet ADP1046

Fast Mode ..................................................................................... 39

Repeated Start Condition ........................................................... 39

Electrical Specifications .............................................................. 39

Fault Conditions .......................................................................... 39

Timeout Condition ..................................................................... 39

Data Transmission Faults ........................................................... 39

Data Content Faults .................................................................... 39

EEPROM .......................................................................................... 41

Overview ...................................................................................... 41

Page Erase Operation ................................................................. 41

Read Operation (Byte Read and Block Read) ......................... 41

Write Operation (Byte Write and Block Write) ...................... 42

EEPROM Password..................................................................... 42

Downloading EEPROM Settings to Internal Registers .......... 42

Saving Register Settings to the EEPROM ................................ 43

EEPROM CRC Checksum ......................................................... 43

Software GUI ................................................................................... 44

Detailed Register Descriptions ...................................................... 49

Fault Registers .............................................................................. 49

Value Registers ............................................................................. 52

Current Sense and Current Limit Registers ............................ 55

Voltage Sense Registers............................................................... 60

REVISION HISTORY

6/12—Rev. 0 to Rev. A

Changes to Table 1 ............................................................................ 6

Change to Table 2 ............................................................................ 10

Change to Read from Main Block, Page 2 to Page 15 Section .. 41

Change to Write to Main Block, Page 4 to Page 15 Section ...... 42

Change to Table 49 .......................................................................... 60

3/12—Revision 0: Initial Version

ID Registers .................................................................................. 63

PWM and Synchronous Rectifier Timing Registers .............. 64

Digital Filter Programming Registers ...................................... 74

Adaptive Dead Time Registers .................................................. 76

Soft Start Filter Programming Registers .................................. 80

Extended Functions Registers ................................................... 81

EEPROM Registers ..................................................................... 84

Resonant Mode Operation ............................................................. 87

Resonant Mode Enable ............................................................... 87

PWM Timing in Resonant Mode ............................................. 87

Synchronous Rectification in Resonant Mode ........................ 87

Adjusting the Timing of the PWM Outputs ........................... 88

Frequency Limit Setting ............................................................. 88

Feedback Control in Resonant Mode ....................................... 88

Soft Start in Resonant Mode ...................................................... 88

Light Load Operation (Burst Mode) ........................................ 88

OUTAUX in Resonant Mode .................................................... 88

Protections in Resonant Mode .................................................. 88

Resonant Mode Register Descriptions ..................................... 89

Outline Dimensions ........................................................................ 93

Ordering Guide ........................................................................... 93

Rev. A | Page 3 of 96

ADP1046 Data Sheet

RES

VS3–

VS3+

PGOOD1

VDD

GATE

PGND

ACSNS

VS1

OUTA OUTB

SR1 SR2

OUTC OUTD

CS1

PSON SCL SDA

CS2–

CS2+

VS2

VCORE

AGND

OUTAUX

PGOOD2

SHAREi

FLAGIN DGND

RTDADD

ADC

ADC ADC

ADC

UVLO

PWM

ENGINE

REF

LDO

ADC

8kB

EEPROM

DIGITAL

CORE

INTERFACE

PWM

OSC

1.2V

+ –

0.45V

+ –

V_OVP

SHAREo

10045-002

ADP1046

The ADP1046 is a secondary side controller for switch mode power supplies (SMPS). It is designed for use in isolated redundant applications. The ADP1046 integrates the typical functions that are needed to control a power supply, such as

• Output voltage sense and feedback

• Voltage line feedforward control

• Digital loop filter compensation

• PWM generation

• Current sharing

• Current, voltage, and temperature sense

• OrFET control

• Housekeeping and I

C interface

• Calibration and trimming

The main function of controlling the output voltage is performed using the feedback ADCs, the digital loop filter, and the PWM block.

The feedback ADCs use a multipath approach (patent pending). The ADP1046 combines a high speed, low resolution (fast and coarse) ADC with a low speed, high resolution (slow and accurate) ADC. Loop compensation is implemented using the digital filter. This proportional, integral, derivative (PID) filter is implemented in the digital domain to allow easy programming of filter characteristics, which is of great value in customizing and debugging designs.

FUNCTIONAL BLOCK DIAGRAM

The PWM block generates up to seven programmable PWM outputs for control of FET drivers and synchronous rectification FET drivers. This programmability allows many traditional and unique switching topologies to be realized.

A current share bus interface is provided for paralleling multiple power supplies. The ADP1046 also has hot-swap OrFET sense and control for N + 1 redundant power supplies.

Conventional power supply housekeeping features, such as remote and local voltage sense and primary and secondary side current sense, are included. An extensive set of protections is offered, including overvoltage protection (OVP), overcurrent protection (OCP), overtemperature protection (OTP), undervoltage protection (UVP), ground continuity monitoring (voltage continuity), and ac sense.

All these features are programmable through the I

C bus interface. This bus interface is also used to calibrate the power supply. Other information that is useful for power monitoring, such as input current, output current, and fault flags, is also available through the I

C bus interface.

The internal EEPROM can store all programmed values and allows standalone control without a microcontroller. A free, downloadable GUI is available and provides all the necessary software to program the ADP1046. To obtain the latest software and a user guide, visit http://www.analog.com/digitalpower.

The ADP1046 operates from a single 3.3 V supply and is specified from −40°C to +125°C.

Figure 2. ADP1046 Simplified Block Diagram

Rev. A | Page 4 of 96

Data Sheet ADP1046

OVLO

3.8

4.0

4.1

LOAD

−48 +48

Temperature Coefficient

ppm/°C

Leakage Current

1.0

µA

resolution is 7 bits

VS2 and VS3 OVP Threshold

Relative to nominal voltage (1 V) on VS2

−2.0 +2.0

% FSR

SPECIFICATIONS

VDD = 3.0 V to 3.6 V, TA = −40°C to +125°C, unless otherwise noted. FSR = full-scale range.

Table 1.

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

SUPPLY

Supply Voltage VDD 4.7 µF capacitor connected to AGND 3.0 3.3 3.6 V

Supply Current IDD Normal operation (PSON is high or low) 20 mA During EEPROM programming (40 ms) IDD + 8 mA Shutdown (VDD below UVLO) 100 µA POWER-ON RESET

Power-On Reset VDD rising 3.0 V

UVLO VDD falling 2.75 2.85 2.97 V

UVLO Hysteresis 40 mV

OVLO Debounce When set to 2 µs 2.0 µs When set to 500 µs 500 µs VCORE PIN 0.33 µF capacitor connected to DGND

Output Voltage TA = 25°C 2.4 2.5 2.7 V OSCILLATOR AND PLL

PLL Frequency RES = 10 kΩ (±0.1%) 190 200 210 MHz OUTA, OUTB, OUTC, OUTD,

OUTAUX, SR1, SR2, GATE PINS

Output Low Voltage VOL Source current = 10 mA 0.4 V

Output High Voltage VOH Source current = 10 mA VDD − 0.4 V

Rise Time C

Fall Time C VS1, VS2, VS3 LOW SPEED ADCs

Input Voltage Range VIN Differential voltage from VS1, VS2 to

Usable Input Voltage Range 0 1.4 V

ADC Clock Frequency 1.56 MHz

Voltage Sense Measurement

Accuracy

0% to 100% of usable input voltage range −3.0 +3.0 % FSR

= 50 pF 3.5 ns = 50 pF 1.5 ns

0 1 1.6 V

PGND, and from VS3+ to VS3−

Factory trimmed at 1.0 V

10% to 90% of usable input voltage range −2.0 +2.0 % FSR

−32 +32 mV 900 mV to 1.1 V −1.0 +1.0 % FSR

−16 +16 mV

Voltage Sense Measurement

Resolution Common-Mode Voltage Offset −0.25 +0.25 % FSR Voltage Differential from VS3−

to PGND VS1 Accurate OVP Speed Register 0x32[1:0] = 00; equivalent

VS1 OVP Threshold Accuracy Relative to nominal voltage (1 V) on VS1 −2.0 +2.0 % FSR VS2 and VS3 OVP Speed Register 0x33[1:0] = 00; equivalent

Accuracy

12 Bits

−200 +200 mV

80 µs

resolution is 7 bits

80 µs

and VS3

Rev. A | Page 5 of 96

ADP1046 Data Sheet

At other thresholds (0.8 V to 1.6 V)

−2.06

+2.06

ADC Clock Frequency

1.56 MHz

ACSNS

Input Voltage Range

VIN 0 1 1.4

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

VS3 HIGH SPEED ADC

Equivalent Sampling

Frequency Equivalent Resolution fSW = 390.6 kHz 6 Bits Dynamic Range ±30 mV

VS1 FAST OVP COMPARATOR

Threshold Accuracy At factory trim of 1.2 V 1 1.60 %

fSW kHz

SAMP

Propagation Delay Does not include debounce time

40 ns

(Register 0x0A[7] = 1)

VS1 UVP DIGITAL COMPARATOR

VS1 UVP Accuracy −2.0 +2.0 % FSR Propagation Delay Does not include debounce time

80 µs

(Register 0x0B[3] = 1)

AC SENSE COMPARATOR PWM and resonant mode

Input Voltage Threshold 0.4 0.45 0.5 V Propagation Delay

From ACSNS threshold to SRx rising edge

160 ns

(resonant mode only)

Input Voltage Range V

0 1 1.6 V Usable Input Voltage Range 0 1.4 V Sampling Frequency for I2C

100 Hz

Reporting

Sampling Period for

Equivalent resolution is 11 bits 10 µs

Feedforward

Measurement Accuracy Factory trimmed at 1.0 V

0% to 100% of usable input voltage range −5.0 +3.0 % FSR 10% to 90% of usable input voltage range −2.0 +2.0 % FSR

900 mV to 1.1 V −1.0 +1.0 % FSR

−16 +16 mV Leakage Current 1.0 µA

CURRENT SENSE 1 (CS1 PIN)

Usable Input Voltage Range 0 1.3 V ADC Clock Frequency 1.56 MHz Register Update Rate 10 ms Current Sense Measurement

Accuracy

Factory trimmed at 0.7 V; tested under dc

input conditions

10% to 50% of usable input voltage range −3.0 +3.0 % FSR

−41.4 +41.4 mV 0% to 100% of usable input voltage range −6.0 +3.0 % FSR

−84 +42 mV 40% to 60% of usable input voltage range −1.0 +1.0 % FSR Current Sense Measurement

12 Bits

Resolution CS1 Fast OCP Threshold 1.184 1.2 1.216 V CS1 Fast OCP Speed 80 100 ns CS1 Accurate OCP DC Accuracy 10% to 90% of usable input voltage range −2.0 +2.0 % FSR

−28 +28 mV CS1 Accurate OCP Speed 2.62 5.24 ms Leakage Current 1.0 μA

Rev. A | Page 6 of 96

Data Sheet ADP1046

Usable Input Voltage Range

0 110

60 mV Setting

0 mV to 55 mV, VDD = 3.3 V

−1.8 +1.8

% FSR

−2.16

+2.16

−18 mV setting

−12.22

−19.07

−25.92

Current source set to 40 µA

38.45

40.3

41.95

µA

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

CURRENT SENSE 2 (CS2+, CS2−

PINS) Input Voltage Range VIN Differential voltage from CS2+ to CS2−,

ADC Clock Frequency 1.56 MHz Temperature Coefficient

120 mV Range 0 mV to 100 mV 78 ppm/°C

0 mV to 50 mV 70 ppm/°C

60 mV Range 0 mV to 50 mV 156 ppm/°C 0 mV to 25 mV 140 ppm/°C Current Sense Measurement

120 mV Setting 0 mV to 110 mV −2.1 +2.1 % FSR

−2.52 +2.52 mV

60 mV Setting 0 mV to 55 mV −4.2 +4.2 % FSR

−5.04 +5.04 mV

Current Sense Measurement

Accuracy

120 mV Setting 0 mV to 100 mV, VDD = 3.3 V −0.9 +0.9 % FSR

−1.08 +1.08 mV

0 120 mV

LSB = 29.297 μV

With 0.01% level shifting resistors

Current Sense Measurement

Resolution CS2 Accurate OCP Speed 2.62 5.24 ms Current Sink (High Side) 2 mA Current Source (Low Side) 200 μA Common-Mode Voltage at the

CS2+ and CS2− Pins

OrFET PROTECTION (CS2+, CS2−) Low-side and high-side current sensing

Fast OrFET Accuracy −3 mV setting +3.5 −3.00 −9.5 mV

−6 mV setting +0.29 −6.21 −12.71 mV

−9 mV setting −2.68 −9.43 −16.18 mV

−12 mV setting −5.89 −12.64 −19.39 mV

−15 mV setting −9.01 −15.86 −22.71 mV

−21 mV setting −15.29 −22.29 −29.29 mV

−24 mV setting −18.50 −25.50 −32.50 mV Fast OrFET Speed Debounce = 40 ns 110 150 ns

RTD TEMPERATURE SENSE

ADC Clock Frequency 1.56 MHz Input Voltage Range RTD to AGND 0 1.6 V Usable Input Voltage Range 0 1.3 V Source Current Factory trimmed to 46 μA (Register 0x11

Current source set to 10 µA 9.25 10.1 10.85 µA Current source set to 20 µA 18.35 20.1 21.85 µA Current source set to 30 µA 28.45 30.2 31.95 µA

12 Bits

To achieve CS2 measurement accuracy 0.8 1.0 1.4 V

44.35 46 47.65 µA

set to 0xE6)

Source Current Fine Setting See Register 0x11[5:0] 160 nA RTD ADC

Rev. A | Page 7 of 96

ADP1046 Data Sheet

−42 +42

EXT

SDA/SCL PINS

VDD = 3.3 V

BUF

SU;STA

SU;STO

SU ;D AT

SDA Hold Time

HD;DAT

For readback

125

For write

300

TIMEOUT

LOW

HIGH

LO;SEXT

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

Measurement Accuracy Factory trimmed at 1 V

10 mV to 160 mV −0.5 +0.5 % FSR

−8 +8 mV 0% to 100% of usable input voltage range −3.0 +3.0 % FSR

Temperature Readings

According to Internal Linearization Scheme

RTD source set to 46 µA (Register 0x11 set to 0xE6); NTC R0 = 100 kΩ, 1%, beta = 4250, 1%; R

= 16.5 kΩ, 1% 25°C to 100°C 7 °C 100°C to 125°C 5 °C

OTP

Threshold Accuracy T = 85°C with 100 kΩ||16.5 kΩ −0.9 +0.25 % FSR

−14.4 +4 mV T = 100°C with 100 kΩ||16.5 kΩ −0.5 +1.1 % FSR

−8 +17.6 mV Comparator Speed 10.5 ms OTP Threshold Hysteresis 16 mV

PGOOD1, PGOOD2, SHAREo PINS Open-drain outputs

Output Low Voltage VOL 0.4 V

PSON, SHAREi PINS Digital inputs

Input Low Voltage VIL 0.8 V Input High Voltage VIH VDD − 0.8 V Leakage Current 1.0 µA

FLAGIN PIN Digital input

Input Low Voltage VIL 0.4 V Input High Voltage VIH VDD − 0.8 V Propagation Delay Does not include debounce time (Register

200 ns

0x0A[3] = 1); flag action set to disable PSU

Leakage Current 1.0 µA

GATE PIN

Output Low Voltage VOL 0.4 V Output High Voltage VOH VDD − 0.4 V

Input Low Voltage VIL 0.8 V Input High Voltage VIH VDD − 0.8 V Output Low Voltage VOL 0.4 V Leakage Current 1.0 µA

SERIAL BUS TIMING See Figure 3

Clock Operating Frequency 10 100 400 kHz Bus-Free Time t Start Hold Time t

Start Setup Time t Stop Setup Time t SDA Setup Time t

SCL Low Timeout t SCL Low Period t SCL High Period t Clock Low Extend Time t SCL, SDA Fall Time tF 20 300 ns SCL, SDA Rise Time tR 20 300 ns

Between stop and start conditions 1.3 µs

HD;STA

Hold time after (repeated) start condition;

0.6 µs

after this period, the first clock is generated Repeated start condition setup time 0.6 µs

0.6 µs 100 ns

25 35 ms

1.3 µs

0.6 µs 25 ms

Rev. A | Page 8 of 96

Data Sheet ADP1046

TJ = 125°C

Years

SCL

SDA

P S

BUF

HD;STA

HD;DAT

HIGH

SU;DAT

HD;STA

SU;STA

SU;STO

LOW

S P

10045-103

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

EEPROM RELIABILITY

Endurance1 TJ = 85°C 10,000 Cycles TJ = 125°C 1000 Cycles Data Retention2 TJ = 85°C 20 Years

Endurance is qualified as per JEDEC Standard 22, Method A117, and is measured at −40°C, +25°C, +85°C, and +125°C. Endurance conditions are subject to change

pending EEPROM qualification.

Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Standard 22, Method A117. The derated retention lifetime equivalent at junction

temperature T

Timing Diagram

= 125°C is 2.87 years and is subject to change pending EEPROM qualification.

Figure 3. Serial Bus Timing Diagram

Rev. A | Page 9 of 96

ADP1046 Data Sheet

Digital Pins: OUTA, OUTB, OUTC, OUTD,

−0.3 V to VDD + 0.3 V

RTD, ADD

−0.3 V to VDD + 0.3 V

(20 sec to 40 sec)

ESD Charged Device Model

1.5 kV

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Supply Voltage (Continuous), VDD 4.2 V

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.

OUTAUX, SR1, SR2, GATE, PGOOD1,

PGOOD2 VS3− to PGND, AGND, DGND −0.3 V to +0.3 V VS1, VS2, VS3+, ACSNS −0.3 V to VDD + 0.3 V

CS1, CS2+, CS2− −0.3 V to VDD + 0.3 V FLAGIN, PSON −0.3 V to VDD + 0.3 V SDA, SCL −0.3 V to VDD + 0.3 V SHAREo, SHAREi −0.3 V to VDD + 0.3 V Operating Temperature Range −40°C to +125°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C Peak Solder Reflow Temperature

SnPb Assemblies (10 sec to 30 sec) 240°C

RoHS-Compliant Assemblies

ESD Human Body Model 3.5 kV

260°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Table 3. Thermal Resistance

Package Type θJA θJC Unit

32-Lead LFCSP 44.4 6.4 °C/W

SOLDERING

It is important to follow the correct guidelines when laying out the PCB footprint for the ADP1046 and when soldering the part onto the PCB. For detailed information about these guidelines, see the AN-772 Application Note.

ESD CAUTION

Rev. A | Page 10 of 96

Data Sheet ADP1046

PIN 1 INDICATOR

1VS2 2AGND 3VS1 4CS2– 5CS2+ 6ACSNS 7CS1 8PGND

24 SHAREi 23 SHAREo 22 PGOOD1 21 PGOOD2 20 FLAGIN 19 PSON 18 SDA 17 SCL

9SR1

10SR2

11OUTA

12OUTB

13OUTC

14OUTD

15OUTAUX

16GATE

VS3+

VS3–

RES

ADD

RTD

VDD

VCORE

DGND

ADP1046

TOP VIEW

(Not to S cale)

NOTES

1. THE ADP1046 HAS AN EXPOSED THERMAL PAD ON THE UNDERSIDE OF THEPACKAGE. FOR INCREASED RELIABILITY OF THE SOLDER JOINTSAND MAXIM UM THERMAL CAPABILITY, IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE PCB AGND PLANE.

10045-003

CS2−

Inverting Differential Current Sense Input. Nominal voltage at this pin should be 1 V for best operation. When

SR1

Synchronous Rectifier Output. This PWM output connects to the input of a FET driver. This pin can be disabled

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 4. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 VS2 Power Supply Output Voltage Sense Input. This signal is referenced to PGND and is the input to a low frequency

Σ-Δ ADC. Nominal voltage at this pin should be 1 V. The resistor divider on this input must have a tolerance

specification of 0.5% or better to allow for trimming. 2 AGND Analog Ground. This pin is the ground for the analog circuitry and the return for the VDD pin of the ADP1046. 3 VS1 Local Output Voltage Sense Input. This signal is referenced to PGND. Nominal voltage at this pin should be 1 V.

The resistor divider on this input must have a tolerance specification of 0.5% or better to allow for trimming.

using low-side current sensing, place a 5 kΩ resistor between the sense resistor and this pin. When using high-

side current sensing in a 12 V application, place a 5.5 kΩ resistor between the sense resistor and this pin. When

using high-side current sensing with a voltage other than 12 V, use this formula to calculate the resistor value:

R = (V

− 1)/2 mA. A 0.1% resistor must be used to connect this circuit. If this pin is not used, connect it to PGND

OUT

and set CS2± to high-side current sense mode (set Bit 2 of Register 0x27). It is recommended that a 500 pF to

1000 pF capacitor be connected either across the resistor or from this pin to AGND. 5 CS2+ Noninverting Differential Current Sense Input. Nominal voltage at this pin should be 1 V for best operation.

When using low-side current sensing, place a 5 kΩ resistor between the sense resistor and this pin. When using

high-side current sensing in a 12 V application, place a 5.5 kΩ resistor between the sense resistor and this pin.

When using high-side current sensing with a voltage other than 12 V, use this formula to calculate the resistor

value: R = (V

− 1)/2 mA. A 0.1% resistor must be used to connect this circuit. If this pin is not used, connect it

OUT

to PGND and set CS2± to high-side current sense mode (set Bit 2 of Register 0x27). It is recommended that a

500 pF to 1000 pF capacitor be connected either across the resistor or from this pin to AGND. 6 ACSNS AC Sense Input. This input is connected upstream of the main output inductor through a resistor divider

network. The nominal voltage for this circuit is 0.45 V. This pin is also connected to the voltage feedforward

ADC (nominal voltage 1 V). This signal is referenced to PGND. 7 CS1 Primary Side Current Sense Input. This pin is connected to the primary side current sensing ADC and to the fast

OCP comparator. This signal is referenced to PGND. The resistors on this input must have a tolerance specification

8 PGND Power Ground. This pin is the ground connection for the main power rail of the power supply and is the

10 SR2 Synchronous Rectifier Output. This PWM output connects to the input of a FET driver. This pin can be disabled

11 OU TA PWM Output for Primary Side Switch. This pin can be disabled when not in use. This signal is referenced to AGND. 12 OUTB PWM Output for Primary Side Switch. This pin can be disabled when not in use. This signal is referenced to AGND.

of 0.5% or better to allow for trimming. If this pin is not used, connect it to PGND.

reference for all voltage and current sensing other than CS2± and VS3±. Star connect to AGND.

when not in use. This signal is referenced to AGND.

Rev. A | Page 11 of 96

ADP1046 Data Sheet

SCL

I2C Serial Clock Input. This signal is referenced to AGND.

this pin is 1 V. The resistor divider on this input must have a tolerance specification of 0.5% or better to allow for

Pin No. Mnemonic Description

13 OUTC PWM Output for Primary Side Switch. This pin can be disabled when not in use. This signal is referenced to AGND. 14 OUTD PWM Output for Primary Side Switch. This pin can be disabled when not in use. This signal is referenced to AGND. 15 OUTAUX Auxiliary PWM Output. This pin can be disabled when not in use. This signal is referenced to AGND. 16 GATE OrFET Gate Drive Output. This signal is referenced to AGND. If this pin is not used, leave it floating.

18 SDA I2C Serial Data Input and Output (Open Drain). This signal is referenced to AGND. 19 PSON Power Supply On Input. This signal is referenced to AGND. This pin is the hardware PSON control signal. It is

recommended that a 1 nF capacitor be connected from the PSON pin to AGND for noise debouncing and

decoupling. 20 FLAGIN Flag Input. An external signal can be input at this pin to generate a flag condition. 21 PGOOD2 Power-Good Output (Open Drain). This signal is referenced to AGND. This pin is controlled by the PGOOD2 flag.

This pin is set by a programmable combination of internal flags. If this pin is not used, connect it to AGND. 22 PGOOD1 Power-Good Output (Open Drain). This signal is referenced to AGND. This pin is controlled by the PGOOD1 flag.

This pin is set by a programmable combination of internal flags. If this pin is not used, connect it to AGND. 23 SHAREo Share Bus Output Voltage Pin. Connect this pin to 3.3 V through a pull-up resistor (typically 2.2 kΩ). When

configured for a digital share bus, this pin is a digital output. This signal is referenced to AGND. If this pin is

not used, connect it to AGND. 24 SHAREi Share Bus Feedback Pin. Connect this pin to the SHAREo pin. This signal is referenced to AGND. If this pin is not

used, connect it to AGND. 25 DGND Digital Ground. This pin is the ground reference for the digital circuitry of the ADP1046. Star connect to AGND. 26 VCORE Output of the 2.5 V Regulator. Connect a decoupling capacitor of at least 330 nF (1 µF maximum) from this pin

to DGND as close to the IC as possible to minimize PCB trace length. It is recommended that the VCORE pin not

be used as a reference or to generate other logic levels using resistive dividers. 27 VDD Positive Supply Input. This signal is referenced to AGND. Connect a 4.7 µF decoupling capacitor from this pin to

AGND as close to the IC as possible to minimize PCB trace length. 28 RTD Thermistor Input. Place a thermistor (100 kΩ, 1%, beta = 4250, 1%) in parallel with a 16.5 kΩ, 1% resistor. This

pin is referenced to AGND. If this pin is not used, connect it to AGND. 29 ADD Address Select Input. This pin is used to program the I2C address. Connect a resistor from ADD to AGND. This

signal is referenced to AGND. 30 RES Resistor Input. This pin sets up the internal voltage reference for the ADP1046. Connect a 10 kΩ, ±0.1% resistor

from RES to AGND. This signal is referenced to AGND. 31 VS3− Inverting Remote Voltage Sense Input. There should be a low ohmic connection to AGND. The resistor divider

on this input must have a tolerance specification of 0.5% or better to allow for trimming. Connect a 0.1 µF

capacitor from VS3− to AGND. 32 VS3+ Noninverting Remote Voltage Sense Input. This signal is referenced to VS3−, and the nominal input voltage at

trimming. This pin is the input to the high frequency Δ-Σ ADC. EP Exposed Pad. The ADP1046 has an exposed thermal pad on the underside of the package. For increased

reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered

to the PCB AGND plane.

Rev. A | Page 12 of 96

Data Sheet ADP1046

2.5

–2.5

–2.0

–1.5

–1.0

–0.5

0.5

1.0

1.5

2.0

–60 –40 –20 0 20 40 60 80 100 120 140

VS1 ADC ACCURACY (%FSR)

TEMPERATURE (°C)

10045-400

MAX SPEC

MIN SPEC

MIN MEAN

MAX

2.5

–2.5

–2.0

–1.5

–1.0

–0.5

0.5

1.0

1.5

2.0

–60 –40 –20 0 20 40 60 80 100 120 140

VS2 ADC ACCURACY (%FSR)

TEMPERATURE (°C)

10045-401

MAX SPEC

MIN SPEC

MIN MEAN

MAX

2.5

–2.5

–2.0

–1.5

–1.0

–0.5

0.5

1.0

1.5

2.0

–60 –40 –20 0 20 40 60 80 100 120 140

VS3 ADC ACCURACY (%FSR)

TEMPERATURE (°C)

10045-402

MAX SPEC

MIN SPEC

MIN MEAN

MAX

2.5

–2.5

–2.0

–1.5

–1.0

–0.5

1.0

0.5

1.5

2.0

–60 –40 –20 0 20 40 60 80 100 120 140

CS1 ADC ACCURACY (%FSR)

TEMPERATURE (°C)

10045-403

MAX SPEC

MIN SPEC

MIN

MEAN

MAX

2.5

–2.5

–2.0

–1.5

–1.0

–0.5

1.0

0.5

1.5

2.0

–60 –40 –20 0 20 40 60 80 100 120 140

CS2 ADC ACCURACY (%FSR)

TEMPERATURE (°C)

10045-404

MAX SPEC

MIN SPEC

MIN

MEAN

MAX

1.24

1.16

1.17

1.18

1.19

1.20

1.21

1.22

1.23

–60 –40 –20 0 20 40 60 80 100 120 140

CS1 FAST O CP THRESHOLD (V )

TEMPERATURE (°C)

10045-405

MIN

MAX

MAX SPEC

MIN SPEC

MEAN

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 5. VS1 ADC Accuracy vs. Temperature (from 10% to 90% of FSR)

Figure 8. CS1 ADC Accuracy vs. Temperature (from 10% to 90% of FSR)

Figure 6. VS2 ADC Accuracy vs. Temperature (from 10% to 90% of FSR)

Figure 7. VS3 ADC Accuracy vs. Temperature (from 10% to 90% of FSR)

Figure 9. CS2 ADC Accuracy vs. Temperature (from 10% to 90% of FSR)

Figure 10. CS1 Fast OCP Threshold vs. Temperature

Rev. A | Page 13 of 96

ADP1046 Data Sheet

2.5

–2.5

–2.0

–1.5

–1.0

–0.5

1.0

0.5

1.5

2.0

–60 –40 –20 0 20 40 60 80 100 120 140

ACSNS ADC ACCURACY (%FSR)

TEMPERATURE (°C)

10045-406

MIN

MAX SPEC

MIN SPEC

MEAN

MAX

–4

–3

–2

–1

–60 –40 –20 0 20 40 60 80 100 120 140

RTD ADC ACCURACY (%FSR)

TEMPERATURE (°C)

10045-408

MAX SPEC

MIN SPEC

MIN

MAX

MEAN

Figure 11. ACSNS ADC Accuracy vs. Temperature (from 10% to 90% of FSR)

Figure 12. RTD ADC Accuracy vs. Temperature (from 10% to 90% of FSR)

Rev. A | Page 14 of 96

Data Sheet ADP1046

CS1

1kΩ 10Ω

I = 100mA

I = 10A

OUTA

OUTB

OUTC

OUTD

ADC

12 BITS

REF

FAST OCP

1:100

10045-010

CS2–CS2+

ADC

12 BITS

5.5kΩ 5.5kΩ

12V

2mA 2mA

10045-011

CS2+CS2–

ADC

12 BITS

5kΩ 5kΩ

200µA 200µA

10045-012

THEORY OF OPERATION

CURRENT SENSE

The ADP1046 has two current sense inputs: CS1 and CS2±. These inputs sense, protect, and control the primary input current, secondary output current, and the share bus information. They can be calibrated to reduce errors due to external components.

CS1 Operation (CS1)

CS1 is typically used for the monitoring and protection of the primary side current, which is commonly sensed using a current transformer (CT). The input signal at the CS1 pin is fed into an ADC for current monitoring. The range of the ADC is 0 V to 1.4 V. The input signal is also fed into a comparator for pulse-by-pulse OCP protection. The typical configuration for the CS1 current sense is shown in Figure 13.

When using low-side current sensing, the current sources are 200 µA; therefore, the required resistor value is 1 V/200 µA = 5 kΩ. When using high-side current sensing, the current sources are 2 mA; therefore, the resistor value required is (V In the case of V

= 12 V, the required resistor value is 5.5 kΩ.

OUT

− 1 V)/2 mA.

OUT

Typical configurations are shown in Figure 14 and Figure 15. Various thresholds and limits can be set for CS2±, such as OCP. These thresholds and limits are described in the Current Sense and Current Limit Registers section.

When not in use, the CS2+ and CS2− inputs should both be connected directly to PGND, and CS2± should be set to highside current sense mode (Register 0x27[2] = 1).

The CS2 ADC is used to measure the CS2 current; the reading is averaged every 2.62 ms in an asynchronous fashion. This averaged reading is used to make fault decisions, such as the CS2 OCP fault. The ADP1046 also writes the 12-bit CS2 reading every 10 ms to Register 0x18.

Figure 13. Current Sense 1 (CS1) Operation

The CS1 ADC is used to measure the average value of the primary current; the reading is averaged every 2.62 ms in an asynchronous fashion to make fault decisions. The ADP1046 also writes the 12-bit CS1 reading every 10 ms to Register 0x13.

The fast OCP comparator is used to limit the instantaneous primary current within each switching cycle and has a nominal threshold of 1.2 V.

Various thresholds and limits can be set for CS1, as described in the Current Sense and Current Limit Registers section.

CS2 Operation (CS2+, CS2−)

CS2+ and CS2− are differential inputs used for the monitoring and protection of the secondary side current. The full-scale range of the CS2 ADC is programmable to 60 mV or 120 mV. The differential inputs are fed into an ADC through a pair of external resistors that provide the necessary level shifting. The device pins, CS2+ and CS2−, are internally regulated to approximately 1 V by internal current sources.

Figure 14. High-Side Resistive Current Sense

Figure 15. Low-Side Resistive Current Sense (Recommended)

Rev. A | Page 15 of 96

ADP1046 Data Sheet

VS1

VS3+

VS3–

VS2

ADC

PGND

VS3VS2

12 BITS

VS1

12 BITS

DIGITAL

FILTER

1V 1V

12V 12V

11kΩ

1kΩ

LOAD

11kΩ11kΩ

1kΩ 1kΩ

12V

ADC

VS3

12 BITS

ADC

10045-013

MAGNITUDE

FREQUENCY

NYQUIST ADC

NOISE

Σ-Δ ADC

NOISE

10045-014

195.3

7 bits

VOLTAGE SENSE AND CONTROL LOOP

Multiple voltage sense inputs on the ADP1046 are used for the monitoring, control, and protection of the power supply output. This information is available through the I sense points can be calibrated digitally to minimize errors due to external components. This calibration can be performed in the production environment, and the settings can be stored in the EEPROM of the ADP1046 (see the Power Supply Calibration and Tri m section for more information).

For voltage monitoring, the VS1, VS2, and VS3 voltage value registers (Register 0x15, Register 0x16, and Register 0x17, respectively) are updated every 10 ms. The ADP1046 stores every ADC sample for 10 ms and then outputs the average value at the end of the 10 ms period. Therefore, if these registers are read at least every 10 ms, a true average value is read.

The ADP1046 uses two separate sensing points: VS1 and VS3±, depending on the condition of the OrFET. When the OrFET is turned off, the control loop is regulated via VS1; when the OrFET is turned on, the control loop is regulated via the differential sensing on VS3±. This sensing mechanism effectively performs a local and remote voltage sense.

The control loop of the ADP1046 features a patented multipath architecture. The output voltage is converted simultaneously by two ADCs: a high accuracy ADC and a high speed ADC. The complete signal is reconstructed and processed in the digital filter to provide a high performance, cost competitive solution.

C interface. All voltage

Σ-Δ ADCs also differ from Nyquist rate ADCs in that the quantization noise is not uniform across the frequency spectrum. At lower frequencies, the noise is lower, and at higher frequencies, the noise is higher (see Figure 17).

Figure 17. Noise Performance for Nyquist Rate and Σ-Δ ADCs

The low frequency ADC runs at approximately 1.56 MHz. For a specified bandwidth, the equivalent resolution can be calculated as follows:

ln(1.56 MHz/BW)/ln2 = N bits

For example, at a bandwidth of 95 Hz, the equivalent resolution/noise is

ln(1.5 MHz/95)/ln2 = 14 bits

At a bandwidth of 1.5 kHz, the equivalent resolution/noise is

ln(1.56 MHz/1.5 kHz)/ln2 = 10 bits

The high frequency ADC has a clock of 25 MHz. It is comb filtered and outputs at the switching frequency (f

) into the

digital filter. The equivalent resolution at some sample frequencies is listed in Ta b l e 5.

Figure 16. Voltage Sense Configuration

ADCs

Two kinds of Σ-Δ ADCs are used in the feedback loop of the

ADP1046: a low frequency (LF) ADC that runs at 1.56 MHz

and a high frequency (HF) ADC that runs at 25 MHz.

Σ-Δ ADCs have a resolution of one bit and operate differently from traditional flash ADCs. The equivalent resolution obtainable depends on how long the output bit stream of the Σ-Δ is sampled.

Table 5. Equivalent Resolutions for High Frequency ADC at Various Switching Frequencies

fSW (kHz) High Frequency ADC Resolution

48.8 9 bits

97.7 8 bits

390.6 6 bits

The HF ADC has a range of ±30 mV. Using a base switching frequency (f increases to 200 kHz (7-bit HF ADC resolution), the quantization noise is 0.9375 mV (1 LSB). Increasing f quantization noise to 3.75 mV (1 LSB = 2 × 30 mV/2

VS1 OPERATION (VS1)

Rev. A | Page 16 of 96

VS1 is used for the monitoring and protection of the power supply voltage at the output of the LC stage, upstream of the OrFET. The VS1 sense point on the power rail needs an external resistor divider to bring the nominal input voltage to 1 V at the VS1 pin (see Figure 16). The resistor divider is necessary because the VS1 ADC input range is 0 V to 1.6 V (12-bit reading). This divideddown signal is internally fed into a low speed Σ-Δ ADC. The output of the VS1 ADC goes to the digital filter and is also updated in Register 0x15 every 10 ms. The VS1 signal is referenced to PGND. When the OrFET is turned off, the power supply is regulated from the VS1 sense point instead of the VS3± sense point.

) of 100 kHz (8-bit HF ADC resolution), when fSW

to 400 kHz increases the

= 0.9375 mV).

Data Sheet ADP1046

ACSNS

ADC

0V TO 1.6V

ACSNS

FEEDFORWARD

ADC

0.6V TO 1. 6V

PROGRAMMABLE

ACTION (REG 0x0D[3:0])

FEEDFORWARD

GAIN

(REG 0x75[1:0])

DPWM

ENGINE

DIGITAL

FILTER

ACSNS GAIN TRIM

(REG 0x5E)

0.45V

1/x

FROM

SECONDARY

WINDING

10045-015

ACSNS

DIGITAL

FILTER

OUTPUT

OUTx

MODULATION

10045-016



 





 



−

×+



 





 



−

H(z)

68.7124.202

VS2 OPERATION (VS2)

VS2 is used in conjunction with VS1 to control the OrFET gate drive turn-on. The VS2 sense point on the power rail needs an external resistor divider to bring the nominal common-mode signal to 1 V at the VS2 pin (see Figure 16).

The resistor divider is necessary because the VS2 ADC input range is 0 V to 1.6 V. This divided-down signal is internally fed into the VS2 ADC. The output of the VS2 ADC goes to the VS2 voltage value register (Register 0x16). The VS2 signal is never used for the control loop but is used to control the turn-on and turn-off of the OrFET (see the OrFET Control (GATE) section) as well as the voltage continuity flag. If the OrFET function of the ADP1046 is not used, it is recommended that the VS2 input be connected directly to PGND. The VS2 value is updated in Register 0x16 every 10 ms.

VS3 OPERATION (VS3+, VS3−)

VS3± is used for the monitoring and protection of the remote load voltage. VS3± is a fully differential input that is the main feedback sense point for the power supply control loop. The VS3± sense point on the power rail needs an external resistor divider to bring the nominal common-mode signal to 1 V at the VS3± pins (see Figure 16). The resistor divider is necessary because the VS3 ADC input range is 0 V to 1.6 V. This divideddown signal is internally fed into a high frequency (HF) ADC. The output of the VS3 ADC goes to the digital filter and is also updated in Register 0x17 every 10 ms. The HF ADC is also the high frequency feedback loop for the power supply.

VOLTAGE LINE FEEDFORWARD AND ACSNS

The ADP1046 supports voltage line feedforward control to improve line transient performance. The ACSNS value is used to divide the output of the digital filter, and the result is fed into the PWM engine. The input voltage signal can be sensed at the secondary winding of the isolation transformer and must be filtered by an RCD network to eliminate the voltage spike at the switch node (see Figure 18).

The feedforward scheme modifies the modulation value based on the ACSNS voltage. When the ACSNS input is 1 V, the line feedforward has no effect. For example, if the digital filter output remains unchanged and the ACSNS voltage changes to 50% of its original value (still higher than 0.5 V), the modulation of the falling edge of OUTx doubles and vice versa (see Figure 19). The voltage line feedforward function is optional and is programmable using Register 0x75.

Figure 19. Feedforward Control on Modulation

The ACSNS level comparator is also connected on the same pin and flags an ACSNS fault when the voltage on the pin is below

0.45 V within each switching period. The ACSNS level comparator is used to detect whether the node is switching.

DIGITAL FILTER

The loop response of the power supply can be changed using the internal programmable digital filter. A Type 3 filter architecture has been implemented. To tailor the loop response to the specific application, the low frequency gain, zero location, pole location, and high frequency gain can all be set individually (see the Digital Filter Programming Registers section). It is recommended that the Analog Devices, Inc., software GUI be used to program the filter. The software GUI displays the filter response in Bode plot format and can be used to calculate all stability criteria for the power supply.

From the sensed voltage to the duty cycle, the transfer function of the filter in z-domain is as follows:

Figure 18. Feedforward Configuration

The ACSNS voltage must be set to 1 V when the nominal input voltage is applied. The ACSNS ADC sampling period is 10 µs; therefore, the decision to modify the PWM outputs based on input voltage is performed at this rate.

where:

a = filter_pole_register_value/256. b = filter_zero_register_value/256. c = high_frequency_gain_register_value. d = low_frequency_gain_register_value. m = 1 when 48.8 kHz ≤ f m = 2 when 97.7 kHz ≤ f m = 4 when 195.3 kHz ≤ f m = 8 when 390.6 kHz ≤ f

where f

Rev. A | Page 17 of 96

< 97.7 kHz.

< 195.3 kHz.

< 390.6 kHz.

is the switching frequency.

ADP1046 Data Sheet

z(s)

−

ISOLATORDRIVER

DRIVER

OUTA OUTB OUTC OUTD

SR1 SR2

OUTA

OUTD

OUTC

OUTB

SR1

SR2

10045-117

To transfer the z-domain value to the s-domain, plug the following bilinear transformation equation into the H(z) equation:

The digital filter introduces an extra phase delay element into the control loop. The digital filter circuit sends the duty cycle information to the PWM circuit at the beginning of each switching cycle (unlike an analog controller, which makes decisions on the duty cycle information continuously). Therefore, the extra phase delay for phase margin, Φ, introduced by the filter block is

Φ = 360 × (f

C/fSW

)

where:

is the crossover frequency.

is the switching frequency.

At one-tenth the switching frequency, the phase delay is 36°. The GUI incorporates this phase delay into its calculations. Note that the GUI does not account for other delays such as gate driver and propagation delays.

Two sets of registers allow for two distinct filter responses. The main filter, called the normal mode filter, is controlled by programming Register 0x60 to Register 0x63. The light load mode filter is controlled by programming Register 0x64 to Register 0x67. The ADP1046 uses the light load mode filter only when the output current measured on CS2± is below the load current threshold (programmed using Register 0x3B[2:0]).

The Analog Devices software GUI allows the user to program the light load mode filter in the same manner as the normal mode filter. It is recommended that the GUI be used for this purpose.

In addition, during the soft start process, a soft start filter can be used in combination with the normal mode filter and the light load mode filter. The soft start filter is programmed using Register 0x71 to Register 0x74. For more information, see the Soft Start section.

Filter Transitions

To avoid output voltage glitches and provide a seamless transition from one filter to another, the ADP1046 supports programmable filter transitions. This feature allows a gradual transition from one filter to another. Filter transitions are programmed using Register 0x7A[2:0].

PWM AND SYNC RECT OUTPUTS (OUTA, OUTB, OUTC, OUTD, OUTAUX, SR1, SR2)

The PWM and SR outputs are used for control of the primary side drivers and the synchronous rectifier drivers. These outputs can be used for several control topologies such as full-bridge, phase-shifted ZVS configurations and interleaved, two switch forward converter configurations. Delays between rising and falling edges can be individually programmed. Special care must be taken to avoid shootthrough and cross-conduction. It is recommended that the Analog Devices software GUI be used to program these outputs. Figure 20 shows an example configuration to drive a full-bridge, phase-shifted topology with synchronous rectification.

Figure 20. PWM Pin Assignment for Full-Bridge, Phase-Shifted Topology

with Synchronous Rectification

The PWM and SR outputs are all synchronized with each other. Therefore, when reprogramming more than one of these outputs, it is important to first update all the registers and then latch the information into the ADP1046 at the same time. During reprogramming, the outputs are temporarily disabled. A special instruction is sent to the ADP1046 to ensure that new timing information is programmed simultaneously. This is done by setting Bit 1 in Register 0x7F. It is recommended that PWM outputs be disabled when not in use.

OUTAUX is an additional PWM output pin. OUTAUX allows an extra PWM signal to be generated at a different frequency from the other six PWM outputs. This signal can be used to drive an extra power converter stage, such as a buck controller located in front of a full-bridge converter. OUTAUX can also be used as a clock reference signal.

For more information about the various programmable switching frequencies and PWM timings, see the PWM and Synchronous Rectifier Timing Registers section (Register 0x3F to Register 0x5C).

Rev. A | Page 18 of 96

OUTx

MODULATION_LIMIT

10045-118

Data Sheet ADP1046

SYNCHRONOUS RECTIFICATION

SR1 and SR2 are recommended for use as the PWM control signals when using synchronous rectification. These PWM signals can be configured much like the other PWM outputs.

An optional soft start can be applied to the synchronous rectifier PWM outputs. The SR soft start can be programmed using Register 0x54[1:0].

• When SR soft start is disabled (Register 0x54[0] = 0),

the SR signals are turned on to their full PWM duty cycle values immediately.

• When SR soft start is enabled (Register 0x54[0] = 1), the

SR signals ramp up from zero duty cycle to the desired duty cycle in steps of 40 ns per switching cycle.

The advantage of ramping the SR signals is to minimize the output voltage step that occurs when the SR FETs are turned on without a soft start. The advantage of turning the SR signals completely on immediately is that they can help to minimize the voltage transient caused by a load step.

Using Register 0x54[1], the SR soft start can be programmed to occur only once (the first time that the SR signals are enabled) or every time that the SR signals are enabled, for example, when the system enters or exits light load mode.

When programming the ADP1046 to use SR soft start, ensure correct operation of this function by setting the falling edge of SR1 (t

) to a lower value than the rising edge of SR1 (t9) and by

setting the falling edge of SR2 (t edge of SR2 (t

). SR soft start can also be disabled by setting

) to a lower value than the rising

SR (SYNCHRONOUS RECTIFIER) DELAY

The ADP1046 is well suited for dc-to-dc converters in isolated topologies. Every time a PWM signal crosses the isolation barrier an additional propagation delay is added due to the isolating components. The ADP1046 allows programming of an adjustable delay (0 ns to 315 ns in steps of 5 ns) using Register 0x79[5:0]. This delay moves both SR1 and SR2 later in time to compensate for the added delay due to the isolating components (see Figure 56). In this way, the edges of all PWM outputs can be aligned, and the SR delay can be applied separately as a constant dead time.

ADAPTIVE DEAD TIME CONTROL

A set of registers called the adaptive dead time (ADT) registers (Register 0x68 to Register 0x70) allows the dead time between PWM edges to be adapted on the fly. The ADP1046 uses the ADT only when the modulation is below the dead time (primary current) threshold programmed in Register 0x68. The Analog Devices software GUI allows the user to easily program the dead time values, and it is recommended that the GUI be used for this purpose.

Before ADT is configured, the primary current threshold must be programmed. Each individual PWM rising and falling edge (t

to t14) can then be programmed to have a specific dead time

offset at no load (zero current).

Rev. A | Page 19 of 96

This offset can be positive or negative and is relative to the nominal edge position. When the CS1 current is between zero and the current threshold, the amount of dead time is linearly adjusted in steps of 5 ns. The averaging period of the CS1 current and the speed of the dead time adjustment can also be programmed in Register 0x70 to accommodate faster or slower adjustment.

For example, if the CS1 threshold is set to 2 A, t rising edge of 100 ns. If the ADT setting for t t

moves to 140 ns when the current is 0 A and to 120 ns when

has a nominal

is 40 ns at no load,

the current is 1 A. Similarly, ADT can be applied in the negative direction.

LIGHT LOAD MODE

The ADP1046 can be configured to disable PWM outputs under light load conditions based on the value of CS2. Register 0x3B and Register 0x7D are used to program the light load mode thresholds for turn-off and turn-on of SR1, SR2, and other PWM outputs. Below the light load threshold programmed in Register 0x3B, the SR outputs are disabled; the user can also program any of the other PWM outputs to shut down below this threshold. Light load mode allows the ADP1046 to be used with interleaved topologies that incorporate automatic phase shedding at light load.

To prevent the system from oscillating between light load and normal modes due to the thresholds being programmed too close to each other, a programmable debounce is provided in Register 0x7D[5:4]. This debounce prevents the part from changing state within the programmed interval.

The speed of the SR enable is programmable from 37.5 µs to 300 µs in four discrete steps using Register 0x7D[3:2]. This ensures that, in case of a load step, the SR signals (and any other PWM outputs that are temporarily disabled) can be turned on quickly enough to prevent damage to the FETs that they are controlling.

The light load mode digital filter is also used during light load mode.

MODULATION LIMIT

The modulation limit register (Register 0x2E) can be programmed to apply a maximum duty cycle modulation limit to any PWM signal, thus limiting the modulation range of any PWM output. When modulation is enabled, the maximum modulation limit is applied to all PWM outputs collectively. As shown in Figure 21, this limit is the maximum time variation for the modulated edges from the default timing, following the configured modulation direction. There is no minimum duty cycle limit setting. Therefore, the user must set the rising edges and falling edges based on the case with the least modulation.

Figure 21. Modulation Limit Settings

ADP1046 Data Sheet

10045-119

Each LSB in Register 0x2E corresponds to a different time step size, depending on the switching frequency (see Tab l e 46). The modulated edges cannot extend beyond one switching cycle.

The GUI provided with the ADP1046 is recommended for programming this feature (see Figure 22).

Figure 22. Setting Modulation Limits (Modulation Range Shown by Arrows)

SOFT START

The turning on and off of the ADP1046 is controlled by the hardware PSON pin and/or the software PSON register, depending on the configured settings in Register 0x2C. When the user turns on the power supply (enables PSON), the following soft start procedure occurs (see Figure 23).

1. The PSON signal is enabled at Time t

programmed to be always on (Register 0x2C[7:6] = 00), PSON is enabled as soon as VCORE is above UVLO.

2. The ADP1046 waits for the programmed PS_ON delay

(set in Register 0x2C[4:3]).

3. The soft start begins to ramp up the internal digital refer-

ence. The total duration of the soft start ramp is programmable from 5 ms to 100 ms using Register 0x5F[7:5].

4. If the soft start from precharge function is enabled

(Register 0x5F[4] = 1), the soft start ramp starts from the value of the output voltage sensed on VS1 or VS3± (depending on the OrFET status), and the soft start ramp time is reduced proportionally. If the soft start from precharge function is disabled, the soft start ramp time is the programmed value in Register 0x5F[7:5].

5. When the power supply voltage exceeds the VS1 under-

voltage protection (UVP) limit (set in Register 0x34[6:0]), the UVP flag is reset.

6. The OrFET is turned on as soon as the OrFET enable thresh-

old is met. (The OrFET enable threshold is programmed in Register 0x30[6:5].) The regulation point is switched from VS1 to VS3±.

7. If no other fault conditions are present, the PGOODx

signals wait for the programmed debounce time (set in Register 0x2D[7:4]) and are then enabled. The soft start flag must be unmasked in Register 0x7B and Register 0x7C (Bit 7 must be set to 0).

8. If no OrFET is used, the power supply must be configured

to regulate using VS3 at all times (Register 0x33[2] = 1). VS2 can be used as a secondary OVP mechanism.

. If the part is

Fault Condition During Soft Start

If a fault condition occurs during soft start, the controller responds as programmed unless the flag is blanked. Flag blanking during soft start is programmed in Register 0x0F. The UVP and ACSNS flags are always blanked during soft start. The OTP, FLAGIN, OVP, and OCP fault flags can be blanked during soft start by setting the appropriate bits in Register 0x0F.

Digital Compensation Filters During Soft Start

The ADP1046 has a dedicated soft start filter (SSF) that can be used to fine-tune and optimize the dynamic response during the output voltage ramp-up.

Before it ramps up the internal reference after the PSON signal is enabled, the ADP1046 evaluates whether the OrFET should be turned on or off by looking at the difference between VS1 and VS2. This step is done to determine whether the regulation point should be VS1 or VS3± (see Figure 23).

• If the regulation point is VS1, the soft start filter is used

by default during the ramp-up. At the end of the soft start ramp, the part switches to the normal mode filter (NMF).

• If the regulation point is VS3±, the part starts the ramp

using the normal mode filter (NMF).

In both cases, after the voltage reaches 12.5% of the nominal output voltage value, the load current is evaluated.

• If the load current is below the light load mode threshold,

the part switches to the light load mode filter (LLF).

• If the load current is above the light load mode threshold,

the normal mode filter is used until the end of the soft start ramp, even if the system subsequently enters light load mode based on a change to the load current.

• Force soft start filter (Bit 0). This option forces the part to

use the soft start filter even when the regulation point is VS3. In some cases, this option allows better fine-tuning of the ramp-up voltage. This option can also be selected when an OrFET is not used.

• Disable light load mode during soft start (Bit 1). This

option prevents the use of the light load mode filter during soft start, even if the light load condition is met. The light load mode filter is available for use after the end of the soft start ramp.

Rev. A | Page 20 of 96

Data Sheet ADP1046

OrFET E NABLE

UVP

PSON

VS3

VS1

(VS1 – VS2)

VOLTAGE

OrFET GATE

LOOP CONTROLLED

FROM VS1

LOOP CONTROLLED

FROM VS3

UVP FLAG

PGOOD1

PS_ON DELAY

(REG 0x2C[4:3])

RAMP TIME

(REG 0x5F[7: 5] )

PGOOD DE BOUNCE

(REG 0x2D)

10045-120

PSON

OUT

RAMP TIME

(REG 0x5F[7: 5] )

12.5% REF

LIGHT LOAD FILTER (LLF)

NORMAL MODE FILTER (NMF)

OR SOFT START FILTER (SSF)

NORMAL MODE FILTER (NMF) OR SOFT START FILTER (SSF)

NORMAL MODE FILTER (NMF)

OR SOFT START FILTER (SSF)

LLF OR NMF BASED ON LOAD

10045-121

Figure 23. Soft Start Timing Diagram

Figure 24. Filter Sequencing at Startup

Rev. A | Page 21 of 96

ADP1046 Data Sheet

FAST OrFET

COMPARATOR

FAST OrFET THRESHOLD

OrFET

DISABLE

CS2– CS2+

12V

11kΩ

1kΩ

OUT

VS2VS1

SENSE

GATE

FAST OrFET

BYPASS

FAST OrFET

DEBOUNCE

OrFET

ENABLE

OrFET

ENABLE THRES HOLD

FLAGS

DRIVER

DEBOUNCE

GATE

DISABLE

10045-122

ORFET CONTROL (GATE)

The GATE control signal drives an external OrFET. The OrFET is used in redundant systems to protect against power flow into the power supply from another supply’s output terminals. This ensures that power flows only out of the power supply and that the unit can be hot-swapped.

The GATE pin is a totem-pole output and does not require a pull-up resistor. The GATE pin polarity can be programmed via Register 0x2D[1] to be active high or active low. The GATE output is CMOS level (0 V to 3.3 V). An external driver is required to turn the OrFET on or off.

OrFET Turn-On

The turn-on process for the OrFET is controlled by the voltage difference between VS1 and VS2. For this reason, the VS1 and VS2 readings must be correctly calibrated for the OrFET function to perform properly.

The OrFET turn-on circuit detects the voltage difference between VS1 and VS2 (see Figure 25). When the forward voltage drop from VS1 to VS2 is greater than the programmable OrFET enable threshold set in Register 0x30[6:5], the OrFET is enabled. The OrFET enable threshold can be set to 0%, −0.5%, −1%, or −2% of the nominal output voltage.

OrFET Turn-Off

The OrFET can be turned off by three methods:

• Fault flag. Any flag in a fault configuration register

(Register 0x08 to Register 0x0D) can be programmed with an action to turn off the OrFET. The OrFET is kept off for as long as the flag is set.

• OrFET programmable comparator. If the reverse voltage

present on CS2± exceeds the analog comparator threshold programmed in Register 0x30[4:2], the OrFET is turned off. This comparator can be disabled using Register 0x30[0].

• GATE signal disable. When Register 0x5D[0] = 1, the

GATE signal is disabled and has no effect on the VSx feedback point.

OrFET GATE Control and Regulation Points

The GATE signal is enabled when the threshold configured in Register 0x30[6:5]) is met. The GATE signal controls a very important function of output voltage regulation: the control loop sensing point.

• When the GATE signal is disabled, the OrFET is turned off

and the voltage regulation sensing point is VS1.

• When the GATE signal is enabled, the OrFET is turned on

and the voltage regulation sensing point is VS3±.

Recommended Setup for a 12 V Application

In normal operating mode, follow this procedure:

• When 12 V < V

< OVP, use the fast OrFET control

OUT

circuit to turn off the Or FE T.

• When V

> OVP, use load OVP to turn off the OrFET.

OUT

In light load mode, follow this procedure:

• When 12 V < V

< OVP, use ACSNS to turn off the

OUT

OrF ET.

• When V

> OVP, use load OVP to turn off the OrFET.

OUT

In a 12 V application, when an internal short circuit occurs, use CS1 OCP or VS1 UVP to shut down the unit and restart it.

Figure 25. OrFET Control Circuit Internal Detailed Diagram

Rev. A | Page 22 of 96

Data Sheet ADP1046

CH2 2.00V CH4 10.0V

CH1 2.00V CH3 2.00A

M10.0ms A CH4 100mV

CS2

VS3

VS1

OrFET

10045-017

CH2 2.00V CH4 10.0V

CH1 2.00V CH3 2.00A

M50.0ms A CH4 0mV

CS2

VS3

VS1

OrFET

10045-018

CH2 2.00V CH4 10.0V

CH1 2.00V CH3 2.00A

M200.0ms A CH4 7.5mV

CS2

VS3

OrFET

VS1

10045-019

CH2 2.00V CH4 10.0V

CH1 2.00V CH3 2.00A

M5.0ms A CH4 8.3mV

CS2

VS3

OrFET

VS1

10045-020

OrFET Operation Examples

Hot Plug into a Live Bus

A new PSU is plugged into a live 12 V bus (yellow). The internal voltage, VS1 (red), is ramped up before the OrFET is turned on. After the OrFET is turned on (green), current in the new PSU begins to flow to the load (blue). The turn-on voltage threshold between the new PSU and the bus is programmable.

Short Circuit

When one of the output rectifiers fails, the bus voltage can collapse if the OrFET is not promptly turned off. The fast OrFET comparator is used to protect the system from this fault event. Figure 28 shows a short circuit applied to the output capacitors before the OrFET. After the fast OrFET threshold for CS2± (blue) is triggered, the OrFET (green) is turned off. Figure 28 also shows the operation when the short circuit is removed. The internal regulation point, VS1 (red), returns to 12 V, and the OrFET (green) is reenabled. The PSU again begins to contribute current to the load (blue).

Figure 26. Hot Plug into a Live Bus (Yellow Is Bus Voltage; Red Is VS1 Voltage;

Green Is OrFET Control Signal; Blue Is Load Current)

Runaway Master

A rogue PSU on the bus (yellow) has a fault condition, causing the bus voltage to increase above the OVP threshold. The good PSU turns off the OrFET (green) and regulates its internal voltage, VS1 (red). When the rogue power supply fault condition is removed, the bus voltage decreases. The OrFET of the good PSU is immediately turned on, and the good PSU resumes regulating from VS3±.

Figure 28. Internal Short Circuit (Yellow Is Bus Voltage; Red Is VS1 Voltage;

Green Is OrFET Control Signal; Blue Is Load Current)

Light Load Mode Operation

PSU 1 increases its voltage at light load from 12 V to 12.1 V (yellow). Both PSU 1 and PSU 2 are CCM; therefore PSU 1 sources current and PSU 2 sinks current (blue). In PSU 2, the OrFET control turns off the OrFET to prevent reverse current from flowing. Note that the OrFET voltage (green) is solid during this transition because PSU 1 and PSU 2 are in CCM mode.

Figure 27. Runaway Master (Yellow Is Bus Voltage; Red Is VS1 Voltage;

Green Is OrFET Control Signal; Blue Is Load Current)

Figure 29. Light Load Mode (Yellow Is Bus Voltage; Red Is VS1 Voltage;

Green Is OrFET Control Signal; Blue Is Load Current)

Rev. A | Page 23 of 96

ADP1046 Data Sheet

PGOOD1 (FLAG AND P IN)

PGOOD2 (FLAG AND P IN)

ADDITIONAL FLAGS

-VOLTAGE CONTINUITY

-OrFET DISABLE

-ACSNS

-FLAGIN

-OTP

MASKED BY

REG 0x7B

MASKED BY

REG 0x7C

DEBOUNCE

(REG 0x2D[7:6])

DEBOUNCE

(REG 0x2D[5:4])

10045-127

MAIN FLAGS

-SOFT START

-CS1 FAST OCP

-CS1 ACCURATE OCP

-CS2 ACCURATE OCP

-UVP

-LOCAL OVP

(FAST AND ACCURAT E )

-LOAD OVP

-OrFET (GATE PIN)

IF REG 0x2D[ 3] = 0, THE ADDITIONAL FLAGS ALWAYS AFFECT PGOOD2, REGARDLESS OF THE PROGRAMME D ACTION. IF REG 0x2D[ 3] = 1, THE ADDITIONAL FLAGS AFFECT PGOOD2 ONLY IF THEY ARE NOT SET TO BE IGNORED.

VDD

When VDD is applied, a certain time elapses before the part is capable of regulating the power supply. When VDD rises above the power-on reset and UVLO levels, it takes approximately 20 μs for VCORE to reach its operational point of 2.5 V. T h e EEPROM contents are then downloaded to the registers. The download takes an additional 25 μs (approximately). After the EEPROM download, the ADP1046 is ready for operation.

If the ADP1046 is programmed to power up at this time (PSON is enabled), the soft start ramp begins. Otherwise, the part waits for the PSON signal.

The proper amount of decoupling capacitance must be placed between VDD and AGND, as close as possible to the device to minimize the trace length. It is recommended that the VCORE pin not be used as a reference or to generate other logic levels using resistive dividers.

VDD/VCORE OVLO

The ADP1046 has built-in overvoltage protection (OVP) on its supply rails. When the VDD or VCORE voltage rises above the OVLO threshold, the response can be programmed using Register 0x0E[7:5]. It is recommended that when a VDD/ VCORE OVP fault occurs, the response be set to download the EEPROM before restarting the part (set Register 0x0E[6] = 1).

POWER GOOD

The ADP1046 has two open-drain power-good pins. The PGOOD1 pin is driven low when a PGOOD1 fault condition is present; the PGOOD2 pin is driven low when a PGOOD2 fault condition is present. The PGOOD1 and PGOOD2 pins and flags can be programmed to respond to the following flags:

• Soft start

• CS1 fast OCP

• CS1 accurate OCP

• CS2 accurate OCP

• UVP

• Local OVP (fast and accurate)

• Load OVP

• OrFET (GATE pin )

The masking of these flags is programmed in Register 0x7B (for PGOOD1) and Register 0x7C (for PGOOD2). When a flag is masked, it does not set PGOOD1 or PGOOD2.

The following additional flags can also set the PGOOD2 pin either unconditionally or based on the flag response, as programmed in Register 0x2D[3] (see Figure 30 and Table 45).

• Voltage continuity

• OrFET disable

• ACSNS

• External flag (FLAGIN pin)

• OTP

These additional flags can be programmed in Register 0x2D[3] to always set PGOOD2 or to set PGOOD2 only if the flag action is not set to “ignore” in the fault configuration register for that flag (see Table 12 and Table 13).

Figure 30. PGOOD1, PGOOD2 Programming

Rev. A | Page 24 of 96

Data Sheet ADP1046

DIGITAL

WORD

BUS

CURRENT SENSE

INFO

SHAREi

SHAREo

POWER SUPPLY A

DIGITAL

WORD

CURRENT SENSE

INFO

SHAREi

SHAREo

POWER SUPPLY B

10045-023

CURRENT

SENSE

ADC

BUS

LPF

BIT STRE AM BIT STRE AM

SHAREo

VOLTAGE

CURRENT

CS2–CS2+

10045-222

8-BIT DATA

FRAME

START BIT

2 STOP BITS

(IDLE)

START BIT

2 STOP BITS

(IDLE)

NEXT FRAME

FRAME

10045-024

CURRENT SHARING (SHARE)

The ADP1046 supports both analog current sharing and digital current sharing. The ADP1046 can use either the CS1 current information or the CS2 current information for current sharing (this setting is programmed in Register 0x29[3]).

Analog Current Sharing

Analog current sharing uses the internal current sensing circuitry to provide a current reading to an external current error amplifier. Therefore, an additional differential current amplifier is not necessary.

The current reading from CS1 or CS2 can be output to the SHAREo pin in the form of a digital bit stream, which is the output of the current sense ADC (see Figure 32). The bit stream is proportional to the current delivered by this unit to the load. By filtering this digital bit stream using an external RC filter, the current information is turned into an analog voltage that is proportional to the current delivered by this unit to the load. This voltage can be compared to the share bus voltage. If the unit is not supplying enough current, an error signal can be applied to the VS3± feedback point. This signal causes the unit to increase its output voltage and, in turn, its current contribution to the load.

Digital Share Bus

The digital share bus scheme is similar in principle to the traditional analog share bus scheme. The difference is that instead of using a voltage on the share bus to represent current, a digital word is used.

The ADP1046 outputs a digital word onto the share bus. The digital word is a function of the current that the power supply is providing (the higher the current, the larger the digital word).

The power supply with the highest current controls the bus (master). A power supply that is putting out less current (slave) sees that another supply is providing more power to the load than it is.

During the next cycle, the slave increases its current output contribution by increasing its output voltage. This cycle continues until the slave outputs the same current as the master, within a programmable tolerance range. Figure 31 shows the configuration of the digital share bus.

Figure 31. Digital Current Share Configuration

The digital share bus is based on a single-wire communication bus principle; that is, the clock and data signals are contained together.

When two or more ADP1046 devices are connected, they synchronize their share bus timing. This synchronization is performed by the start bit at the beginning of a communications frame. If a new ADP1046 is hot-swapped onto an existing digital share bus, the device waits to begin sharing until the next frame. The new

ADP1046 monitors the share bus until it sees a stop bit, which

designates the end of a share frame. It then performs synchronization with the other ADP1046 devices during the next start bit. The digital share bus frame is shown in Figure 33.

Figure 32. Analog Current Share Configuration

Figure 33. Digital Current Share Frame Timing Diagram

Rev. A | Page 25 of 96

ADP1046 Data Sheet

LOGIC 1

LOGIC 0

IDLE

BIT

NEXT BIT

BIT

10045-025

CURRENT

SENSE

ADC

1 LSB = 29.3µV

35mV/29.3µV = 1195

MASTER

35mV

–

DIGITAL

WORD

DIGITAL

FILTER

÷16

12 BITS

1195 DEC

0x4AB

8 BITS

74 DEC

0x4A

SHAREi

CS2+

CS2–

SHARE BUS

8-BIT WORD

0xB5

8-BIT WORD

0x4A

SHAREo

OUT

= 35A

1mΩ

PSU A

10045-026

Figure 34 shows the possible signals on the share bus.

Figure 34. Share Bus High, Low, and Idle Bits

The length of a bit (t

) is fixed at 10 μs. A Logic 1 is defined as

BIT

a high-to-low transition at the start of the bit and a low-to-high transition at 75% of t

. A Logic 0 is defined as a high-to-low

BIT

transition at the start of the bit and a low-to-high transition at 25% of t

The bus is idle when it is high during the whole period of t All other activity on the bus is illegal. Glitches up to t

BIT

GLITC H

(200 ns) are ignored.

The digital word that represents the current information is eight bits long. The ADP1046 takes the eight MSBs of the CS1 or CS2 reading (the current share signal specified in Register 0x29[3]) and uses this reading as the digital word. When read, the share bus value at any given time is equal to the CS1 or CS2 current reading (see Figure 35).

Digital Share Bus Scheme

Each power supply compares the digital word that it is outputting with the digital words of all the other supplies on the bus.

Round 1

In Round 1, every supply first places its MSB on the bus. If a supply senses that its MSB is the same as the value on the bus, it continues to Round 2. If a supply senses that its MSB is less than the value on the bus, it means that this supply must be a slave.

When a supply becomes a slave, it stops communicating on the share bus because it knows that it is not the master. The supply then increases its output voltage in an attempt to share more current.

If two units have the same MSB, they both continue to Round 2 because either of them may be the master.

Round 2

In Round 2, all supplies that are still communicating on the bus place their second MSB on the share bus. If a supply senses that its MSB is less than the value on the bus, it means that this supply must be a slave and it stops communicating on the share bus.

Round 3 to Round 8

The same algorithm is repeated for up to eight rounds to allow supplies to compare their digital words and, in this way, to determine whether each unit is the master or a slave.

Digital Share Bus Configuration

The digital share bus can be configured in various ways. The bandwidth of the share bus loop is programmable in Register 0x29[2:0]. The extent to which a slave tries to match the current of the master is programmable in Register 0x2A[3:0]. The primary side or the secondary side current can be used as the current share signal by programming Register 0x29[3].

Figure 35. How the Share Bus Generates the Digital Word to Place on the Digital Share Bus

Rev. A | Page 26 of 96

Data Sheet ADP1046

POWER SUPPLY SYSTEM AND FAULT MONITORING

The ADP1046 has extensive system and fault monitoring capabilities. The system monitoring functions include voltage, current, power, and temperature readings. The fault conditions include out-of-limit values for current, voltage, power, and temperature. The limits for the fault conditions are programmable. The ADP1046 has an extensive set of flags that are set when certain programmed thresholds or limits are exceeded. These thresholds and limits are described in the Fault Registers section.

FLAGS

The ADP1046 has an extensive set of flags that are set when certain limits, conditions, and thresholds are exceeded. The real-time status of these flags can be read in Register 0x00 to Register 0x03. The response to these flags is individually programmable. Flags can be ignored or used to trigger actions such as turning off certain PWM outputs or the OrFET gate. Flags can also be used to turn off the power supply. The ADP1046 can be programmed to respond when these flags are reset. For more information, see the Fault Registers section.

The ADP1046 also has a set of latched fault registers (Register 0x04 to Register 0x07). The latched fault registers have the same flags as Register 0x00 to Register 0x03, but the flags in the latched registers remain set so that intermittent faults can be detected. Reading a latched fault register resets all the flags in that register.

MONITORING FUNCTIONS

The ADP1046 monitors and reports several signals, including voltages, currents, power, and temperature. All these values are stored in separate registers and can be read through the I

interface. For more information, see the Value Registers section.

VOLTAGE READINGS

The VS1, VS2, and VS3 ADCs have an input range of 1.6 V. The outputs of the ADCs are 12-bit values, which means that the LSB size is 1.6 V/4096 = 390.625 μV. The user is limited to an input range of 1.4 V, which means that the ADC output code is limited to 1.4 V/390.6 μV = 3584.

The equation to calculate the ADC code at a specified voltage (Vx) at the pin is given by the following formula:

ADC Code = Vx/1.6 × 4096

For example, when there is 1 V on the input of the ADC,

ADC Code = 1 V/1.6 × 4096

ADC Code = 2560

In a 12 V application, the 12 V reading is divided down using a resistor divider network to provide 1 V at the sense pin. Therefore, to convert the register value to a real voltage, use the following formula:

= (LSB × 2560) × ((R1 + R2)/R2)

OUT

In a 12 V system, this equates to

= (390.625 μV × 2560) × (11 kΩ + 1 kΩ)/1 kΩ

OUT

CURRENT READINGS

CS1 Pin

CS1 has an input range of 1.4 V. The ADC performs a 12-bit reading conversion of this value, which means that the LSB size is 1.4 V/4096 = 341.8 μV.

When there is exactly 1 V on the CS1 pin, the value in the CS1 value register (Register 0x13[15:4]) reads 2926.

The equation to calculate the ADC code at a specified CS1 input voltage (Vx) is given by the following formula:

ADC Code = Vx/1.4 × 4096

For example, when there is 1 V on the CS1 input pin,

ADC Code = 1 V/1.4 × 4096

ADC Code = 2926

CS2+, CS2− Pins

The full-scale (FS) range for the CS2 ADC can be set to 60 mV or 120 mV using Register 0x27[5].

The CS2 ADC has an input range of 120 mV. The resolution is 12 bits, which means that the LSB size is 120 mV/4096 = 29.30 μV. The user is limited to an input range of 110 mV.

The equation to calculate the ADC code at a specified voltage (V

) is given by the following formula:

ADC Code = Vx/(120 mV) × 4096

For example, when there is 50 mV on the input of the ADC,

ADC Code = 50 mV/120 mV × 4096

ADC Code = 1707

Therefore, to convert the CS2 register value to a real current, use the following formula:

= (CS2_ADC_CODE/4096) × (FS/R

OUT

where:

CS2_ADC_CODE is the value in Register 0x18[15:4]. FS is the full-scale voltage drop (60 mV or 120 mV). R

is the sense resistor value.

SENSE

For example, if CS2_ADC_CODE = 1520, R FS = 120 mV, the real current is calculated as follows:

= (1520/4096) × (120 mV/10 mΩ)

OUT

= 4.453 A

OUT

)

SENSE

= 10 mΩ, and

SENSE

Rev. A | Page 27 of 96

ADP1046 Data Sheet

ADC

DAC

RTD

EXT

10045-134

FLAGS

OTP

FLAG

OTP

THRESHOLD

REG 0x2F[7:0]

RTD TEMPERATURE

VALUE REGISTER

REG 0x1A[15:4]

RTD TEMPERATURE

VALUE IN °C

REG 0x1B[7:0]

SIGNAL

CONDITIONING

10µA/20µA/30µA/40µA

RTD

100kΩ

NTC

16.5kΩ

10045-027

RTD ADC

POWER READINGS

The output power value register (Register 0x19) is the product of the VS3 voltage value and the CS2 current value. Therefore, a combination of the formulas in the Voltage Readings section and the CS2+, CS2− Pins section is used to calculate the power reading in watts. This register is a 16-bit word. It multiplies two 12-bit numbers and discards the eight LSBs.

= V

× I

OUT

For example,

= 12 V × 4.453 A = 53.436 W

OUT

POWER MONITORING ACCURACY

The ADP1046 power monitoring accuracy is specified relative to the full-scale range of the signal that it is measuring.

FIRST FLAG FAULT ID AND VALUE REGISTERS

When the ADP1046 registers several fault conditions, it stores the value of the first fault in a dedicated register. For example, if the overtemperature (OTP) fault is registered followed by an OVP fault, the OTP flag is stored in the first flag ID register (Register 0x10). This register gives the user more information for fault diagnosis than a simple flag. The contents of this register are latched, meaning that they are stored until read by the user. The contents are also reset by toggling PSON. If a flag is set to be ignored, it does not appear in the first flag register.

EXTERNAL FLAG INPUT (FLAGIN PIN)

The FLAGIN pin can be used to send an external fault signal into the ADP1046. Register 0x0A[3:0] can be used to program the FLAGIN flag to trigger an action.

TEMPERATURE READINGS (RTD PIN)

The RTD pin is set up for use with an external negative temperature coefficient (NTC) thermistor. The RTD pin has an internal programmable current source. An ADC monitors the voltage on the RTD pin.

The RTD temperature value register, Register 0x1A, is updated every 10 ms. The ADP1046 stores every ADC sample for 10 ms and then outputs the average value at the end of the 10 ms period.

The RTD ADC has an input range of 1.6 V and a resolution of 12 bits, which means that the LSB size is 1.6 V/4096 = 390.625 µV. The user is limited to an input range of 1.3 V, which means that the maximum ADC output code is limited to 1.3 V/390.6 µV = 3328.

The output of the RTD ADC is linearly proportional to the voltage on the RTD pin. However, thermistors exhibit a nonlinear function of resistance vs. temperature. Therefore, the user must perform postprocessing on the RTD ADC reading to accurately read the temperature.

By connecting an external resistor (R

) in parallel with the

EXT

NTC thermistor (TH), a constant current can be used to achieve linearization (see Figure 36).

Figure 36. Temperature Measurement Using Thermistor

An internal, precision current source of 10 µA, 20 µA, 30 µA, or 40 µA can be selected in Register 0x11. This current source can be trimmed by means of an internal DAC to compensate for thermistor accuracy (see the RTD/OTP Trim section). The user can select the output current source using Bits[7:6] of Register 0x11.

The ADP1046 implements a linearization scheme based on a preselected combination of external components and current selection for best performance when measuring linearized temperatures in degrees Celsius in the industrial range.

For more information about the required thermistor and selecting and trimming the precision current sources, see the Temperature Linearization Scheme section.

Optionally, the user can process the RTD reading and perform postprocessing in the form of a lookup table or polynomial equation to match the specific NTC thermistor used. With the internal current source set to 46 µA, the equation to calculate the ADC code at a specified NTC thermistor value (Rx) is given by the following formula:

ADC CODE = 46 µA × Rx/1.6 × 4096

For example, at 60°C, the NTC thermistor at the RTD pin is

21.82 kΩ.

RTD_ADC_CODE = 46 µA × 21.82 kΩ/1.6 × 4096 = 2570

Figure 37. RTD Pin Internal Details

Rev. A | Page 28 of 96

Data Sheet ADP1046

OUTA

OUTD

OUTC

OUTB

CS1

ADC

1.2V

FAST OCP

COMPARATOR

CS1 FAST

OCP FLAG

PWM

CS1 ACCURATE

OCP FLAG

CYCLE-BY-CYCLE

SHUTDOWN

OUTA OUTB OUTC OUTD SR1 SR2 OUTAUX

FLAGS

CS1

FAST OCP

BYPASS

REG 0x27[4]

CS1

FAST OCP

DEBOUNCE

REG 0x27[7:6]

CS1 FAST OCP BLANKING

REG 0x22[7:5]

FLAGIN

CS1 ACCURATE

OCP SETTING REG 0x22[4:0]

SHUTDOWN

CYCLE

TIMEOUT

REG 0x27[1:0]

ASYNCHRONOUS

2.62ms AVERAGING

10045-135

Temperature Linearization Scheme

The ADP1046 implements a linearization scheme based on a preselected combination of thermistor (100 kΩ, 1%), external resistor (16.5 kΩ, 1%), and the 46 µA current source for best performance when linearizing measured temperatures in the industrial range.

The required NTC thermistor should have a resistance of 100 kΩ, 1%, such as the NCP15WF104F03RC (beta = 4250, 1%). It is recommended that 1% tolerance be used for both the resistor and beta values.

Reading the Linearized Temperature

Reading Register 0x1B (updated every 10 ms) returns the current temperature according to an internal linearization scheme. See Table 1 for the specified accuracy of these measurements. The temperature reading result is represented in 8-bit decimal format in °C; therefore, the temperature range for this reading is from 0°C to 255°C.

OVERTEMPERATURE PROTECTION (OTP)

If the temperature sensed at the RTD pin exceeds the threshold programmed in Register 0x2F, the OTP flag is set. The response to the OTP flag is programmable using Register 0x0B[7:4].

An RTD trim is required to make accurate temperature readings at the lower end of the RTD ADC range to account for tolerances in the NTC thermistor and the external resistor. This trim results in a more accurate measurement for determining the OTP threshold (see the RTD/OTP Trim section).

OVERCURRENT PROTECTION (OCP)

The ADP1046 has several OCP functions. CS1 and CS2± have separate OCP circuits to provide both primary and secondary side protection.

CS1 OCP

CS1 has two protection circuits: CS1 fast OCP and CS1 accurate OCP (see Figure 38).

CS1 Fast OCP

CS1 fast OCP is an analog comparator. When the voltage at the CS1 pin exceeds the (fixed) 1.2 V threshold, the CS1 fast OCP flag is set. A programmable blanking time can be set to ignore the leading edge current spike at the beginning of the current signal (leading edge blanking).

A debounce time can be programmed to improve the noise immunity of the OCP circuit. When the CS1 fast OCP comparator is set, the OUTA, OUTB, OUTC, and OUTD PWM outputs are immediately disabled for the remainder of the switching cycle. These outputs are reenabled at the start of the next switching cycle. This function cannot be bypassed.

CS1 Accurate OCP

CS1 accurate OCP is used for more precise control of overcurrent protection. With CS1 accurate OCP, the reading at the output of the CS1 ADC (Register 0x13) is compared to a programmable OCP limit. The CS1 accurate OCP value can be programmed from 0 to 31 decimal using Register 0x22[4:0]. If the CS1 reading exceeds the CS1 accurate OCP limit, the CS1 accurate OCP flag is set. The CS1 ADC is asynchronously sampled, and the readings are averaged every 2.62 ms to make a fault decision. The flag response is programmed in Register 0x08.

Figure 38. CS1 OCP Detailed Internal Schematic

Rev. A | Page 29 of 96

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ANALOG DEVICES ADP1046 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

TYPICAL APPLICATION CIRCUIT

TABLE OF CONTENTS

REVISION HISTORY

FUNCTIONAL BLOCK DIAGRAM

SPECIFICATIONS

Timing Diagram

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

SOLDERING

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

THEORY OF OPERATION

CURRENT SENSE

CS1 Operation (CS1)

CS2 Operation (CS2+, CS2−)

VOLTAGE SENSE AND CONTROL LOOP

ADCs

VS1 OPERATION (VS1)

VS2 OPERATION (VS2)

VS3 OPERATION (VS3+, VS3−)

VOLTAGE LINE FEEDFORWARD AND ACSNS

DIGITAL FILTER

Filter Transitions

PWM AND SYNC RECT OUTPUTS (OUTA, OUTB, OUTC, OUTD, OUTAUX, SR1, SR2)

SYNCHRONOUS RECTIFICATION

SR (SYNCHRONOUS RECTIFIER) DELAY

ADAPTIVE DEAD TIME CONTROL

LIGHT LOAD MODE

MODULATION LIMIT

SOFT START

Fault Condition During Soft Start

Digital Compensation Filters During Soft Start

ORFET CONTROL (GATE)

OrFET Turn-On

OrFET Turn-Off

OrFET GATE Control and Regulation Points

Recommended Setup for a 12 V Application

OrFET Operation Examples

Hot Plug into a Live Bus

Short Circuit

Runaway Master

Light Load Mode Operation

VDD/VCORE OVLO

POWER GOOD

CURRENT SHARING (SHARE)

Analog Current Sharing

Digital Share Bus

Digital Share Bus Scheme

Round 1

Round 2

Round 3 to Round 8

Digital Share Bus Configuration

POWER SUPPLY SYSTEM AND FAULT MONITORING

FLAGS

MONITORING FUNCTIONS

VOLTAGE READINGS

CURRENT READINGS

CS1 Pin

CS2+, CS2− Pins

POWER READINGS

POWER MONITORING ACCURACY

FIRST FLAG FAULT ID AND VALUE REGISTERS

EXTERNAL FLAG INPUT (FLAGIN PIN)

TEMPERATURE READINGS (RTD PIN)

Temperature Linearization Scheme

Reading the Linearized Temperature

OVERTEMPERATURE PROTECTION (OTP)

OVERCURRENT PROTECTION (OCP)

CS1 OCP

CS1 Fast OCP

CS1 Accurate OCP