ANALOG DEVICES ADP1043A Service Manual
Digital Controller for Isolated
T
FEATURES
Integrates all typical controller functions
Digital control loop
Remote and local voltage sense
Primary and secondary side current sense
PWM control
Synchronous rectifier control
Current sharing
Integrated programmable loop filter
2
I
C interface
Extensive fault detection and protection
Extensive programming
Fast calibration
EEPROM
Standalone or microcontroller control
APPLICATIONS
AC-to-DC power supplies
Isolated dc-to-dc power supplies
Redundant power supplies
Parallel power supplies
Server, storage, network, and communications infrastructure
Power Supply Applications
ADP1043A
GENERAL DESCRIPTION
The ADP1043A is a secondary side power supply controller IC
designed to provide all the functions that are typically needed in
an ac-to-dc or isolated dc-to-dc control application.
The ADP1043A is optimized for minimal component count,
maximum flexibility, and minimum design time. Features
include remote voltage sense, local voltage sense, primary and
secondary side current sense, pulse-width modulation (PWM)
generation, and hot-swap sense and control. The control loop is
digital with an integrated programmable digital filter. Protection
features include current limiting, ac sense, undervoltage lockout
(UVLO), and overvoltage protection (OVP).
The built-in EEPROM provides extensive programming of the
integrated loop filter, PWM signal timing, inrush current, and
soft start timing and sequencing. Reliability is improved through
a built-in checksum and redundancy of critical circuits.
A comprehensive GUI is provided for easy design of loop filter
characteristics and programming of the safety features. The
industry-standard I
toring and system test functions.
The ADP1043A is available in a 32-lead LFCSP and operates
from a single 3.3 V supply.
2
C bus provides access to the many moni-
TYPICAL APPLICATION CIRCUIT
PFC
AC
INPU
DRIVER
SR1 SR2 ACSNS PGND
CS1
OUTA
DRIVER
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
ADuM1410
OUTB
OUTC
OUTD
OUTAUX
RES RTDADD VCORE FLAGIN PSON PGOOD2 PGOOD1 SDA SCL VDD DGND AGND
DRIVER
GATE
CS2– CS2+
MICROCONTROLLER
Figure 1.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved.
VS1
VS2
V
DD
VS3+
VS3–
SHAREo
SHAREi
LOAD
08501-001
ADP1043A
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Typical Application Circuit ............................................................. 1
Revision History ............................................................................... 3
Functional Block Diagram .............................................................. 4
Specifications ..................................................................................... 5
Absolute Maximum Ratings ............................................................ 8
Thermal Resistance ...................................................................... 8
Soldering ........................................................................................ 8
ESD Caution .................................................................................. 8
Pin Configuration and Function Descriptions ............................. 9
Typical Performance Characteristics ........................................... 11
Theory of Operation ...................................................................... 12
Current Sense .............................................................................. 12
Voltage Sense and Control Loop .............................................. 13
ADCs ............................................................................................ 13
Digital Filter ................................................................................ 14
PWM and Sync Rect Outputs (OUTA, OUTB, OUTC,
OUTD, OUTAUX, SR1, SR2) ................................................... 14
Synchronous Rectification ........................................................ 15
Adaptive Dead Time Control.................................................... 15
Light Load Mode ........................................................................ 15
Modulation Limit ....................................................................... 15
OrFET Control (GATE) ............................................................ 15
VDD ............................................................................................. 18
VDD/VCORE OVLO ................................................................ 18
Power Good ................................................................................. 18
Soft Start ...................................................................................... 19
Current Sharing (Share) ............................................................ 20
Power Supply System and Fault Monitoring ............................... 22
Flags .............................................................................................. 22
Monitoring Functions ................................................................ 22
Voltage Readings ........................................................................ 22
Current Readings ........................................................................ 22
Power Readings ........................................................................... 23
Power Monitoring Accuracy ..................................................... 23
First Flag Fault ID and Value Registers ................................... 23
External Flag Input (FLAGIN Pin) .......................................... 23
Temperature Readings (RTD Pin) ............................................ 23
Overtemperature Protection (OTP) ........................................ 23
Overcurrent Protection (OCP) ................................................ 24
Constant Current Mode ............................................................ 25
Overvoltage Protection (OVP) ................................................. 25
Undervoltage Protection (UVP) .............................................. 25
AC Sense (ACSNS)..................................................................... 26
Volt-Second Balance .................................................................. 26
Load Line ..................................................................................... 26
Power Supply Calibration and Trim ............................................ 27
CS1 Trim ...................................................................................... 27
CS2 Trim ...................................................................................... 27
Voltage Calibration and Trim ................................................... 27
Output Voltage Setting (VS3+, VS3− Trim) ........................... 28
VS1 Trim ...................................................................................... 28
VS2 Trim ...................................................................................... 28
RTD/OTP Trim .......................................................................... 28
Layout Guidelines....................................................................... 28
Communication .............................................................................. 29
I2C Interface ................................................................................ 29
EEPROM ..................................................................................... 31
Software GUI .............................................................................. 32
Register Listing ............................................................................... 33
Detailed Register Descriptions ..................................................... 35
Fault Registers ............................................................................. 35
Value Registers ............................................................................ 38
Current Sense and Current Limit Registers ............................ 41
Voltage Sense Registers .............................................................. 46
ID Registers ................................................................................. 49
PWM and Synchronous Rectifier Timing Registers ............. 50
Digital Filter Programming Registers ...................................... 58
Adaptive Dead Time Registers ................................................. 60
EEPROM Registers .................................................................... 64
Resonant Mode Operation ............................................................ 65
Resonant Mode Enable .............................................................. 65
PWM Timing in Resonant Mode ............................................. 65
Synchronous Rectification in Resonant Mode ....................... 65
Adjusting the Timing of the PWM Outputs ........................... 66
Frequency Limit Setting ............................................................ 66
Feedback Control in Resonant Mode ...................................... 66
Soft Start in Resonant Mode ..................................................... 66
Rev. 0 | Page 2 of 72
ADP1043A
Light Load Operation (Burst Mode) ........................................ 66
OUTAUX in Resonant Mode .................................................... 66
Protections in Resonant Mode .................................................. 66
REVISION HISTORY
10/09—Revision 0: Initial Version
Resonant Mode Register Descriptions ..................................... 67
Outline Dimensions ........................................................................ 71
Ordering Guide ........................................................................... 71
Rev. 0 | Page 3 of 72
ADP1043A
The ADP1043A is a secondary side controller for switch mode
power supplies (SMPS). It is designed for use in isolated redundant applications. The ADP1043A integrates the typical functions
that are needed to control a power supply. These include
• Output voltage sense and feedback
• Digital loop filter compensation
• PWM generation
• Current sharing
• Current, voltage, and temperature sense
• OrFET control
• Housekeeping and I
2
C interface
• Calibration and trimming
The main function of controlling the output voltage is performed
using the feedback ADCs, the digital loop filter, and the PWM
block. The feedback ADCs use a multipath approach (patent
pending). The ADP1043A combines a high speed, low resolution
(fast and coarse) ADC and a low speed, high resolution (slow and
accurate) ADC. Loop compensation is implemented using the
digital filter. This PID (proportional, integral, derivative) filter is
implemented in the digital domain to allow easy programming
of filter characteristics, which is of great value in customizing
and debugging designs.
The PWM block generates up to seven programmable PWM
outputs for control of FET drivers and synchronous rectification
FET drivers. This programmability allows many traditional and
unique switching topologies to be realized.
A current share bus interface provides for parallel power supplies.
The part also has hot-swap OrFET sense and control for N + 1
redundant power supplies.
Conventional power supply housekeeping features, such as remote
and local voltage sense and primary and secondary side current
sense, are included. An extensive set of protections is offered,
including overvoltage protection (OVP), overcurrent protection
(OCP), overtemperature protection (OTP), undervoltage protection (UVP), ground continuity monitoring, and ac sense.
All these features are programmable through the I
2
C bus interface. This bus interface is also used to calibrate the power supply.
Other information, such as input current, output current, and
fault flags, is also available through the I
2
C bus interface.
The internal EEPROM can store all programmed values and
allows standalone control without a microcontroller. A free,
downloadable GUI is available that provides all the necessary
software to program the ADP1043A. For more information
about the GUI, contact Analog Devices, Inc., for the latest
software and a user guide.
The ADP1043A operates from a single 3.3 V supply and is
specified from −40°C to +85°C.
CS1
SR1
SR2
OUTA
OUTB
OUTC
OUTD
OUTAUX
VDD
VCORE
RES
AGND
VREF
ADC
PWM
ENGINE
UVLO
LDO
FUNCTIONAL BLOCK DIAGRAM
PGND
ADC
8kB
EEPROM
2
I
C
INTERFACE
VS1
VS2
ADC
OSC
CS2–
ADC
CS2+
ADC
ACSNS
DIGITAL
CORE
RTDADD
Figure 2.
ADC
PWM
GATE
VS3+
VS3–
SHAREo
SHAREi
PGOOD1
PGOOD2
FLAGIN
DGND
PSON
SCL
SDA
08501-002
Rev. 0 | Page 4 of 72
ADP1043A
SPECIFICATIONS
VDD = 3.3 V, TA = −40°C to +85°C, unless otherwise noted. FSR = full-scale range.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
SUPPLY
VDD V
IDD I
Power supply off (PSON is low) 15 mA
During EEPROM programming (40 ms) IDD + 8 mA
POWER-ON RESET
Power-On Reset VDD rising 3.05 V
UVLO VDD falling 2.75 2.85 2.95 V
UVLO Hysteresis 35 mV
OVLO 3.7 3.9 4.1 V
VCORE PIN
Output Voltage TA = 25°C 2.3 2.5 2.7 V
OSCILLATOR AND PLL
PLL Frequency RES = 49.9 kΩ 190 200 210 MHz
OUTA, OUTB, OUTC, OUTD,
OUTAUX, SR1, SR2 PINS
Output Low Voltage VOL Source current = 10 mA 0.4 V
Output High Voltage VOH Source current = 10 mA VDD − 0.4 V
Rise Time C
Fall Time C
AC SENSE PWM and resonant mode
Input Voltage Threshold 0.3 0.45 0.65 V
Propagation Delay
VS1, VS2, VS3 LOW SPEED ADC
Input Voltage Range VIN
Sampling Frequency f
Voltage Sense Measurement
Accuracy
−155 +155 mV
From 10% to 90% of input voltage range −2.5 +2.5 % FSR
−38.75 +38.75 mV
From 900 mV to 1.1 V −1.5 +1.5 % FSR
−23.25 +23.25 mV
Voltage Sense Measurement
Resolution
Voltage Differential from VS3−
to PGND
VS1 OVP Comparator Speed Register 0x2C[2] = 0 300 s
VS1 OVP Threshold Accuracy Relative to nominal voltage (1 V) on VS1 2.5 %
VS2 and VS3 OVP Comparator
Speed
VS2 and VS3 OVP Threshold
Accuracy
VS1 HIGH SPEED ADC
Sampling Frequency f
Resolution 6 Bits
Dynamic Range ±18 mV
3.1 3.3 3.6 V
DD
Normal operation (PSON is high) 20 mA
DD
= 50 pF 3.5 ns
LOAD
= 50 pF 1.5 ns
LOAD
From ACSNS threshold to SR start;
160 ns
resonant mode only
Differential voltage from VS1, VS2 to PGND,
0 1 1.55 V
and from VS3+ to VS3−
100 Hz
SAMP
From 0% to 100% of input voltage range −10 +10 % FSR
12 Bits
−200 +200 mV
Register 0x2C[2] = 0 300 s
Relative to nominal voltage (1 V) on VS2
2.5 %
and VS3
400 kHz
SAMP
Rev. 0 | Page 5 of 72
ADP1043A
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
CURRENT SENSE 1 (CS1 PIN)
Input Voltage Range VIN 0 1 1.38 V
Sampling Frequency f
Current Sense Measurement
Accuracy
−41.4 +41.4 mV
From 0% to 100% of input voltage range −10 +10 % FSR
−138 +138 mV
Current Sense Measurement
Resolution
CS1 Fast OCP Threshold 1.1 1.2 1.3 V
CS1 Fast OCP Speed 80 100 ns
CS1 Accurate OCP DC Accuracy From 10% to 90% of input voltage range −3.0 +3.0 % FSR
−41.4 +41.4 mV
CS1 Accurate OCP Speed 10 ms
Leakage Current 4.0 A
CURRENT SENSE 2 (CS2+, CS2−
PINS)
Input Voltage Range VIN Differential voltage from CS2+ to CS2− −100 +225 mV
ADC Input Voltage Range LSB = 61.04 V 0 225 mV
Sampling Frequency f
Current Sense Measurement
Accuracy
From 200 mV to 225 mV −15 +15 mV
−7.5 +7.5 % FSR
Current Sense Measurement
Resolution
CS2 Accurate OCP Accuracy From 0 mV to 200 mV −4 +4 mV
From 200 mV to 225 mV −15 +15 mV
−7.5 +7.5 % FSR
CS2 Accurate OCP Speed 10 ms
Current Sink (High Side) 100 A
Current Source (Low Side) 100 A
Common-Mode Voltage at the
CS2+ and CS2− Pins
GATE PIN (OPEN DRAIN)
Output Low Voltage VOL 0.4 V
OrFET PROTECTION (CS2+, CS2−) Low-side current sensing only
Accurate OrFET Threshold
Accuracy
Accurate OrFET Speed 10 ms
Fast OrFET Accuracy −25 mV setting −40 −25 −10 mV
−50 mV setting −70 −50 −30 mV
−75 mV setting −100 −75 −50 mV
−100 mV setting −125 −100 −75 mV
Fast OrFET Speed Debounce = 40 ns 110 150 ns
RTD PIN
Input Voltage Range VIN 0 1 1.55 V
Current Source RTD resistor = 100 kΩ 9.5 10.8 12 A
RTD ADC Measurement
Accuracy
From 32 mV to 320 mV −15.5 +15.5 mV
From 0% to 100% of input voltage range −10 +10 % FSR
From 0 V to 1.55 V −155 +155 mV
100 Hz
SAMP
From 10% to 90% of input voltage range −3.0 +3.0 % FSR
12 Bits
100 Hz
SAMP
From 0 mV to 200 mV −4 +4 mV
12 Bits
To achieve CS2 measurement accuracy 0.8 1 1.3 V
−1.2 0 +1 mV
From 2% to 20% of input voltage range −1 +1 % FSR
Rev. 0 | Page 6 of 72
ADP1043A
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
OTP Threshold Accuracy When RTD = 10 kΩ −0.5 +0.5 % FSR
−7.75 +7.75 mV
When RTD = 100 kΩ −5 +5 % FSR
−77.5 +77.5 mV
OTP Speed 10 ms
OTP Threshold Hysteresis When RTD = 10 kΩ 16 mV
PGOOD1, PGOOD2, SHAREo PINS
(OPEN DRAIN)
Output Low Voltage VOL 0.4 V
PSON, FLAGIN, SHAREi PINS
(DIGITAL INPUTS)
Input Low Voltage VIL 0.4 V
Input High Voltage VIH V
SDA/SCL PINS VDD = 3.3 V
Input Low Voltage VIL 0.4 V
Input High Voltage VIH V
Output Low Voltage VOL 0.4 V
Leakage Current −5 +5 µA
SERIAL BUS TIMING
Clock Frequency 100 400 kHz
Glitch Immunity tSW 50 ns
Bus-Free Time t
Start Setup Time t
Start Hold Time t
SCL Low Time t
SCL High Time t
SCL, SDA Rise Time tR 1000 ns
SCL, SDA Fall Time tF 300 ns
Data Setup Time t
Data Hold Time t
EEPROM RELIABILITY
1
Endurance
Data Retention
1
Endurance is qualified as per JEDEC Standard 22, Method A117, and is measured at −40°C, +25°C, +85°C, and +125°C.
2
Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Standard 22, Method A117. Retention lifetime derates with junction temperature.
2
− 0.8 V
DD
− 0.8 V
DD
4.7 µs
BUF
4.7 µs
SU;STA
4 µs
HD;STA
4.7 µs
LOW
4 µs
HIGH
250 ns
SU;DAT
300 ns
HD;DAT
10,000 Cycles
T
= 85°C 20 Years
J
Rev. 0 | Page 7 of 72
ADP1043A
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage (Continuous) VDD 4.2 V
Digital Pins −0.3 V to VDD + 0.3 V
VS3− to PGND, AGND, DGND −0.3 V to +0.3 V
RTD, VS1 to AGND 2.5 V
VS2, VS3+, ADD to AGND −0.3 V to VDD + 0.3 V
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
Peak Solder Reflow Temperature
SnPb Assemblies (10 sec to 30 sec) 240°C
RoHS-Compliant Assemblies
(20 sec to 40 sec)
ESD Charged Device Model 1.5 kV
ESD Human Body Model 3.5 kV
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
260°C
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type θJA θ
32-Lead LFCSP 44.4 6.4 °C/W
Unit
JC
SOLDERING
It is important to follow the correct guidelines when laying out
the PCB footprint for the ADP1043A and when soldering the
part onto the PCB. The AN-772 Application Note discusses this
topic in detail (see www.analog.com).
ESD CAUTION
Rev. 0 | Page 8 of 72
ADP1043A
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
RTD
VS3+
32
VDD
RES
ADD
VCORE
VS3–
31
30
DGND
29
28
27
26
25
14
OUTD
15
16
GATE
OUTAUX
24 SHAREi
23 SHAREo
22 PGOOD1
21 PGOOD2
20 FLAGIN
19 PSON
18 SDA
17 SCL
08501-003
1VS2
PIN 1
2AGND
INDICATOR
3VS1
4CS2–
TOP VIEW
5CS2+
(Not to S cal e)
6ACSNS
7CS1
8PGND
9
11
12
13
10
SR1
SR2
UTB
OUTA
O
OUTC
NOTES
1. THE ADP1043A HAS AN EXPOSED THERMAL PAD ON THE UNDERSIDE
OF THE PACKAG E . FOR INCREASED RELIABIL ITY OF THE SOLDER
JOINTS AND MAX IMUM THERMAL CAPABILITY , IT IS RECOMMENDED
THAT THE PAD BE S OLDERED TO THE PCB GROUND PL ANE .
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 VS2
Power Supply Output Sense Input. This signal is referred to PGND. Input to a low frequency Σ-∆ ADC. Nominal
voltage at this pin should be 1 V. The resistor divider on this input must have a tolerance specification of 0.5%
or better to allow for trimming.
2 AGND Analog Ground. This pin is the ground for the analog circuitry of the ADP1043A. Star connect to DGND.
3 VS1
Local Voltage Sense Input. This signal is referred to PGND. Input to a high frequency Σ-∆ ADC. Nominal voltage
at this pin should be 1 V. The resistor divider on this input must have a tolerance specification of 0.5% or
better to allow for trimming.
4 CS2−
Inverting Differential Current Sense Input. Nominal voltage at this pin should be 1 V for best operation. When
using high-side current sensing in a 12 V application, place a 110 kΩ resistor between the sense resistor and
this pin. When using low-side current sensing, place a 10 kΩ resistor between the sense resistor and this pin.
When using high-side current sensing, use the formula R = (V
COMMONMODE
− 1)/100 A. A 0.1% resistor must be
used to connect this circuit.
5 CS2+
Noninverting Differential Current Sense Input. Nominal voltage at this pin should be 1 V for best operation.
When using high-side current sensing in a 12 V application, place a 110 kΩ resistor between the sense resistor
and this pin. When using low-side current sensing, place a 10 kΩ resistor between the sense resistor and this
pin. When using high-side current sensing, use the formula R = (V
COMMON MODE
− 1)/100 A. A 0.1% resistor must
be used to connect this circuit.
6 ACSNS
AC Sense Input. This input is connected upstream of the main inductor through a resistor divider network.
The nominal voltage for this circuit is 0.45 V. This signal is referred to PGND.
7 CS1
Primary Side Current Sense Input. This pin is the current transformer input to measure and control the primary
side current. This signal is referred to PGND. The resistors on this input must have a tolerance specification of
0.5% or better to allow for trimming.
8 PGND
Power Ground. This pin is the ground connection for the main power rail of the power supply. Star connect
to AGND.
9 SR1
Synchronous Rectifier Output. This PWM output connects to the input of a FET driver. This pin can be disabled
when not in use. This signal is referred to AGND.
10 SR2
Synchronous Rectifier Output. This PWM output connects to the input of a FET driver. This pin can be disabled
when not in use. This signal is referred to AGND.
11 OUTA PWM Output for Primary Side Switch. This pin can be disabled when not in use. This signal is referred to AGND.
12 OUTB PWM Output for Primary Side Switch. This pin can be disabled when not in use. This signal is referred to AGND.
13 OUTC PWM Output for Primary Side Switch. This pin can be disabled when not in use. This signal is referred to AGND.
14 OUTD PWM Output for Primary Side Switch. This pin can be disabled when not in use. This signal is referred to AGND.
15 OUTAUX Auxiliary PWM Output. This pin can be disabled when not in use. This signal is referred to AGND.
16 GATE OrFET Gate Drive Output (Open Drain). This signal is referred to AGND.
17 SCL I2C Serial Clock Input. This signal is referred to AGND.
18 SDA I2C Serial Data Input and Output (Open Drain). This signal is referred to AGND.
Rev. 0 | Page 9 of 72
ADP1043A
Pin No. Mnemonic Description
19 PSON
20 FLAGIN Flag Input. An external signal can be input at this pin to generate a flag condition.
21 PGOOD2
22 PGOOD1
23 SHAREo
24 SHAREi Share Bus Feedback Pin. Connect this pin to the SHAREo pin. This signal is referred to AGND.
25 DGND Digital Ground. This pin is the ground for the digital circuitry of the ADP1043A. Star connect to AGND.
26 VCORE Output of 2.5 V Regulator. Connect a 100 nF capacitor from this pin to DGND.
27 VDD Positive Supply Input. Range is from 3.1 V to 3.6 V. This signal is referred to AGND.
28 RTD Thermistor Input. A 100 kΩ thermistor is placed from this pin to AGND. This signal is referred to AGND.
29 ADD Address Select Input. Connect a resistor from ADD to AGND. This signal is referred to AGND.
30 RES
31 VS3−
32 VS3+
Exposed
Pad
EP
Power Supply On Input. This signal is referred to DGND. This is the hardware PSON control signal. It is recommended that a 1 nF capacitor be included from the PSON pin to DGND for noise debounce and decoupling.
Power-Good Output (Open Drain). This signal is referred to AGND. This pin is controlled by the PGOOD2 flag.
This pin is set if any flag is set.
Power-Good Output (Open Drain). This signal is referred to AGND. This pin is controlled by the PGOOD1 flag.
This pin is set if any of the following are out of range: power supply, CS1 fast OCP, CS1 accurate OCP, CS2
a c cu ra te O CP, UV P, l oc al O V P, or lo ad OV P.
Share Bus Output Voltage Pin. Connect this pin to 3.3 V through a 2.2 kΩ resistor. When configured as a digital
share bus, this pin is a digital output. This signal is referred to AGND.
Resistor Input. This pin sets up the internal voltage reference for the ADP1043A. Connect a 49.9 kΩ resistor
(±0.1%) from RES to AGND. This signal is referred to AGND.
Inverting Remote Voltage Sense Input. There should be a low ohmic connection to AGND. The resistor divider
on this input must have a tolerance specification of 0.5% or better to allow for trimming.
Noninverting Remote Voltage Sense Input. This signal is referred to VS3−. Use 0.1% resistors as the resistor
divider to connect this circuit. The resistor divider on this input must have a tolerance specification of 0.5%
or better to allow for trimming.
The ADP1043A has an exposed thermal pad on the underside of the package. For increased reliability of the
solder joints and maximum thermal capability, it is recommended that the pad be soldered to the PCB
ground plane.
Rev. 0 | Page 10 of 72
ADP1043A
TYPICAL PERFORMANCE CHARACTERISTICS
4
3
2
1
0
–1
–2
VS1 ADC ACCURACY (%FSR)
–3
MEAN MIN MAX MIN SPE C MAX SPEC
–4
–40–200 20406080
TEMPERATURE ( °C)
08501-004
4
3
2
1
0
–1
MEAN MIN MAX MIN SPEC MAX SPEC
–2
CS1 ADC ACCURACY (%FSR)
MIN_N10% MAX_P10%
–3
–4
–40 –20 0 20 40 60 80
TEMPERATURE (°C)
Figure 4. VS1 ADC Accuracy vs. Temperature (from 10% to 90% of FSR) Figure 7. CS1 ADC Accuracy vs. Temperature (from 10% to 90% of FSR)
4
3
2
1
0
6
4
2
0
08501-007
–1
–2
VS2 ADC ACCURACY (%FSR)
–3
MEAN MIN MAX MIN SPEC MAX SPEC
–4
–40 –20 0 20 40 60 80
TEMPERATURE (°C)
08501-005
–2
CS2 ADC ACCURACY (%FSR)
–4
MEAN MIN MAX MIN SPE C MAX SPEC
MIN_P10% MAX_P10% MAX_N10%
–6
–40 –20 0 20 40 60 80
TEMPERATURE ( °C)
Figure 5. VS2 ADC Accuracy vs. Temperature (from 10% to 90% of FSR) Figure 8. CS2 ADC Accuracy vs. Temperature (from 0 mV to 200 mV)
4
3
2
1
0
–1
–2
VS3 ADC ACCURACY (%FSR)
–3
MEAN MIN MAX MIN SPEC MAX SPEC
MIN_P10% MAX_N10%
–4
–40 –20 0 20 40 60 80
TEMPERATURE (°C)
08501-006
1.35
1.30
1.25
1.20
1.15
CS1 FAST OCP THRESHOLD (V )
1.10
MEAN MIN MAX MIN SPEC MAX SPEC
1.05
–40 –20 20040608
TEMPERATURE (°C)
0
08501-008
08501-009
Figure 6. VS3 ADC Accuracy vs. Temperature (from 10% to 90% of FSR) Figure 9. CS1 Fast OCP Threshold vs. Temperature
Rev. 0 | Page 11 of 72
ADP1043A
V
THEORY OF OPERATION
CURRENT SENSE
The ADP1043A has two individual current sense inputs: CS1
and CS2±. These inputs sense, protect, and control the output
current and the share bus information. They can be calibrated
to remove any errors due to external components.
CS1 Operation (CS1)
CS1 is typically used for the monitoring and protection of the
primary side current. This is commonly known as the current
transformer (CT) method of current sensing. The input signal
at the CS1 pin is fed into an ADC for current monitoring. The
range of the ADC is 0 V to 1.38 V. The input signal is also fed
into a comparator for fast OCP protection. The typical configuration for the current sense is shown in Figure 10.
IN
OUTA
OUTC
OUTB
OUTD
I = 10A
1kΩ 10Ω
1:100
Figure 10. Current Sense 1 (CS1) Operation
1V
I = 100mA
The comparator effectively measures peak current, and the
ADC effectively measures the average current information.
This information is available through the I
thresholds and limits can be set for CS1, such as OCP. These
thresholds and limits are described in the Current Sense and
Current Limit Registers section.
CS1
VREF
2
C interface. Various
ADC
12 BITS
FAST
OCP
CS2 Operation (CS2+, CS2−)
CS2± is used for the monitoring and protection of the secondary
side current. The full-scale range of the CS2 ADC is 225 mV. The
nominal full load voltage drop can be configured for 37.5 mV,
75 mV, or 150 mV. The differential inputs are fed into an ADC
through a pair of external resistors. When using low-side current
sensing, a 10 k resistor is required. When using high-side current
sensing, a 110 k resistor is required (for a 12 V application).
Low-side current sensing is recommended because it provides
improved performance compared with high-side current sensing.
High-side current sensing is not supported for applications
where the output voltage is above 20 V common mode. (There
is not enough offset trim range above 20 V common mode.)
Typical configurations are shown in Figure 11 and Figure 12.
Various thresholds and limits can be set for CS2, such as OCP.
These thresholds and limits are described in the Current Sense
and Current Limit Registers section.
When not in use, both CS2 inputs should be connected through
10 k resistors to PGND.
I
110kΩ 110kΩ
08501-010
1V
100µA 100µA
Figure 11. High-Side Resistive Current Sense
12V
CS2–CS2+
ADC
12 BITS
8501-011
I
10kΩ 10kΩ
CS2+CS2–
12 BITS
1V
100µA 100µA
Figure 12. Low-Side Resistive Current Sense (Recommended)
Rev. 0 | Page 12 of 72
ADC
08501-012
ADP1043A
VOLTAGE SENSE AND CONTROL LOOP
Multiple voltage sense inputs on the ADP1043A are used for the
monitoring, control, and protection of the power supply output.
The voltage information is available through the I
All voltage sense points can be calibrated digitally to remove
any errors due to external components. This calibration can be
performed in the production environment, and the settings can
be stored in the EEPROM of the ADP1043A (see the Power
Supply Calibration and Trim section for more information).
The update rate of the ADC from a control loop standpoint
is set to the switching frequency. Therefore, if the switching
frequency is set to 100 kHz, the ADC outputs a signal every
100 kHz to the control loop. Because the Σ- modulators of the
ADC sample at 1.6 MHz, the output of the ADC is the average
of the 16 readings taken during the 1.6 MHz time frame.
For voltage monitoring, the VS1, VS2, and VS3 voltage value
registers are updated every 10 ms. The ADP1043A stores every
ADC sample for 10 ms and then outputs the average value at the
end of the 10 ms period. Therefore, if these registers are read at
least every 10 ms, a true average value is read. The same applies
to the CS1 and CS2 current readings.
For the control loop, the high speed signal always comes from
the VS1 high speed ADC. The low speed signal normally comes
from the VS3 low speed ADC. However, during soft start or in
response to a load OVP or other fault condition, the ADP1043A
can switch its low speed regulating point from VS3 to VS1.
12V 12V
11kΩ11kΩ
1kΩ 1kΩ
VS2
ADCADC
VS3VS2
ADC
VS1
HIGH
SPEED
6 BITS
HIGH
FREQUENCY
FEEDBACK
LOOP
1V 1V
PGND
ADC
DIGITAL
FILTER
VS1
VS1
LOW
SPEED
12 BITS 12 BITS 12 BITS
LOW FREQUENCY
FEEDBACK LOO P
Figure 13. Voltage Sense Configuration
2
C interface.
11kΩ
VS3+
1V
1kΩ
VS3–
LOAD
12V
08501-013
VS1 Operation (VS1)
VS1 is used for the monitoring and protection of the power
supply voltage at the output of the LC stage, upstream of the
OrFET. This is also the high frequency feedback loop for the
power supply. The VS1 sense point on the power rail needs an
external resistor divider to bring the nominal common-mode
signal to 1 V at the VS1 pin (see Figure 13). The resistor divider
is necessary because the ADP1043A VS1 ADC input range is
0 V to 1.55 V. This divided-down signal is internally fed into a
high speed and a low speed Σ- ADC. The output of the VS1
ADCs goes to the digital filter.
The high speed ADC has a 2 MHz bandwidth and is run from
a 25 MHz clock. It has a range of ±18 mV. When the sampling
rate is 200 kHz, there is 0.6 mV (two LSBs) of quantization noise.
Increasing the sampling rate to 400 kHz increases the quantization noise to 1.2 mV.
In the event of a load overvoltage condition, the power supply
is regulated from the VS1 sense point, rather than from the
VS3 sense point.
VS2 Operation (VS2)
VS2 is typically used for the monitoring and protection of the
output of the power supply, downstream of the OrFET. It is
used with VS1 to control the OrFET gate drive turn-on. The
VS2 sense point on the power rail needs an external resistor
divider to bring the nominal common-mode signal to 1 V at
the VS2 pin (see Figure 13). The resistor divider is necessary
because the ADP1043A VS2 ADC input range is 0 V to 1.55 V.
This divided-down signal is internally fed into an ADC. The
output of the VS2 ADC goes to the VS2 voltage value register
(Register 0x16).
VS3 Operation (VS3+, VS3−)
VS3± is used for the monitoring and protection of the remote
load voltage. It is a fully differential input. This is the main
feedback sense point for the power supply control loop. The
VS3 sense point on the power rail needs an external resistor
divider to bring the nominal common-mode signal to 1 V at
the VS3± pins (see Figure 13). The resistor divider is necessary
because the ADP1043A VS3 ADC input range is 0 V to 1.55 V.
This divided-down signal is internally fed into an ADC. The
output of the VS3 ADC goes to the digital filter.
ADCs
The ADP1043A includes several ADCs. The high speed ADC is
described in the VS1 Operation (VS1) section. The other ADCs
are low speed, high resolution. They have a 1 kHz bandwidth
and 12-bit resolution. Each ADC has its own voltage reference
for added protection from potential failure. The digital output
of each ADC is readable through the appropriate value register.
Rev. 0 | Page 13 of 72
ADP1043A
V
DIGITAL FILTER
The loop response of the power supply can be changed using
the internal programmable digital filter. A Type 3 filter architecture has been implemented. To tailor the loop response to
the specific application, the low frequency gain, zero location,
pole location, and high frequency gain can all be set individually
(see the Digital Filter Programming Registers section). It is
recommended that the Analog Devices software GUI be used to
program the filter. The software GUI displays the filter response
in Bode plot format and can be used to calculate all stability
criteria for the power supply.
From the sensed voltage to the duty cycle, the transfer function
of the filter in z-domain is as follows:
⎛
d
⎜
=
H(z)
⎜
⎝
×
m
where:
a = filter_pole_register_value/256.
b = filter_zero_register_value/256.
c = high_frequency_gain_register_value.
d = low_frequency_gain_register_value.
m = 1 when 48.8 kHz ≤ f
m = 2 when 97.7 kHz ≤ f
SW
SW
m = 4 when 195.3 kHz ≤ f
m = 8 when 390.6 kHz ≤ f
To go from z-domain to s-domain, plug the following equation
into the H(z) equation:
sf
+
2
SW
z(s)
where
=
2
f
is the switching frequency.
SW
SW
sf
−
The digital filter introduces an extra phase delay element into
the control loop. The digital filter circuit sends the duty cycle
information to the PWM circuit at the beginning of each switching cycle (unlike an analog controller, which makes decisions on
the duty cycle information continuously). Therefore, the extra
phase delay for phase margin, Φ, introduced by the filter block is
Φ = 180 × (f
C/fSW
)
where:
f
is the crossover frequency.
C
f
is the switching frequency.
SW
At one tenth of the switching frequency, the phase delay is 18°.
The GUI incorporates this phase delay into its calculations.
Two sets of registers allow for two distinct filter responses. The
main filter, called the normal mode filter, is controlled by
programming Register 0x60 to Register 0x63. The other filter,
called the light load mode filter, is controlled by programming
Register 0x64 to Register 0x67. The ADP1043A uses the light
load mode filter only when the modulation is below the load
current threshold (programmed through Register 0x3B).
⎞
z
⎟
×
⎟
−
z
⎠
< 97.7 kHz.
< 195.3 kHz.
< 390.6 kHz.
SW
.
SW
⎛
c
⎜
⎜
68.7124.202
⎝
⎞
bz
−
⎟
×+
(1)
⎟
az
−
⎠
The Analog Devices software GUI allows the user to program
the light load mode filter in the same manner as the normal
mode filter. It is recommended that the GUI be used for this
purpose.
In addition, during the soft start process, a different set of
digital filters is used. The soft start filter value for a, b, and c in
Equation 1 is 0, and the d value is programmed through the soft
start filter gain setting (Register 0x5F[1:0]).
PWM AND SYNC RECT OUTPUTS (OUTA, OUTB, OUTC, OUTD, OUTAUX, SR1, SR2)
The PWM and SR outputs are used for control of the primary
side drivers and the synchronous rectifier drivers. These outputs
can be used for several control topologies, including full-bridge,
phase-shifted ZVS, and interleaved two switch forward converter
configurations. Delays between rising and falling edges can be
individually programmed. Special care must be taken to avoid
shoot-through and cross-conduction. It is recommended that
the Analog Devices software GUI be used to program these
outputs. Figure 14 shows an example configuration to drive a
full-bridge, phase shift topology with synchronous rectification.
IN
OUTA OUTC
SR2
SR2
08501-014
SR1
OUTB OUTD
DRIVER
SR1
OUTA
DRIVER
ADuM1410
Figure 14. PWM Pin Assignment
OUTB
OUTC
OUTD
The PWM and SR outputs all work together. Therefore, when
reprogramming more than one of these outputs, it is important to
first update all the registers, and then latch the information into
the ADP1043A at one time. During reprogramming, the outputs
are temporarily disabled. A special instruction is sent to the
ADP1043A to ensure that new timing information is programmed
simultaneously. This is done by setting Register 0x5D[0] to 1. It is
recommended that PWM outputs be disabled when not in use.
OUTAUX is an additional PWM output pin; OUTAUX allows
an extra PWM signal to be generated at a different frequency
from the other six PWM outputs. This signal can be used to
drive an extra power converter stage, such as a buck controller
located in front of a full-bridge converter. OUTAUX can also be
used as a clock reference signal.
Rev. 0 | Page 14 of 72
ADP1043A
SYNCHRONOUS RECTIFICATION
SR1 and SR2 are recommended for use as the PWM control
signals when using synchronous rectification. These PWM
signals can be set up similarly to the other PWM outputs. The
turn-on of these signals can be programmed in two ways. They
can either be turned on to their full PWM value immediately, or
they can be turned on in a soft start fashion. When turned on
in a soft start, the signals ramp up from zero duty cycle to the
desired duty cycle. The advantage of ramping the SR signals is
to minimize a voltage step that would occur by turning the SR
FETs on completely. The advantage of turning the SR signals
completely on immediately is that they can help to minimize
the voltage transient caused by a load step.
Using Register 0x54[1], the SR soft start can be programmed to
occur just once, the first time that the SR signals are enabled, or
every time that the SR signals are enabled.
When programming the ADP1043A to use SR soft start, ensure
correct operation of this function by setting the falling edge of
) to a lower value than the rising edge of SR1 (t9) and by
SR1 (t
10
setting the falling edge of SR2 (t
rising edge of SR2 (t
).
11
) to a lower value than the
12
The speed of the SR enable is approximately 200 s. This ensures
that in case of a load step, the SR signals (and any other PWM
outputs that are temporarily disabled) can be turned on quickly
enough to prevent damage to the FETs that they are controlling.
ADAPTIVE DEAD TIME CONTROL
A set of registers called the adaptive dead time (ADT) registers
(Register 0x68 to Register 0x6F) allows the dead time between
PWM edges to be adapted on-the-fly. The ADP1043A uses the
ADT only when the modulation is below the dead time (load
current) threshold (programmed in Register 0x68). The Analog
Devices software GUI allows the user to easily program the
dead time values, and it is recommended that the software be
used for that purpose.
Each individual PWM rising and falling edge (t
to t14) can then
1
be programmed to have a specific dead time offset. This offset
can be positive or negative. The offset is relative to the nominal
edge position. For example, if t
100 ns and the ADT setting for t
has a nominal rising edge of
1
is −15 ns, t1 moves to 85 ns
1
when it falls below the adaptive dead time threshold. The dead
times are programmed using Register 0x69 to Register 0x6F.
LIGHT LOAD MODE
Register 0x3B allows the ADP1043A to shut down PWM
outputs under light load conditions. The light load current
threshold can be programmed. Below this current threshold,
the SR outputs are disabled. The user can also program any of
the other PWM outputs to shut down below this current threshold. This allows the ADP1043A to be used with an interleaved
two transistor forward topology, incorporating phase shedding
at light load. The light load mode digital filter is also used
during light load mode.
Rev. 0 | Page 15 of 72
MODULATION LIMIT
Using the modulation limit register (Register 0x2E), it is possible to
apply a maximum modulation limit and a minimum modulation
limit to any PWM signal, thus limiting the modulation range of
any PWM. These limits are a percentage of the switching period.
If the modulation required is lower than the minimum setting,
pulse skipping can be enabled.
Following is an example of how to use the modulation limit
settings. In this example, the switching cycle period is 4 s
and modulation on the t
nominal position of t
edge (falling edge) is enabled. The
2
is set to 1.6 s, which is 40% of the 4 s
2
period. The modulation high limit is set to (nominal + 50%).
Therefore, the modulation high limit is (40% + 50%) = 90% of
the switching cycle period; 90% of 4 s = 3.6 s. The modulation
low limit is set to (nominal − 35%). Therefore, the modulation
low limit is (40% − 35%) = 5% of the switching cycle period;
5% of 4 s = 0.2 s.
The GUI provided with the ADP1043A is recommended for
evaluating this feature of the ADP1043A (see Figure 15).
8501-015
Figure 15. Setting Modulation Limits (Modulation Range Shown by Arrows)
OrFET CONTROL (GATE)
The GATE control signal drives an external OrFET. The OrFET
gate control is used to protect against power flow into the power
supply from another supply. This ensures that power flows only
out of the power supply and that the unit can be hot-swapped.
The OrFET circuit can be used only when the ADP1043A is
connected to a sense resistor on the low side. The OrFET circuit
is not guaranteed for operation with high-side current sensing.
The GATE pin is an open-drain, N-channel MOSFET. An
external 2.2 kΩ pull-up resistor is recommended. Its output is
normally high to keep the OrFET turned off. When the start-up
criteria have been achieved, the GATE output is pulled low,
allowing the OrFET to turn on. The OrFET turn-on and turnoff thresholds can be individually programmed. The GATE
outputs are CMOS levels (0 V to 3.3 V). An external driver is
required to turn the OrFET on or off.
The OrFET can be turned off by three methods:
Fault flag (any fault flag can be programmed to turn off the
•
OrFET)
•
Fast OrFET control circuit
•
Accurate OrFET control circuit
Fast OrFET control looks at the reverse voltage across CS2+
and CS2− and is implemented using an analog comparator
(see Figure 16). If the voltage difference between CS2+ and
CS2− is greater than the fast OrFET threshold programmed
in Register 0x30, the OrFET is turned off.
ADP1043A
Accurate OrFET control also uses the reverse voltage across the
CS2+ and CS2− pins to disable the OrFET (see Figure 16). If the
voltage difference between CS2+ and CS2− is greater than 0 mV,
the OrFET is disabled. The accurate OrFET circuit is more accurate, but it is slower than the fast OrFET circuit.
The OrFET turn-on circuit looks at the voltage difference
between VS1 and VS2 (see Figure 16). When the forward
voltage drop from VS1 to VS2 is greater than the programmable OrFET enable threshold (Register 0x30[5:4]), the
OrFET is enabled. The OrFET enable threshold can be set to
−0.5%, 0%, 1%, or 2% of the nominal output voltage (12 V).
R
SENSE
10kΩ 10kΩ
11kΩ
1kΩ
Recommended Setup
In a 12 V application, while in normal operating mode
When 12 V < V
•
< OVP, use the accurate OrFET control
OUT
circuit to turn off the OrFET.
•
When V
> OVP, use load OVP to turn off the OrFET.
OUT
In a 12 V application, while in light load mode
When 12 V < V
•
< OVP, use ACSNS to turn off the
OUT
OrFET.
•
When V
> OVP, use load OVP to turn off the OrFET.
OUT
In a 12 V application, when an internal short circuit occurs,
follow this procedure:
1.
Use fast OrFET to turn off the OrFET.
Use CS1 OCP or VS1 UVP to shut down the unit and
2.
restart it.
12V
V
OUT
DRIVER
11kΩ
1kΩ
CS2– VS1 VS2CS2+
DIFFERENTIAL
TO SINGLE-
ENDED
DIFFERENTIAL
TO SINGLE-
ENDED
100µA 100µA
Figure 16. OrFET Control Circuit Internal Detailed Diagram
FAST OrFET
COMPARATOR
FAST OrFET
THRESHOLD
REG 0x30[3:2]
CS2 ADC
OrFET ENABLE
THRESHOLD
REG 0x30[5:4]
FAST OrFET
DEBOUNCE
REG 0x30[1]
ACCURATE OrFET
REG 0x30[7:6]
CS2 VALUE
REGISTER
REG 0x18[15:4]
THRESHOLD
OrFET
ENABLE
FAST OrFET
BYPASS
REG 0x30[0]
ACCURATE
OrFET
DISABLE
FLAG
SRQ
OrFET
DISABLE
FLAGS
GATE
08501-016
Rev. 0 | Page 16 of 72
ADP1043A
OrFET Operation Examples
Hot Plug into a Live Bus
A new PSU is plugged into a live 12 V bus (yellow). The internal
voltage VS1 (red) is ramped up before the OrFET is turned on.
After the OrFET is turned on (green), current in the new PSU
begins to flow to the load (blue). The turn-on voltage threshold
between the new PSU and the bus is programmable.
VS3
VS1
OrFET
4
Short Circuit
When one of the output rectifiers fails, the bus voltage can
collapse if the OrFET is not promptly turned off. The fast
OrFET comparator is used to protect the system from this fault
event. Figure 19 shows a short circuit applied to the output
capacitors, before the OrFET. After the fast OrFET threshold for
CS2 (blue) is triggered, the OrFET (green) is turned off. In this
case, the gate driver is not very fast and takes about 500 ns. (A
larger buffer to drive the OrFET would turn it off quicker.)
Figure 19 also shows the operation when the short circuit is
removed. The internal regulation point, VS1 (red), returns to
12 V, and the OrFET (green) is reenabled. The PSU again begins
to contribute current to the load (blue).
VS3
3
2
CH1 2.00V
CH3 2.00A
CS2
CH2 2.00V
CH4 10.0V
M10.0ms A CH4 100mV
08501-017
Figure 17. Hot Plug into a Live Bus (Yellow Is Bus Voltage; Red Is VS1 Voltage;
Green Is OrFET Control Signal; Blue Is Load Current)
Runaway Master
A rogue PSU on the bus (yellow) has a fault condition, and the
result is that the bus voltage increases above the OVP threshold.
The good PSU turns off the OrFET (green) and regulates its
internal voltage VS1 (red). When the rogue power supply fault
condition is removed, the bus voltage decreases. The OrFET of
the good PSU is immediately turned on and the good PSU
resumes regulating from VS3.
VS1
4
OrFET
VS3
CS2
CH1 2.00V
CH3 2.00A
OrFET
CH2 2.00V
CH4 10.0V
VS1
M200.0ms A CH4 7.5mV
08501-019
4
3
Figure 19. Internal Short Circuit (Yellow Is Bus Voltage; Red Is VS1 Voltage;
Green Is OrFET Control Signal; Blue Is Load Current)
Light Load Mode Operation
PSU 1 increases its voltage at light load from 12 V to 12.1 V
(yellow). Both PSU 1 and PSU 2 are CCM, so PSU 1 sources
current and PSU 2 sinks current (blue). In PSU 2, after 10 ms
the accurate OrFET control turns off the OrFET to prevent
reverse current from flowing. Note that the OrFET voltage
(green) is solid during this transition because PSU 1 and PSU 2
are in CCM mode.
VS1
VS3
3
CH1 2.00V
CH3 2.00A
CS2
CH2 2.00V
CH4 10.0V
M50.0ms A CH4 0mV
Figure 18. Runaway Master (Yellow Is Bus Voltage; Red Is VS1 Voltage;
Green Is OrFET Control Signal; Blue Is Load Current)
08501-018
Rev. 0 | Page 17 of 72
4
OrFET
3
CS2
CH1 2.00V
CH3 2.00A
CH2 2.00V
CH4 10.0V
M5.0ms A CH4 8.3mV
Figure 20. Light Load Mode (Yellow Is Bus Voltage; Red Is VS1 Voltage;
Green Is OrFET Control Signal; Blue Is Load Current)
08501-020
ADP1043A
VDD
When VDD is applied, a certain time elapses before the part is
capable of regulating the power supply. When the VDD rises
above the power-on reset and UVLO levels, it takes approximately 20 s for VCORE to reach its operational point of 2.5 V.
The EEPROM contents are then downloaded to the registers.
The download takes an additional 25 s (approximately). After
the EEPROM download, the ADP1043A is ready for operation.
If the ADP1043A is programmed to power up at this time, the
soft start ramp begins.
VDD/VCORE OVLO
The ADP1043A has built-in overvoltage protection (OVP) on
its supply rails. When the VDD or VCORE voltage rises above
the OVLO threshold, the response can be programmed. This
circuit can be set to be ignored, but it is recommended that the
user not program the OVP circuit to be ignored.
POWER GOOD
The ADP1043A has two power-good pins. The PGOOD1 pin
and fault flag are set when any of the following conditions are
out of range: power supply, CS1 fast OCP, CS1 accurate OCP,
CS2 accurate OCP, UVP, local OVP, or load OVP.
The PGOOD2 pin and fault flag are set when any flag is set:
power supply, OrFET, CS1 fast OCP, CS1 accurate OCP, CS2
accurate OCP, voltage continuity, UVP, accurate OrFET disable,
ACSNS, external flag (FLAGIN), VCORE OV, VDD OV, local
OVP, load OVP, OTP, CRC fault, and EEPROM unlocked.
If Register 0x2D[3] is set, PGOOD2 looks only at the flags that
are not programmed to be ignored.
The PGOOD2 pin can also be used as an interrupt pin to notify
a host controller that a flag has been set. The polarity of the
PGOOD1 and PGOOD2 pins is configured as active low.
Rev. 0 | Page 18 of 72
ADP1043A
The soft start begins to ramp up the power supply voltage
SOFT START
A dedicated filter is used during soft start. The filter is disabled
at the end of the soft start routine, and the voltage loop digital
filter is used.
Fault Condition During Soft Start
If a CS1 fast OCP fault condition occurs during soft start, the
entire soft start routine is reset, and the ADP1043A begins another
soft start routine. All other fault flags are ignored during soft start.
Soft Start Routine
When the user turns on the power supply (enables PSON), the
following soft start procedure occurs:
1.
The PSON signal is enabled at Time t
checks that initial flags are OK. These flags include VDD
OK and GND OK.
The ADP1043A waits for Time t
2.
The length of t
is set in Register 0x2C, Bits[4:3].
1
. The ADP1043A
0
before it begins soft start.
1
t
0
t
1
3.
at the start of Time t
The ADP1043A keeps the OrFET gate signal turned off.
4.
.
2
The voltage differential across the OrFET increases (VS1 −
VS2) due to the diode conduction of the OrFET. When the
voltage differential reaches the OrFET enable threshold
(Register 0x30, Bits[5:4]), the OrFET gate signal is enabled
at Time t
. The ADP1043A begins to regulate voltage from
3
VS3 instead of VS1.
After the power supply voltage increases above the VS1 UVP
5.
undervoltage limit (Register 0x34, Bits[6:0]), at the end of
, the UVP flag is reset.
Time t
4
After the UVP flag is reset and if all other PGOOD1 fault
6.
conditions are OK, the PGOOD1 signal waits for Time t
before it is enabled. The length of t
is programmable in
5
Register 0x2D, Bits[7:4].
t
3
t
2
t
4
t
5
5
PSON
SOFT START RAMP
V
VOLTAGE
OUT
(VS1 – VS2) VOLTAGE
GATE SIGNAL
LOOP CO NTROLLED FROM VS1
LOOP CO NTROLLED FROM VS3
UVP FLAG
PGOOD1
120mV
Figure 21. Soft Start Timing Diagram
UVP
08501-021
Rev. 0 | Page 19 of 72
ADP1043A
V
CURRENT SHARING (SHARE)
The ADP1043A supports both analog current sharing and
digital current sharing. It is recommended that analog current
sharing be used because it offers improved performance over
digital current sharing. Digital current sharing requires a load
line of >15 mΩ to prevent oscillation between units. The analog
current sharing scheme has no such issues.
Using Register 0x29, Bit 3, it is possible to program the
ADP1043A to use the CS1 current information or the CS2
current information for current sharing.
Analog Current Sharing
The ADP1043A supports analog current sharing. The current
reading from CS1 or CS2 can be output to the SHAREo pin in
the form of a digital bit stream, which is the output of the current
sense ADC (see Figure 23). The bit stream is proportional to the
current being delivered by this unit to the load. By filtering this
digital bit stream using an external RC filter, the current information is turned into an analog voltage. This means that there is
now an analog voltage that is proportional to the current being
delivered by this unit to the load. This voltage can be compared
to the share bus. If the unit is not supplying enough current, an
error signal can be applied to the VS3 feedback point. This signal
causes the unit to increase its output voltage and, therefore, its
current contribution to the load.
For more information about the analog current share functionality, including schematics and measurements in different fault
and setup conditions, see the product page for the ADP1043A.
Digital Share Bus
The digital share bus scheme is similar in principle to the traditional analog share bus scheme. The difference is that instead of
using a voltage on the share bus to represent current, a digital
word is used.
The ADP1043A outputs a digital word onto the share bus. The
digital word is a function of the current that the power supply is
providing (the higher the current, the larger the digital word).
CURRENT
The power supply with the highest current controls the bus
(master). A power supply that is putting out less current (slave)
sees that another supply is providing more power to the load
than it is. During the next cycle, the slave increases its current
output contribution by increasing its output voltage. This cycle
continues until the slave outputs the same current as the master,
within a programmable tolerance range. Figure 22 shows the
configuration of the digital share bus.
DD
SHAREi
CURRENT SENSE
INFO
POWER SUPPLY A
CURRENT SENSE
INFO
POWER SUPPLY B
DIGITAL
WORD
DIGITAL
WORD
SHAREo
SHAREi
SHAREo
SHARE
BUS
08501-023
Figure 22. Digital Current Share Configuration
The digital share bus is based on a single-wire communication
bus principle; that is, the clock and data signals are contained
together.
When two or more ADP1043A devices are connected, they
synchronize their share bus timing. This synchronization is
performed by the start bit at the beginning of a communications
frame. If a new ADP1043A is hot-swapped onto an existing
digital share bus, it waits to begin sharing until the next frame.
The new ADP1043A monitors the share bus until it sees a stop
bit, which designates the end of a share frame. It then performs
synchronization with the other ADP1043A devices during the
next start bit. The digital share bus frame is shown in Figure 24.
CS2–CS2+
LPF
VOLTAGE
08501-022
CURRENT
SENSE
ADC
SHARE
BIT STREAM BIT STREAM
BUS
SHAREo
Figure 23. Analog Current Share Configuration
2 STOP BI TS
(IDLE)
PREVIOUS
FRAME
START BIT
0
8-BIT DATA
FRAME
Figure 24. Digital Current Share Frame Timing Diagram
Rev. 0 | Page 20 of 72
2 STOP BIT S
(IDLE)
START BIT
0
NEXT FRAME
8501-024
ADP1043A
Figure 25 shows the possible signals on the share bus.
LOGIC 1
LOGIC 0
IDLE
PREVIOUS
BIT
t
0
t
1
NEXT
t
BIT
BIT
08501-025
Figure 25. Share Bus High, Low, and Idle Bits
The length of a bit (t
) is fixed at 10 s. A Logic 1 is defined as
BIT
a high-to-low transition at the start of the bit and a low-to-high
transition at 75% of t
. A Logic 0 is defined as a high-to-low
BIT
transition at the start of the bit and a low-to-high transition at
25% of t
The bus is idle when it is high during the whole period of t
All other activity on the bus is illegal. Glitches up to t
BIT
.
.
BIT
GLITCH
(200 ns) are ignored.
The digital word that represents the current information is eight
bits long. The ADP1043A takes the eight MSBs of the CS1 or CS2
reading (whichever the user chooses as the current share signal)
and uses this reading as the digital word. When read, the share
bus value at any given time is equal to the CS1 or CS2 current
reading (see Figure 26).
Digital Share Bus Scheme
Each power supply compares the digital word that it is outputting
with the digital words of all the other supplies on the bus.
Round 1
In Round 1, every supply first places its MSB on the bus. If a
supply senses that its MSB is the same as the value on the bus, it
continues to Round 2. If a supply senses that its MSB is less than
the value on the bus, it means that this supply must be a slave.
When a supply becomes a slave, it stops communicating on the
share bus because it knows that it is not the master. The supply
then increases its output voltage in an attempt to share more
current.
If two units have the same MSB, they both continue to Round 2,
because either of them could be the master.
Round 2
In Round 2, all supplies that are still communicating on the bus
place their second MSB on the share bus. If a supply senses that
its MSB is less than the value on the bus, it means that this
supply must be a slave and it stops communicating.
Round 3 to Round 8
The same algorithm is repeated for up to eight rounds to allow
supplies to compare their digital words and, in this way, to
determine whether each unit is the master or a slave.
Digital Share Bus Configuration
The digital share bus can be configured in various ways.
The bandwidth of the share bus loop is programmable in
Register 0x29[2:0]. The extent to which a slave tries to match
the current of the master can be selected by programming
Register 0x2A[3:0]. The primary side or the secondary side
can be used as the current share signal by programming
Register 0x29[3].
A load line may be required between PSUs when using a digital
share bus. A minimum impedance of 15 m is recommended
between the remote voltage sense node and the load.
I
OUT
= 35A
1mΩ
CS2+
CS2–
+
35mV
–
15.26µV = 1 LSB
CURRENT
SENSE
ADC
12-BIT
2293 DEC
0x8F5
PSU A
MASTER
DIGITAL
FILTER
÷16
35mV/15.26µ V = 229 3
8-BIT
143 DEC
0x8F
DIGITAL
WORD
0x8F
0x8F
SHAREi
SHAREo
8-BIT
WORD
V
DD
SHARE
BUS
8-BIT
WORD
0x8F
8501-026
Figure 26. How the Share Bus Generates the Digital Word to Place on the Digital Share Bus
Rev. 0 | Page 21 of 72
ADP1043A
POWER SUPPLY SYSTEM AND FAULT MONITORING
The ADP1043A has extensive system and fault monitoring
capabilities. The system monitoring functions include voltage,
current, power, and temperature readings. The fault conditions
include out-of-limit values for current, voltage, power, and temperature. The limits for the fault conditions are programmable.
The ADP1043A has an extensive set of flags that are set when
certain thresholds or limits are exceeded. These thresholds and
limits are described in the Fault Registers section.
FLAGS
The ADP1043A has an extensive set of flags that are set when
certain limits, conditions, and thresholds are exceeded. The
real-time status of these flags can be read in Register 0x00 to
Register 0x03. The response to these flags is individually
programmable. Flags can be ignored or used to trigger tasks
such as turning off certain PWM outputs or the OrFET GATE
output. Flags can also be used to turn off the power supply. The
ADP1043A can be programmed to respond when these flags are
reset. For more information, see Register 0x08 to Register 0x0D.
The ADP1043A also has a set of latched fault registers
(Register 0x04 to Register 0x07). The latched fault registers
have the same flags as Register 0x00 to Register 0x03, but the
flags in the latched registers remain set so that intermittent
faults can be detected. Reading a latched register resets all the
flags in that register.
MONITORING FUNCTIONS
The ADP1043A monitors and reports several signals, including
voltages, currents, power, and temperature. All these values are
2
stored in individual registers and can be read through the I
C
interface. See the Value Registers section for more details.
VOLTAGE READINGS
The VS1, VS2, and VS3 ADCs have an input range of 1.55 V.
The outputs of the ADCs are 12-bit values, which means that
the LSB size is 1.55 V/4096 = 378.4 V. The user is limited to an
input range of 1.5 V, which means that the ADC output code is
limited to 1.5 V/378.4 V = 3964.
The equation to calculate the ADC code at a certain voltage
(Vx) is given by the following formula:
ADC Code = Vx/378.4 V
For example, when there is 1 V on the input of the ADC
ADC Code = 1 V/378.4 V
ADC Code = 2643
In a 12 V application, the 12 V reading is divided down using
a resistor divider network to provide 1 V at the sense pin.
Therefore, to convert the register value to a real voltage, use
the following formula:
V
= (VSx_Voltage_Value/2643) × ((R1 + R2)/R2)
OUT
Rev. 0 | Page 22 of 72
In a 12 V system, this equates to
V
= (VSx_Voltage_Value/2643) × 12 V
OUT
CURRENT READINGS
CS1 Pin
DC Input Voltage
The CS1 ADC is identical in design to the VS1, VS2, and VS3
ADCs. Therefore, the description in the Vo lt a ge Re ad i ng s section
also applies to the CS1 ADC. When there is exactly 1 V on the
CS1 pin, the value in the CS1 value register (Register 0x13)
reads 2968.
CS1 has an input range of 1.38 V. The ADC performs a 12-bit
reading conversion on this value, which means that the LSB size
is 1.38 V/4096 = 337 V.
The equation to calculate the ADC code at a certain CS1 input
voltage (Vx) is given by the following formula:
ADC Code = Vx/337 V
For example, when there is 1 V on the CS1 input pin
ADC Code = 1 V/337 V
ADC Code = 2968
AC Input Voltage
CS1 often receives a rectified ac signal through a current
transformer. In this case, the ADC has a frequency response
(see Figure 27).
105
103
101
99
97
95
93
91
PERCENTAGE DEV IATION (%)
89
CS1 ADC FREQUENCY RESP ONSE
87
85
1k 10k 100k
To compensate for this frequency response, the multiplication
factor (M) should be used, as shown in the following equation:
M = (−2 × 10
where
−18
× f
f
is the switching frequency of the power supply.
SW
Using the multiplication factor (M) results in a more accurate
reading. This formula can be used by an MCU or other system
monitoring device. The ADP1043A GUI has the option to use
this formula.
CS1 INPUT FREQUENCY ( Hz)
Figure 27. CS1 ADC Frequency Response
3
) + (2 × 10
SW
−12
2
× f
) + (2 × 10−8 × fSW) + 0.9998
SW
08501-041
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