Analog Devices ADN8830 c Datasheet

Thermoelectric Cooler Controller

ADN8830

FEATURES
High Efficiency
Small Size: 5 mm  5 mm LFCSP
Low Noise: <0.5% TEC Current Ripple
Long-Term Temperature Stability: 0.01C
Temperature Lock Indication
Temperature Monitoring Output
Oscillator Synchronization with an External Signal
Clock Phase Adjustment for Multiple Controllers
Programmable Switching Frequency up to 1 MHz
Thermistor Failure Alarm
Maximum TEC Voltage Programmability

APPLICATIONS
Thermoelectric Cooler (TEC) Temperature Control
Resistive Heating Element Control
Temperature Stabilization Substrate (TSS) Control

FUNCTIONAL BLOCK DIAGRAM

PID COMPENSATION

NETWORK

FROM

THERMISTOR

TEMPERATURE

SET

INPUT

V

REF

TEMPERATURE

MEASUREMENT

AMPLIFIER

VOLTA G E

REFERENCE

PWM

CONTROLLER

OSCILLATOR

GENERAL DESCRIPTION

The ADN8830 is a monolithic controller that drives a thermo­electric cooler (TEC) to stabilize the temperature of a laser diode
or a passive component used in telecommunications equipment.

This device relies on a negative temperature coefficient (NTC)
thermistor to sense the temperature of the object attached to the
TEC. The target temperature is set with an analog input voltage
either from a DAC or an external resistor divider.

The loop is stabilized by a PID compensation amplifier with
high stability and low noise. The compensation network can be
adjusted by the user to optimize temperature settling time. The
component values for this network can be calculated based on
the thermal transfer function of the laser diode or obtained
from the lookup table given in the Application Notes section.

Voltage outputs are provided to monitor both the temperature of
the object and the voltage across the TEC. A voltage reference
of 2.5 V is also provided.

P-CHANNEL
(UPPER MOSFET)

MOSFET

DRIVERS

N-CHANNEL

P-CHANNEL
(LOWER MOSFET)

N-CHANNEL

FREQUENCY/PHASE

CONTROL

REV. C

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

ADN8830–SPECIFICATIONS

(@ VDD = 3.3 V to 5.0 V, V
configuration as shown in Figure 1, unless otherwise noted.)

= 0 V, TA = 25C, T

GND

= 25C, using typical application

SET

Parameter Symbol Conditions Min Typ Max Unit

TEMPERATURE STABILITY

Long-Term Stability Using 10 kΩ thermistor with

 = –4.4% at 25°C 0.01 °C

PWM OUTPUT DRIVERS

Output Transition Time t

, t

R

F

CL = 3,300 pF 20 ns
Nonoverlapping Clock Delay 50 65 ns
Output Resistance R
Output Voltage Swing OUT A V
Output Voltage Ripple OUT A f
Output Current Ripple I

(N1, P1) IL = 50 mA 6 Ω

O

TEC

= 0 V 0 V

LIM

= 1 MHz 0.2 %

CLK

f

= 1 MHz 0.2 %

CLK

DD

V

LINEAR OUTPUT AMPLIFIER

I

Output Resistance R

R

O, P2

O, N2

Output Voltage Swing OUT B 0 V

= 2 mA 85 Ω

OUT

I

= 2 mA 178 Ω

OUT

DD

V

POWER SUPPLY

Power Supply Voltage V

DD

Power Supply Rejection Ratio PSRR V

Supply Current I

Shutdown Current I
Soft-Start Charging Current I
Undervoltage Lockout V

SY

SD

SS

OLOCK

= 3.3 V to 5 V, V

DD

–40°C ≤ T

≤ +85°C60 dB

A

= 0 V 80 92 dB

TEC

PWM not switching 8 12 mA

–40°C ≤ T

≤ +85°C15mA

A

Pin 10 = 0 V 5 µA

Low-to-high threshold 2.0 2.7 V

3.0 5.5 V

15 µA

ERROR AMPLIFIER

Input Offset Voltage V
Gain A
Input Voltage Range V

OS

V, IN

CM

Common-Mode Rejection Ratio CMRR 0.2 V < V

Open-Loop Input Impedance R

IN

VCM = 1.5 V 50 250 µV

20 V/V

0.2 2.0 V

< 2.0 V 58 68 dB

–40°C ≤ T

CM

≤ +85°C55 dB

A

1GΩ

Gain-Bandwidth Product GBW 2 MHz

REFERENCE VOLTAGE

Reference Voltage V

REF

I

< 2 mA 2.37 2.47 2.57 V

REF

OSCILLATOR

Synchronization Range f
Oscillator Frequency f

CLK

CLK

Pin 25 connected to external clock 200 1,000 kHz

Pin 24 = VDD; (R = 150 kΩ; 800 1,000 1,250 kHz

Pin 25 = GND)

LOGIC CONTROL*

Logic Low Input Threshold 0.2 V
Logic High Input Threshold 3 V
Logic Low Output Level 0.2 V
Logic High Output Threshold VDD – 0.2 V

*Logic inputs meet typical CMOS I/O conditions for source/sink current (~1 µA).

Specifications subject to change without notice.

REV. C–2–

ADN8830

ABSOLUTE MAXIMUM RATINGS*

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . GND to V

+ 0.3 V

S

Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C

Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C

Package Type JA* 

JC

Unit

32-Lead LFCSP (ACP) 35 10 °C/W

*JA is specified for worst-case conditions, i.e., JA is specified for a device

soldered in a 4-layer circuit board for surface-mount packages.

Operating Junction Temperature . . . . . . . . . . . . . . . . . . 125°C

Lead Temperature Range (Soldering, 10 sec) . . . . . . . . 300°C

ESD RATINGS

883 (Human Body) Model . . . . . . . . . . . . . . . . . . . . . . 1.0 kV

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADN8830ACP –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP) CP-32-1
ADN8830ACP-REEL –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP) CP-32-1
ADN8830ACP-REEL7 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP) CP-32-1
ADN8830-EVAL Evaluation Board

PIN CONFIGURATION

32 NC

31 TEMPOUT

30 AGND

29 PHASE

28 SYNCOUT

27 SOFTSTART

26 FREQ

25 SYNCIN

THERMFAULT 1

THERMIN 2

SD 3

TEMPSET 4

TEMPLOCK 5

NC 6

VREF 7

AVDD 8

PIN 1
INDICATOR

ADN8830

TOP VIEW

P2 11

N2 10

OUT B 9

COMPFB 13

TEMPCTL 12

NC = NO CONNECT

15

VLIM

COMPOUT 14

24 COMPOSC
23 PGND
22 N1
21 P1
20 PVDD
19 OUT A
18 COMPSWIN
17 COMPSWOUT

VTEC 16

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADN8830 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

REV. C

–3–

ADN8830

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Type Description

1 THERMFAULT Digital Output Indicates an Open or Short-Circuit Condition from Thermistor.

2 THERMIN Analog Input Thermistor Feedback Input.
3 SD Digital Input Puts Device into Low Current Shutdown Mode. Active low.

4 TEMPSET Analog Input Target Temperature Input.
5 TEMPLOCK Digital Output Indicates when Thermistor Temperature is within ±0.1°C of Target Tem-

perature as Set by TEMPSET Voltage.

6NCNo Connection, except as Noted in the Application Notes Section.

7 VREF Analog Output 2.5 V Reference Voltage.

8 AVDD Power Power for Nondriver Sections. 3.0 V min; 5.5 V max.

9 OUT B Analog Input Linear Output Feedback. Will typically connect to TEC+ pin of TEC.

10 N2 Analog Output Drives Linear Output External NMOS Gate.

11 P2 Analog Output Drives Linear Output External PMOS Gate.

12 TEMPCTL Analog Output Output of Error Amplifier. Connects to COMPFB through feedforward

section of compensation network.

13 COMPFB Analog Input Feedback Summing Node of Compensation Amplifier. Connects to

TEMPCTL and COMPOUT through compensation network.

14 COMPOUT Analog Output Output of Compensation Amplifier. Connects to COMPFB through feed-

back section of compensation network.

15 VLIM Analog Input Sets Maximum Voltage across TEC.

16 VTEC Analog Output Indicates Relative Voltage across the TEC. The 1.5 V corresponds to 0 V

across TEC. The 3.0 V indicates maximum output voltage, maximum heat
transfer through TEC.

17 COMPSWOUT Analog Output Compensation for Switching Amplifier.

18 COMPSWIN Analog Input Compensation for Switching Amplifier. Capacitor connected between

COMPSWIN and COMPSWOUT.

19 OUT A Analog Input PWM Output Feedback. Will typically connect to TEC– pin of TEC.

20 PVDD Power Power for Output Driver Sections. 3.0 V min; 5.5 V max.

21 P1 Digital Output Drives PWM Output External PMOS Gate.

22 N1 Digital Output Drives PWM Output External NMOS Gate.

23 PGND Ground Power Ground. External NMOS devices connect to PGND. Can be

connected to digital ground as noise sensitivity at this node is not critical.

24 COMPOSC Analog Input Connect as Indicated in the Application Notes Section.

25 SYNCIN Digital Input Optional Clock Input. If not connected, clock frequency set by FREQ pin.

26 FREQ Analog Input Sets Switching Frequency.

27 SOFTSTART Analog Input Controls Initialization Time for ADN8830 with Capacitor to Ground.

28 SYNCOUT Digital Output Phase Adjusted Clock Output. Phase set from PHASE pin. Can be used to

drive SYNCIN of other ADN8830 devices.

29 PHASE Analog Input Sets Switching and SYNCOUT Clock Phase Relative to SYNCIN Clock.

30 AGND Ground Analog Ground. Should be low noise for highest accuracy.

31 TEMPOUT Analog Output Indication of Thermistor Temperature.

32 NC No Connection.

REV. C–4–

VDD = 5V

R

FREQ

(k)

1,000

800

0

01,500250 500 750 1,000 1,250

600

400

200

VDD = 5V
T

A

= 25C

SWITCHING FREQUENCY (kHz)

TA = 25C

VOLTA GE (1V/DIV)

0

000

VOLTA GE (1V/DIV)

P1

N1

00000000

TIME (20ns/DIV)

TPC 1. N1 and P1 Rise Time

P1

N1

Typical Performance Characteristics–ADN8830

360

SYNC IN = 200kHz
T

= 25C

A

320

280

240

200

160

120

PHASE SHIFT (Degrees)

80

40

0

VDD = 5V

= 25C

T

A

0

TPC 4. Clock Phase Shift vs. Phase Voltage

2.480

2.475

2.470

( V)

REF

V

2.465

2.460

VPHASE (V)

2.40.4 0.8 1.2 1.6 2.0

0

000

00000000

TIME (20ns/DIV)

TPC 2. N1 and P1 Fall Time

360

SYNC IN = 1MHz

= 25C

T

A

320

280

240

200

160

120

PHASE SHIFT (Degrees)

80

40

0

0

VPHASE (V)

TPC 3. Clock Phase Shift vs. Phase Voltage

2.455
–40 85–15

TPC 5. V

2.40.4 0.8 1.2 1.6 2.0

TPC 6. Switching Frequency vs. R

10 35 60

TEMPERATURE (C)

vs. Temperature

REF

FREQ

REV. C

–5–

ADN8830

1,000

VDD = 5V

= 150k

R

990

FREQ

980

970

960

950

940

SWITCHING FREQUENCY (kHz)

930

920

–40 85–15

10 35 60

TEMPERATURE (C)

TPC 7. Switching Frequency vs. Temperature

70

65

60

55

50

45

VDD = 5V

= 25C

T

40

A

USING CIRCUIT SHOWN IN FIGURE 1

35

30

25

20

15

SUPPLY CURRENT (mA)

10

5

0

200 1,000300 400 500 600 700 800 900

SWITCHING FREQUENCY (kHz)

TPC 10. Supply Current vs. Switching Frequency

2.06

2.05

2.04

45

OFFSET VOLTAGE (V)

40

35

30

–40 85–15

10 35 60

TEMPERATURE (C)

TPC 8. Offset Voltage vs. Temperature

200

100

0

–100

–200

OFFSET VOLTAGE (V)

–300

–400

02.00.2

0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
COMMON-MODE VOLTAGE (V)

TPC 9. Offset Voltage vs. Common-Mode Voltage

2.03

THERM FAULT UPPER THRESHOLD (V)

2.02
–40 85–15

10 35 60

TEMPERATURE (C)

TPC 11. Open Thermistor Fault Threshold vs. Temperature

0.26

0.25

0.24

THERM FAULT LOWER THRESHOLD (V)

0.23
–40 85–15

10 35 60

TEMPERATURE (C)

TPC 12. Short Thermistor Fault Threshold vs.
Temperature

REV. C–6–

ADN8830

APPLICATION NOTES
Principle of Operation

The ADN8830 is a controller for a TEC and is used to set and
stabilize the temperature of the TEC. A voltage applied to the
input of the ADN8830 corresponds to a target temperature
setpoint. The appropriate current is then applied to the TEC
to pump heat either to or away from the object whose tem­perature is being regulated. The temperature of the object is
measured by a thermistor and is fed back to the ADN8830 to
correct the loop and settle the TEC to the appropriate final
temperature. For best stability, the thermistor should be mounted
in close proximity to the object. In most laser diode modules,
the TEC and thermistor are already mounted in the unit and
are used to regulate the temperature of the laser diode.

A complete TEC controller solution requires:

• A precision input amplifier stage to accurately measure the

difference between the target and object temperatures.

• A compensation amplifier to optimize the stability and

temperature settling time.

• A high output current stage. Because of the high output

currents involved, a TEC controller should operate with
high efficiency to minimize the heat generated from
power dissipation.

In addition, an effective controller should operate down to 3.3 V
and have an indication of when the target temperature has been
reached. The ADN8830 accomplishes all of these requirements
with a minimum of external components. Figure 1 shows a
reference design for a typical application.

Temperature is monitored by connecting the measurement
thermistor to a precision amplifier, called the error amplifier,
with a simple resistor divider. This voltage is compared against
the temperature set input voltage, creating an error voltage that
is proportional to their difference. To maintain accurate wave­length and power from the laser diode, this difference voltage
must be as accurate as possible. For this reason, self-correction
auto-zero amplifiers are used in the input stage of the ADN8830,
providing a maximum offset voltage of 250 µV over time and
temperature. This results in final temperature accuracy within
±0.01°C in typical applications, eliminating the ADN8830 as an
error source in the temperature control loop. A logic output is
provided at TEMPLOCK to indicate when the target temperature
has been reached.

The output of the error amplifier is then fed into a compensa­tion amplifier. An external network consisting of a few resistors
and capacitors is connected around the compensation amplifier.
This network can be adjusted by the user to optimize the step

THERMFAULT

THERMIN

TEMPSET

TEMPLOCK

VREF

RTH

10k

@25C

3.3V

3.3V

VREF

10F

R2

7.68k

0.1%

R3

10k

0.1%

R4

7.68k

0.1%

C8

SYNCOUT

TEMPOUT

32 31 30 29 28 27 26 25

1

2

3

4

0.1F

C1

R1
150k

ADN8830

5

6

7

8

9

10 11

12 13 14 15 16

C9

10F

100k

R6

C10
330pF

C11
1F

R5

205k

R7

1M

VTEC

3.3V

24

23

22

21

20

19

18

17

10F

C5
10nF

C3

2.2nF

C6

Q1

FDW2520C-B

C4

22F

CDE ESRD

3.3V

3.3V

C7

10F

Q3
FDW2520C-A

Q4
FDW2520C-B

4.7H
COILCRAFT
DO3316-472

3.3V

L1

Q2
FDW2520C-A

C12

3.3nF

TEC–

C2
22F
CDE ESRD

TEC+

REV. C

Figure 1. Typical Application Schematic

–7–

ADN8830

response of the TEC’s temperature either in terms of settling time
or maximum current change. Details of how to adjust the compen­sation network are given in the Compensation Loop section.

The ADN8830 can be easily integrated with a wavelength locker
for fine-tune temperature adjustment of the laser diode for a
specific wavelength. This is a useful topology for tunable wave­length lasers. Details are highlighted in the Using the TEC
Controller ADN8830 with a Wave Locker section.

The TEC is driven differentially using an H-bridge configura­tion to maximize the output voltage swing. The ADN8830
drives external transistors that are used to provide current to the
TEC. These transistors can be selected by the user based on the
maximum output current required for the TEC. The maximum
voltage across the TEC can be set through use of the VLIM pin
on the ADN8830.

To further improve the power efficiency of the system, one side
of the H-bridge uses a switched output. Only one inductor and
one capacitor are required to filter out the switching frequency.
The output voltage ripple is a function of the output inductor
and capacitor and the switching frequency. For most applica­tions, a 4.7 µH inductor, 22 µF capacitor, and switching frequency
of 1 MHz maintains less than ±0.5% worst-case output voltage
ripple across the TEC. The other side of the H-bridge does not
require any additional circuitry.

The oscillator section of the ADN8830 controls the switched
output section. A single resistor sets the switching frequency
from 100 kHz to 1 MHz. The clock output is available at the
SYNCOUT pin and can be used to drive another ADN8830
device by connecting to its SYNCIN pin. The phase of the
clock is adjusted by a voltage applied to the PHASE pin, which
can be set by a simple resistor divider. Phase adjustment allows
two or more ADN8830 devices to operate from the same clock
frequency and not have all outputs switch simultaneously, which
could create an excessive power supply ripple. Details of how to
adjust the clock frequency and phase are given in the Setting the
Switching Frequency section.

For effective indication of a catastrophic system failure, the
ADN8830 alerts to open-circuit or short-circuit conditions from the
thermistor, preventing an erroneous and potentially damaging
temperature correction from occurring. With some additional
external circuitry, output overcurrent detection can be imple­mented to provide warning in the event of a TEC short-circuit
failure. This circuit is highlighted in the Setting Maximum
Output Current and Short-Circuit Protection section.

Signal Flow Diagram

Figure 2 shows the signal flow diagram through the ADN8830.
The input amplifier is fixed with a gain of 20. The voltage at

TEMPCTL can be expressed as

TEMPCTL TEMPSET THERMIN=×

()

+20 1 5– .

(1)

When the temperature is settled, the thermistor voltage will be
equal to the TEMPSET voltage, and the output of the input
amplifier will be 1.5 V.

The voltage at TEMPCTL is then fed into the compensation
amplifier whose frequency response is dictated by the compen­sation network. Details on the compensation amplifier can be
found in the Compensation Loop section. When configured as a

simple integrator or PID loop, the dc forward gain of the
compensation section is equal to the open-loop gain of the
compensation amplifier, which is over 80 dB or 10,000. The
output from the compensation loop at COMPOUT is then fed
to the linear amplifier. The output of the linear amplifier at
OUT B is fed with COMPOUT into the PWM amplifier whose
output is OUT A. These two outputs provide the voltage drive
directly to the TEC. Including the external transistors, the gain of
the differential output section is fixed at 4. Details on the output
amplifiers can be found in the Output Driver Amplifiers section.

1.5V

PWM/LINEAR
AMPLIFIERS

AV = 4

19

OUT A

OUT B

9

TEMPSET

THERMIN

4

2

INPUT
AMPLIFIER

AV = 20

12 13 14

TEMPCTL COMPOUT

COMPENSATION
AMPLIFIER

1.5V

Z1

COMPFB

A

V

= Z2/Z1

Z2

Figure 2. Signal Flow Block Diagram of the ADN8830

Thermistor Setup

The temperature of the thermal object, such as a laser diode, is
detected with a negative temperature coefficient (NTC) thermistor.
The thermistor’s resistance exhibits an exponential relationship to
the inverse of temperature, meaning the resistance decreases at
higher temperatures. Thus, by measuring the thermistor resistance,
temperature can be ascertained. Betatherm is a leading supplier
of NTC thermistors. Thermistor information and details can be
found at www.betatherm.com.

For this application, the resistance is measured using a voltage
divider. The thermistor is connected between THERMIN (Pin 2)
and AGND (Pin 30). Another resistor (R

) is connected between

X

VREF (Pin 7) and THERMIN (Pin 2), creating a voltage divider
for the VREF voltage. Figure 3 shows the schematic for this
configuration.

V

DD

8

7

R

X

2

ADN8830

R

THERM

30

Figure 3. Connecting a Thermistor to the ADN8830

With the thermistor connected from THERMIN to AGND, the
voltage at THERMIN will decrease as temperature increases.
To maintain the proper input-to-output polarity in this configu­ration, OUT A (Pin 19) should connect to the TEC– pin on the
TEC, and OUT B (Pin 9) should connect to the VTEC+ pin.

The thermistor can also be connected from VREF to THERMIN
with R

connecting to ground. In this case, OUT A must connect to

X

TEC+ with OUT B connected to TEC– for proper operation.

REV. C–8–